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| 32 www.renesas.com sh7014 hd6417014f28 hd6417014rf28 sh7016 hd6437016f28 sh7017 hd64f7017f28 rev.5.00 revision date: sep. 27, 2007 renesas 32-bit risc microcomputer superh tm risc engine family/sh7010 series sh7014, sh7016, sh7017f-ztat tm hardware manual rej09b0398-0500
rev.5.00 sep. 27, 2007 page ii of xxxiv rej09b0398-0500 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor g rants any license to any intellectual property ri g hts or any other ri g hts of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for dama g es or infrin g ement of any intellectual property or other ri g hts arisin g out of the use of any information in this document, includin g , but not limited to, product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples. 3. you should not use the products or the technolo g y described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exportin g the products or technolo g y described herein, you should follow the applicable export control laws and re g ulations, and procedures required by such laws and re g ulations. 4. all information included in this document such as product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to chan g e without any prior notice. before purchasin g or usin g any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay re g ular and careful attention to additional and different information to be disclosed by renesas such as that disclosed throu g h our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compilin g the information included in this document, but renesas assumes no liability whatsoever for any dama g es incurred as a result of errors or omissions in the information included in this document. 6. when usin g or otherwise relyin g on the information in this document, you should evaluate the information in li g ht of the total system before decidin g about the applicability of such information to the intended application. renesas makes no representations, warranties or g uaranties re g ardin g the suitability of its products for any particular application and specifically disclaims any liability arisin g out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi g ned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially hi g h quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considerin g the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for dama g es arisin g out of the uses set forth above. 8. notwithstandin g the precedin g para g raph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) sur g ical implantations (3) healthcare intervention (e. g ., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for dama g es arisin g out of the uses set forth in the above and purchasers who elect to use renesas products in any of the fore g oin g applications shall indemnify and hold harmless renesas technolo g y corp., its affiliated companies and their officers, directors, and employees a g ainst any and all dama g es arisin g out of such applications. 9. you should use the products described herein within the ran g e specified by renesas, especially with respect to the maximum ratin g , operatin g supply volta g e ran g e, movement power volta g e ran g e, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or dama g es arisin g out of the use of renesas products beyond such specified ran g es. 10. althou g h renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to g uard a g ainst the possibility of physical injury, and injury or dama g e caused by fire in the event of the failure of a renesas product, such as safety desi g n for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for a g in g de g radation or any other applicable measures. amon g others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowin g by infants and small children is very hi g h. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for dama g es arisin g out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions re g ardin g the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes re g ardin g these materials rev.5.00 sep. 27, 2007 page iii of xxxiv rej09b0398-0500 general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. if the descriptions under general precautions in the handling of mpu/mcu products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. when changing to products of different type numbers, implement a system-evaluation test for each of the products. rev.5.00 sep. 27, 2007 page iv of xxxiv rej09b0398-0500 rev.5.00 sep. 27, 2007 page v of xxxiv rej09b0398-0500 preface the sh7014/16/17 cmos single-chip microprocessors integrate a renesas technology-original architecture, high-speed cpu with peripheral functions required for system configuration. the cpu has a risc-type instruction set . most instructions can be ex ecuted in one clock cycle, which greatly improves instruction execution speed. in addition, the 32-bit internal-bus architecture enhances data processing power. with this cpu, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds. in particular, this lsi has a 1-kbyte on-chip cache, which allows an improvement in cpu performance during external memory access. in addition, this lsi includes on-chip peripheral functions necessary for system configuration, such as large-capacity rom (ex cept the sh7014, which is romless) and ram, timers, a serial communication interface (sci), an a/d converter, an interrupt controller (intc), and i/o ports. memory or peripheral lsis can be connected effi ciently with an external memory access support function. this greatly reduces system cost. this lsi has an f-ztat ? version with on-chip flash memory and a mask rom version. these versions enable users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. this hardware manual covers the sh7014/16/17/. fo r a detailed description of instructions, refer to the programming manual. related manuals sh7014/16/17 instruction execution: sh-1/sh-2/sh-dsp software manual for information on development systems, please contact a renesas technology sales representative. rev.5.00 sep. 27, 2007 page vi of xxxiv rej09b0398-0500 rev.5.00 sep. 27, 2007 page vii of xxxiv rej09b0398-0500 main revisions for this edition item page revision (see manual for details) all ? company name and brand names amended (before) hitachi, ltd. (after) renesas technology corp. description of dtc deleted 1.2 block diagram figure 1.1 block diagram of the sh7014 6 figure amended a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 md3 md2 md1 md0 nmi extal xtal v cc v cc v cc pllvcc pllcap pllvss v cc v cc v ss v ss v ss v ss v ss v ss v ss v ss av cc av ss res wdtovf pb9/ irq7 /a21 pb8/ irq6 /a20/ wait pb7/a19 pb6/a18 pb5/ irq3 /rdwr pb4/ irq2 / cash pb3/ irq1 / casl pb2/ irq0 / ras a17 a16 pa15/ck rd wrh wrl cs1 cs0 pa9/tclkd/ irq3 pa8/tclkc/ irq2 pa7/tclkb/ cs3 pa6/tclka/ cs2 pa5/sck1/ dreq1 / irq1 pa4/txd1 pa3/rxd1 pa2/sck0/ dreq0 / irq0 pa1/txd0 pa0/rxd0 pe15/dack1 pe14/dack0/ ah pe13 pe12 pe11 pe10 pe9 pe8 pe7/tioc2b pe6/tioc2a pe5/tioc1b pe4/tioc1a pe3/tioc0d/drak1 pe2/tioc0c/ dreq1 pe1/tioc0b/drak0 pe0/tioc0a/ dreq0 : peripheral address bus : peripheral data bus : internal address bus : internal upper data bus : internal lower data bus pll pf7/an7 pf6/an6 pf5/an5 pf4/an4 pf3/an3 pf2/an2 pf1/an1 pf0/an0 ram (3 kb)/ cache (1 kb) cpu direct memory access controller interrupt controller bus state controller serial communi- cation interface ( 2 channels) multifunction timer/ pulse unit compare match timer ( 2 channels) a/d converter watch- dog timer v ss v ss v ss figure 1.2 block diagram of the sh7016, sh7017 7 note amended note: * v cc in the sh7016, fwp in the sh7017 (except fwe pin in the programmer mode). rev.5.00 sep. 27, 2007 page viii of xxxiv rej09b0398-0500 item page revision (see manual for details) 1.3.1 pin arrangement figure 1.4 sh7016, sh7017 pin arrangement (fp-112 top view) 9 note amended note: * v cc in the sh7016, fwp in the sh7017 (except fwe pin in the programmer mode). 5.3.1 address error sources table 5.5 bus cycles and address errors 64 title added and table amended bus cycle type bus master bus cycle description address errors cpu instruction fetched from even address none (normal) instruction fetch instruction fetched from odd address address error occurs instruction fetched from other than on-chip peripheral module space * none (normal) instruction fetched from on-chip peripheral module space * address error occurs instruction fetched from external memory space when in single chip mode address error occurs 5.4.1 interrupt sources 65 title added and description amended table 5.6 shows the sources that start up interrupt exception processing. these are divided into nmi, irq and on-chip peripheral modules. 6.3.1 interrupt priority registers a to h (ipra to iprh) 82 description amended ipra to iprh are initialized to h'0000 by a power-on reset . they are not initialized in standby mode. 8.1.3 pin configuration table 8.1 pin configuration 103 table amended signal i/o description wrh o strobe that indicates a write cycle to the higher byte (d15 to d8) for ordinary space/multiplex i/o. also output during dram access. wrl o strobe that indicates a write cycle to the lower byte (d7 to d0) for ordinary space/multiplex i/o. also output during dram access. 105 table amdended addresss h'00000000 to h'0001fff * 4 8.1.5 address map table 8.3 address map ? in on-chip rom enabled mode 8.2.1 bus control register 1 (bcr1) bit 0 ? cs0 space size specification (a0sz) 108 note added note: a0sz is effective only in on-chip rom effective mode. in on-chip rom ineffective mode, the cs0 space bus size is specified by the mode pin. rev.5.00 sep. 27, 2007 page ix of xxxiv rej09b0398-0500 item page revision (see manual for details) 8.2.5 dram area control register (dcr) 115 description amended dcr is a 16-bit read/write register that selects the number of waits, operation mode, number of address multiplex shifts and the like for dram control. after a power-on reset, write the initial values to the bits in dcr and do not change the values afterward. do not perform any dram space accesses before dcr initial settings are completed. 9.1.1 features 147 description amended ? transfer requests: there are three dmac transfer activation requests, as indicated below. ? external request: from two dreq pins. dreq can be detected either by falling edge or by low level. these can be received by all channels. 9.2.3 dma transfer count registers 0, 1 (dmatcr0, dmatcr1) 153 description amended ? specifying a h'000001 gives a transfer count of 1, while h'000000 gives the maximum setting, 65,536 transfers. while dmac is in operation, the number of transfers to be performed is indicated. the initial value after power-on resets or in software standby mode is undefined. upper sixteen bits of this register are read as 0 and the write value should always be 0. 9.3.5 number of bus cycle states and dreq pin sample timing cycle steal mode operations: figure 9.12 cycle steal, single address and level detection (normal operation) 176 note added note: with cycle-steal and single address operation, sampling timing is the same whether dreq detection is by level or by edge. burst mode, single address, and edge detection: 185 description amended ?during this period, data is undefined, and dack is not output. nor is the number of dmac transfers counted. the actual dmac transfer begins after one dummy bus cycle output. thereafter, dmac transfer continues until the data transfer count set in the dmatcr has ended. ... rev.5.00 sep. 27, 2007 page x of xxxiv rej09b0398-0500 item page revision (see manual for details) 9.3.6 dma transfer ending conditions conditions for ending all channels simultaneously: 187 description amended when the processing of a one unit transfer is complete. in a dual address mode direct address transfer, even if an address error occurs or the nmi flag is set during read processing, the transfer will not be halted until after completion of the following write processing. in such a case, sar, dar, and dmatcr values are updated. 9.4.2 example of dma transfer between external ram and external device with dack 189 description amended in this example, an external request, single address mode transfer with external memory as the transfer source and an external device with dack as the transfer destination is executed using dmac channel 1. 10.1.1 features 191 description amended ? pwm mode: pwm output can be provided with any duty cycle. when combined with the counter synchronizing function, up to seven-phase pwm output is enabled (with channels 0 to 2 set to pwm mode 2 and channel 0 synchronized with the tgr0a register (channels 0 to 2 phase output: 3, 2, 2)). 10.1.4 register configuration table 10.3 register configuration 198 notes amended notes: do not access empty addresses. 1. 16-bit registers (tcnt, tgr) cannot be read or written in 8-bit units. 2. write 0 to clear flags. 10.2.4 timer interrupt enable register (tier) bit 5?underflow interrupt enable (tcieu) 215 description amended this bit is reserved for channel 0. it always reads as 0. the write value should always be 0. bit 3?tgr interrupt enable d (tgied): 216 description amended this bit is reserved for channels 1 and 2. it always reads as 0. the write value should always be 0. bit 2?tgr interrupt enable c (tgiec): description amended this bit is reserved for channels 1 and 2. it always reads as 0. the write value should always be 0. 10.2.5 timer status register (tsr) 217 description amended the timer status register (tsr) is an 8-bit register that indicates the status of each channel. the mtu has three tsr registers, one each for channel. tsr is initialized to h'c0 by a power-on reset or by standby mode. rev.5.00 sep. 27, 2007 page xi of xxxiv rej09b0398-0500 item page revision (see manual for details) 10.4.4 buffer operation buffer operation examples ? when tgr is an input capture register 237 description amended figure 10.20 shows an example of tgra set as an input capture register with the tgra and tgrc registers set for buffer operation. figure 10.20 buffer operation example (input capture register) 238 figure amended tioc0a 10.4.6 pwm mode 240 description amended a period can be set for a register by using the tgr compare- match as a counter clear source. all channels can be independently set to pwm mode. synchronous operation is also possible. 10.4.7 phase counting mode phase counting mode application example: 250 description amended the channel 1 tgr1a and tgr1b registers are set for the input capture function, the channel 0 tgr0a and tgr0c register compare-match is used as an input capture source, and all of the control period increment and decrement values are stored. this procedure enables the accurate detection of position and speed. 10.6.1 input/output timing output compare output timing: 254 description amended the compare-match signal is generated at the final state of tcnt and tgr matching. when a compare-match signal is issued, the output value set in tior is output to the output compare output pin (the tioc pin). after tcnt and tgr matching, a compare-match signal is not issued until immediately before the tcnt input clock. 10.7.10 tcnt2 write and overflow/underflow contention in cascade connection 269 description amended with timer counters tcnt1 and tcnt2 in a cascade connection, when a contention occurs during tcnt1 count (during a tcnt2 overflow/underflow) in the t 2 state of the tcnt2 write cycle, the write to tcnt2 is conducted, and the tcnt1 count signal is prohibited. at this point, if there is match with tgr1a and the tcnt1 value, a compare signal is issued. furthermore, when the tcnt1 count clock is selected as the input capture source of channel 0, tgra0 to tgrd0 carry out the input capture operation. in addition, when the compare match/input capture is selected as the input capture source of tgrb1, tgrb1 carries out input capture operation. the timing is shown in figure 10.57. rev.5.00 sep. 27, 2007 page xii of xxxiv rej09b0398-0500 item page revision (see manual for details) 10.8.1 operating modes 273 description amended ? normal mode (channels 0 to 2) ? pwm mode 1 (channels 0 to 2) ? pwm mode 2 (channels 0 to 2) ? phase counting modes 1 to 4 (channels 1 and 2) 10.8.3 operation in case of re-setting due to error during operation, etc. 273 description amended the mtu has four operating modes, as stated above. there are thus 16 mode transition combinations . possible mode transition combinations are shown in table 10.14. 10.8.4 overview of initialization procedures and mode transitions in case of error during operation, etc. (3) operation when error occurs during normal mode operation, and operation is restarted in pwm mode 2: 277 note deleted (4) operation when error occurs during normal mode operation, and operation is restarted in phase counting mode: 278 note deleted (7) operation when error occurs during pwm mode 1 operation, and operation is restarted in pwm mode 2: 281 note deleted (8) operation when error occurs during pwm mode 1 operation, and operation is restarted in phase counting mode: 282 note deleted rev.5.00 sep. 27, 2007 page xiii of xxxiv rej09b0398-0500 item page revision (see manual for details) description amended and notes added bit 4 fer des c ription 0 receiving is in progress or has ended normally * 1 [clearing conditions] ? power-on reset or standby mode ? when 0 is written to fer after reading fer = 1 1 a receive framing error occurred * 2 [setting condition] when at the end of an sci receive operation the final stop bit of the receive data is checked and its value * 2 is 0 12.2.7 serial status register (ssr) bit 4?framing error (fer): 318 notes: 1. the fer flag is not affected and retains their previous values when the re bit in scr is cleared to 0. 2. when the stop bit length is two bits, only the first bit is checked to see if it is a 1. the second stop bit is not checked. when a framing error occurs, the sci transfers the receive data into the rdr but does not set rdrf. serial receiving cannot continue while fer is set to 1. in the clock synchronous mode, serial transmitting is also disabled. in addition, serial transmission cannot continue in clock synchronous mode. description amended and notes added bit 3?parity error (per): bit 3 per des c ription 0 receiving is in progress or has ended normally * 1 [clearing conditions] ? power-on reset or standby mode ? when 0 is written to per after reading per = 1 1 a receive parity error occurred * 2 [setting condition] per is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (o/ e ) in the serial mode register (smr) notes: 1. the per flag is not affected and retains their previous values when the re bit in scr is cleared to 0. 2. when a parity error occurs, the sci transfers the receive data into the rdr but does not set rdrf. serial receiving cannot continue while per is set to 1. in the clock synchronous mode, serial transmitting is also disabled. in addition, serial transmission cannot continue in clock synchronous mode. rev.5.00 sep. 27, 2007 page xiv of xxxiv rej09b0398-0500 item page revision (see manual for details) 12.5.7 constraints on dmac use 366 description amended ? when using an external clock source for the synchronization clock, update the tdr with the dmac , and then after five system clocks or more elapse, input a transmit clock. if a transmit clock is input in the first four system clocks after the tdr is written, an error may occur (figure 12.22). 13.1.1 features 367 description amended ? high-speed conversion ? minimum conversion time: 2.9 s per channel (for 28-mhz operation) 1.4 s per channel during continuous conversion 13.4 operation 378 description amended ? in buffer operation, the previous conversion result is saved in a buffer register at the end of a conversion for the relevant channel. ? in simultaneous sampling operation, the analog input voltages of two channels are sampled simultaneously then converted in order. ? software, a timer conversion start trigger (mtu) can be selected as the conversion start condition. 13.4.7 conversion start modes 388 description amended in the low-power conversion mode, power is applied to the analog circuitry simultaneous to the conversion start (adst set). when 200 cycles of the reference clock have elapsed, conversion becomes possible for the analog circuit and the first a/d conversion begins. when performing consecutive conversions, the second and later conversions are executed in 20 cycles. select the basic clock with the cks bit of the adcsr. when the a/d conversion ends, adst is cleared to 0 and the analog circuit power supply is automatically cut off. because the analog circuit is only active during the a/d conversion operation period in this mode, current consumption can be reduced. rev.5.00 sep. 27, 2007 page xv of xxxiv rej09b0398-0500 item page revision (see manual for details) 13.4.8 a/d conversion time table 13.7 a/d conversion times 392 note 2 amended 2. table entries are for when pwr = 1. if 200 states have not elapsed since the adst bit has been set, no conversions are done until after those 200 states have occurred. when pwr = 0, add 200 states to the first a/d conversion start delay time. when two or more conversions are performed in succession, tcp is 20 cycles when cks = 0, and 40 cycles when cks = 1. table 13.8 operating frequency and cks bit settings note added note: the indication " ? " means the setting is not available. 13.6.5 a/d conversion termination (hd6417014r only) 394 title amended 14.1.3 pin configuration 399 description amended the eight analog input pins are divided into two groups, with analog input pins 0 to 3 (an0 to an3) comprising group 0, and analog input pins 4 to 7 (an4 to an7) comprising group 1. the av cc and av ss pins are for the mid-speed speed a/d converter internal analog section power supply. 14.2.1 a/d data register a to d (addra to addrd) 401 description amended a/d registers are special register s that read stored results of a/d conversion in 16 bits. there are four registers: addra to addrd. 14.4.2 scan mode (scan = 1) 409 description amended an example of operation in scan mode when three channels of group 0 (an0 to an2) are selected for a/d conversion is shown in figure 14.4. 1. set the operation mode to scan mode (scan = 1), set the scan group to group 0 (ch2 = 0), set the analog channels to an0 to an2 (ch1 = 1, ch0 = 0), and then start a/d conversion (adst = 1). 14.5 interrupt 414 description amended the mid-speed a/d converter's interrupt source is summarized in table 14.5. when the dmac are activated by an adi interrupt, the adf flag of adcsr is cleared to 0 by register access of a/d. 15.4.1 interrupt sources 427 title amended rev.5.00 sep. 27, 2007 page xvi of xxxiv rej09b0398-0500 item page revision (see manual for details) 15.4.3 compare match flag clear timing 428 description amended the cmf bit of the cmcsr register is cleared either by writing a 0 to it after reading a 1 . figure 15.5 shows the timing when the cmf bit is cleared by the cpu. 16.3.2 port a control registers l1, l2 (pacrl1 and pacrl2) 446 description amended pacrl1 is initialized by external power-on reset to h'4000 in extended mode, and to h'0000 in single chip mode. pacrl2 is initialized by external power-on reset to h'0000. neither register is initialized by reset by wdt, standby mode, or sleep mode, so the previous data is maintained. description amended bit 14 pa15md des c ription 0 general input/output (pa15) (single chip mode initial value) port a control register l1 (pacrl1): bit 14?pa15 mode (pa15md): 447 1 clock output (ck) (extended mode initial value) 16.3.3 port b i/o register (pbior) 452 description amended the port b i/o register l (pbior) is a 16-bit read/write register that selects input or output for the ten pins of port b (eight pins in the sh7014). bits pb9ior to pb0ior correspond to the pb9/ irq7 /a21 pin to pb0/a16 pin. pbior is enabled when the port b pins function as input/outputs (pb9 to pb0). for other functions, it is disabled. 17.2.2 port a data register l (padrl) 477 description amended padrl is initialized by an external power-on reset. however, padrl is not initialized for a reset by wdt, standby mode, or sleep mode. 17.3.2 port b data register (pbdr) 479 description amended pbdr is initialized by an external power-on reset. however, pbdr is not initialized for a reset by wdt, standby mode, or sleep mode. 17.4.2 port c data register (pcdr) 481 description amended pcdr is initialized by an external power-on reset. however, pcdr is not initialized for a reset by wdt, standby mode, or sleep mode. 17.5.2 port d data register l (pddrl) 483 description amended pddrl is initialized by an external power-on reset. however, pddrl is not initialized for a reset by wdt, standby mode, or sleep mode. rev.5.00 sep. 27, 2007 page xvii of xxxiv rej09b0398-0500 item page revision (see manual for details) 17.6.2 port e data register (pedr) 485 description amended pedr is initialized by a external power-on reset. however, pedr is not initialized for a reset by wdt, standby mode, or sleep mode, so the previous data is retained. 17.7.2 port f data register (pfdr) 487 description amended pfdr is an 8-bit read-only register that stores data for port f. the bits pf7dr to pf0dr correspond to the pf7/an7 to pf0/an0 pins. any value written into these bits is ignored, and there is no effect on the status of the pins. when any of the bits are read, the pin status rather than the bit value is read directly. however, when an a/d converter analog input is being sampled, values of 1 are read out. table 17.17 shows the read/write operations of the port f data register. pfdr is not initialized by power-on resets, standby mode, or sleep mode (the bits always reflect the pin status). 18.4 register configuration table 18.3 flash memory registers 497 notes amended notes: flmcr1, flmcr2, and ebr1 are 8-bit registers, and ramer is a 16-bit register. only byte accesses are valid for flmcr1, flmcr2, and ebr1, the access requiring 3 cycles. three cycles are required for a byte or word access to ramer, and 6 cycles for a longword access. when a longword write is performed on ramer, 0 must always be written to the lower word (address h'ffff8630). operation is not guaranteed if any other value is written. 1. in modes in which the on-chip flash memory is disabled, a read will return h'00, and writes are invalid. writes are also disabled when the fwe bit is set to 1 in flmcr1. 2. a read in a mode in which on-chip flash memory is disabled will return h'00. 3. when a low level is input to the fwp pin, the initial value is h'80. 4. when a high level is input to the fwp pin, or if a low level is input and the swe bit in flmcr1 is not set, these registers are initialized to h'00. rev.5.00 sep. 27, 2007 page xviii of xxxiv rej09b0398-0500 item page revision (see manual for details) 18.5.4 ram emulation register (ramer) 503 description amended ramer specifies the area of flash memory to be overlapped with part of ram when emulating real-time flash memory programming. ramer is initialized to h'0000 by a reset and in hardware standby mode. it is not initialized in software standby mode. ramer settings should be made in user mode or user program mode. 18.7.2 program-verify mode figure 18.13 program/ program-verify flowchart 512 figure amended and note 5 added set swe-bit of flmcr1 wait 10 s n = 1 m = 0 successively write 32-byte data in rewrite data area in ram to flash memory enable wdt set psu bit in flmcr1(2) wait 50 s set psu bit in flmcr1(2) wait 200 s write start set psu bit in flmcr1(2) wait 10 s wait 10 s ng ng ng ng ok ok ok wait 4 s wait 2 s * 4 * 2 * 3 store 32 bytes write data in write data area and rewrite data area * 4 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 1 wait 4 s set psu bit in flmcr1(2) disable wdt set psu bit in flmcr1(2) perform dummy-write of h'ff to verify address set psu bit in flmcr1(2) clear swe bit of flmcr1 m = 1 write end write data = verify data? 32 byte data verify complete? m = 0? increment address ok clear swe bit of flmcr1 n 1000? n n + 1 start transfer rewrite data to rewrite data area write end write failure read verify data * 3 operate rewrite data note: 5. set the values of x, y, z, , , , , , and n to match the characteristics of the memory device. rev.5.00 sep. 27, 2007 page xix of xxxiv rej09b0398-0500 item page revision (see manual for details) 18.7.3 erase mode 517 description added when erasing flash memory, the erase/erase-verify flowchart shown in figure 18.14 should be followed. to perform data or program erasure, set the 1 bit flash memory area to be erased in erase block register 1 (ebr1) at least 10 s after setting the swe bit to 1 in flash memory control register 1 (flmcr1). 18.8.2 software protection 525 description amended software protection can be implemented by setting the swe bit in flmcr1, erase block register 1 (ebr1) and the rams bit in the ram emulation register (ramer). 18.11.4 auto-program mode 538 description amended 3. the lower 8 bits of the transfer address must be h'00, h'80. if a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. memory address transfer is performed in the second cycle (figure 18.24). do not perform transfer after the third cycle. 18.11.6 status read mode table 18.19 status read mode return commands 543 note amended note: i/o2 and i/o3 are undefined at present. 22.3.3 bus timing table 22.7 bus timing 567 description amended and notes added conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, av cc = v cc 10%, v ss = av ss = 0 v, ta = ? 20 to +75 c notes: tpc is the set value of the tpc bit in dcr. * the delay time min values are reference values (typ).) 22.3.4 direct memory access controller timing table 22.8 direct memory access controller timing 579 description amended conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, av cc = v cc 10%, v ss = av ss = 0 v, ta = ? 20 to +75 c rev.5.00 sep. 27, 2007 page xx of xxxiv rej09b0398-0500 item page revision (see manual for details) 22.3.5 multifunction timer pulse unit timing table 22.9 multifunction timer pulse unit timing 581 description amended conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, av cc = v cc 10%, v ss = av ss = 0 v, ta = ? 20 to +75 c 22.3.6 i/o port timing table 22.10 i/o port timing 582 description amended conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, av cc = v cc 10%, v ss =av ss = 0 v, ta = ? 20 to +75 c 22.3.7 watchdog timer timing table 22.11 watchdog timer timing 583 description amended conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, av cc = v cc 10%, v ss = av ss = 0 v, ta = ? 20 to +75 c 22.3.8 serial communication interface timing table 22.12 serial communication interface timing 583 description amended conditions: v cc = 5.0 v 10%, av cc = 5.0 v 10%, av cc = v cc 10%, v ss = av ss = 0 v, ta = ? 20 to +75 c a.2 functions 600 to 681 newly added appendix b. i/o port block diagrams figure b.5 pan/tclkm/ irqx block diagram (sh7014, mask) 686 title amended 706 title and table amended pin fun c tion class pin name data bus d0 to d15 c.1 pin states table c.1 pin states in reset, and power-down modes sci sck0, sck1 txd0, txd1 rxd0, rxd1 all trademarks and registered trademarks are the property of their respective owners. rev.5.00 sep. 27, 2007 page xxi of xxxiv rej09b0398-0500 contents section 1 sh7014/16/17 overview ................................................................................ 1 1.1 sh7014/16/17 overview................................................................................................... 1 1.1.1 sh7014/16/17 series features ............................................................................. 1 1.2 block diagram .................................................................................................................. 6 1.3 pin arrangement and pin functions.................................................................................. 8 1.3.1 pin arrangement .................................................................................................. 8 1.3.2 pin arrangement by mode................................................................................... 10 1.3.3 pin functions ....................................................................................................... 14 section 2 cpu ...................................................................................................................... 19 2.1 register configuration...................................................................................................... 19 2.1.1 general registers (rn)......................................................................................... 19 2.1.2 control registers ................................................................................................. 20 2.1.3 system registers .................................................................................................. 21 2.1.4 initial values of registers.................................................................................... 21 2.2 data formats ................................................................................................................... .. 22 2.2.1 data format in registers...................................................................................... 22 2.2.2 data format in memory....................................................................................... 22 2.2.3 immediate data format ....................................................................................... 22 2.3 instruction features........................................................................................................... 23 2.3.1 risc-type instruction set................................................................................... 23 2.3.2 addressing modes ............................................................................................... 26 2.3.3 instruction format................................................................................................ 30 2.4 instruction set by classification ....................................................................................... 33 2.5 processing states.............................................................................................................. . 46 2.5.1 state transitions................................................................................................... 46 2.5.2 power-down state ............................................................................................... 48 section 3 operating modes ............................................................................................... 51 3.1 operating modes, types, and selection............................................................................ 51 3.2 explanation of operating modes ...................................................................................... 52 3.3 pin configuration.............................................................................................................. 52 section 4 clock pulse generator (cpg) ....................................................................... 53 4.1 overview....................................................................................................................... .... 53 4.1.1 block diagram ..................................................................................................... 53 4.2 oscilla tor..................................................................................................................... ...... 54 4.2.1 connecting a crysta l oscillato r ........................................................................... 54 rev.5.00 sep. 27, 2007 page xxii of xxxiv rej09b0398-0500 4.2.2 external clock input method............................................................................... 56 4.3 prescaler...................................................................................................................... ...... 57 section 5 exception processing ....................................................................................... 59 5.1 overview....................................................................................................................... .... 59 5.1.1 types of exception processing and priority ........................................................ 59 5.1.2 exception processing operations......................................................................... 60 5.1.3 exception processing vector table ..................................................................... 61 5.2 resets ......................................................................................................................... ....... 63 5.2.1 power-on reset .................................................................................................... 63 5.3 address errors ................................................................................................................. . 64 5.3.1 address error sources ......................................................................................... 64 5.3.2 address error exception processing.................................................................... 65 5.4 interrupts..................................................................................................................... ...... 65 5.4.1 interrupt sources.................................................................................................. 65 5.4.2 interrupt priority level ........................................................................................ 66 5.4.3 interrupt exception processing ............................................................................ 66 5.5 exceptions triggered by instructions ............................................................................... 67 5.5.1 types of exceptions trigge red by instru ctions ................................................... 67 5.5.2 trap instructions .................................................................................................. 67 5.5.3 illegal slot instructions ........................................................................................ 68 5.5.4 general illegal instructions.................................................................................. 68 5.6 when exception sources are not accepted .................................................................... 69 5.6.1 immediately after a delayed branch instruction ................................................. 69 5.6.2 immediately after an interrupt-disabled instruction............................................ 69 5.7 stack status after exception processing ends .................................................................. 70 5.8 usage notes .................................................................................................................... .. 71 5.8.1 value of stack pointer (sp) ................................................................................. 71 5.8.2 value of vector base register (vbr) ................................................................. 71 5.8.3 address errors caused by stacking of address error exception processing...... 71 section 6 interrupt controller (intc) ........................................................................... 73 6.1 overview....................................................................................................................... .... 73 6.1.1 features................................................................................................................ 73 6.1.2 block diagram..................................................................................................... 73 6.1.3 pin configuration................................................................................................. 75 6.1.4 register configuration......................................................................................... 75 6.2 interrupt sources.............................................................................................................. . 76 6.2.1 nmi interrupts ..................................................................................................... 76 6.2.2 irq interrupts ...................................................................................................... 76 rev.5.00 sep. 27, 2007 page xxiii of xxxiv rej09b0398-0500 6.2.3 on-chip peripheral mo dule interrupts ................................................................ 77 6.2.4 interrupt exception vectors and priority rankings ............................................. 77 6.3 description of registers.................................................................................................... 81 6.3.1 interrupt priority registers a to h (ipra to iprh) ............................................ 81 6.3.2 interrupt control register (icr).......................................................................... 82 6.3.3 irq status register (isr).................................................................................... 83 6.4 interrupt operation............................................................................................................ 85 6.4.1 interrupt sequence ............................................................................................... 85 6.4.2 stack after interrupt exception processing .......................................................... 87 6.5 interrupt res ponse time ................................................................................................... 88 6.6 data transfer with interrupt request signals ................................................................... 90 6.6.1 handling dmac activating sources but not cpu interrupt sources ................ 90 6.6.2 treating cpu interrupt sources but not dmac activating sources.................. 90 section 7 cache memory (cac) .................................................................................... 91 7.1 overview....................................................................................................................... .... 91 7.1.1 features................................................................................................................ 91 7.1.2 block diagram ..................................................................................................... 92 7.1.3 register configuration......................................................................................... 93 7.2 register explanation ......................................................................................................... 9 4 7.2.1 cache control register (ccr) ............................................................................ 94 7.3 address array and data array.......................................................................................... 96 7.3.1 cache address array read/write space ............................................................. 96 7.3.2 cache data array read/write space................................................................... 97 7.4 usage notes .................................................................................................................... .. 98 7.4.1 cache initialization .............................................................................................. 98 7.4.2 forced access to address array and data array ................................................ 98 7.4.3 cache miss penalty and cache fill timing ......................................................... 98 7.4.4 cache hit after cache miss ................................................................................. 100 section 8 bus state controller (bsc) ........................................................................... 101 8.1 overview....................................................................................................................... .... 101 8.1.1 features................................................................................................................ 101 8.1.2 block diagram ..................................................................................................... 102 8.1.3 pin configuration................................................................................................. 103 8.1.4 register configuration......................................................................................... 103 8.1.5 address map ........................................................................................................ 104 8.2 description of registers.................................................................................................... 10 7 8.2.1 bus control regist er 1 (bcr 1) ........................................................................... 107 8.2.2 bus control regist er 2 (bcr 2) ........................................................................... 109 rev.5.00 sep. 27, 2007 page xxiv of xxxiv rej09b0398-0500 8.2.3 wait control register 1 (wcr1)......................................................................... 112 8.2.4 wait control register 2 (wcr2)......................................................................... 114 8.2.5 dram area control register (dcr) ................................................................. 115 8.2.6 refresh timer control/status register (rtcsr)................................................ 118 8.2.7 refresh timer count er (rtcnt)........................................................................ 121 8.2.8 refresh time constant register (rtcor) ......................................................... 122 8.3 accessing ordinary space ................................................................................................ 123 8.3.1 basic timing........................................................................................................ 123 8.3.2 wait state control ............................................................................................... 124 8.3.3 cs assert period extension ................................................................................. 126 8.4 dram access .................................................................................................................. 1 27 8.4.1 dram direct connection ................................................................................... 127 8.4.2 basic timing........................................................................................................ 128 8.4.3 wait state control ............................................................................................... 129 8.4.4 burst operation.................................................................................................... 133 8.4.5 refresh timing .................................................................................................... 135 8.5 address/data multiplex i/o space access ....................................................................... 136 8.5.1 basic timing........................................................................................................ 136 8.5.2 wait state control ............................................................................................... 138 8.5.3 cs assertion extension ....................................................................................... 139 8.6 waits between access cycles........................................................................................... 140 8.6.1 prevention of data bus conflicts......................................................................... 140 8.6.2 simplification of bus cycl e start detection........................................................ 142 8.7 bus arbitration................................................................................................................ .. 143 8.8 memory connection examples......................................................................................... 143 8.9 on-chip peripheral i/o register access ........................................................................... 145 8.10 cpu operation when program is in external memory .................................................... 146 section 9 direct memory access controller (dmac) ............................................ 147 9.1 overview....................................................................................................................... .... 147 9.1.1 features................................................................................................................ 147 9.1.2 block diagram..................................................................................................... 148 9.1.3 pin configuration................................................................................................. 149 9.1.4 register configuration......................................................................................... 150 9.2 register descriptions ........................................................................................................ 1 51 9.2.1 dma source address registers 0, 1 (sar0, sar1) .......................................... 151 9.2.2 dma destination address registers 0, 1 (dar0, dar1).................................. 152 9.2.3 dma transfer count registers 0, 1 (dmatcr0, dmatcr1)......................... 153 9.2.4 dma channel control registers 0, 1 (chcr0, chcr1)................................... 154 9.2.5 dmac operation register (dmaor)................................................................ 159 rev.5.00 sep. 27, 2007 page xxv of xxxiv rej09b0398-0500 9.3 operation...................................................................................................................... ..... 161 9.3.1 dma transfer flow ............................................................................................ 161 9.3.2 dma transfer requests ...................................................................................... 163 9.3.3 channel priority ................................................................................................... 165 9.3.4 dma transfer types........................................................................................... 165 9.3.5 number of bus cycle states a nd dreq pin sample timing.............................. 172 9.3.6 dma transfer endi ng conditi ons....................................................................... 187 9.3.7 dmac access from cpu.................................................................................... 188 9.4 examples of use ............................................................................................................... 188 9.4.1 example of dma transfer between on -chip sci and external memory .......... 188 9.4.2 example of dma transfer between exte rnal ram and external device with dack .................................................................................................................. 189 9.5 usage notes .................................................................................................................... .. 190 section 10 multifunction timer pulse unit (mtu) .................................................. 191 10.1 overview....................................................................................................................... .... 191 10.1.1 features................................................................................................................ 191 10.1.2 block diagram ..................................................................................................... 195 10.1.3 pin configuration................................................................................................. 196 10.1.4 register configuration......................................................................................... 197 10.2 mtu register descriptions .............................................................................................. 199 10.2.1 timer control register (tcr) ............................................................................. 199 10.2.2 timer mode register (tmdr) ............................................................................ 203 10.2.3 timer i/o control register (tior) ..................................................................... 205 10.2.4 timer interrupt enable register (tier) .............................................................. 214 10.2.5 timer status register (tsr)................................................................................ 217 10.2.6 timer counters (tcnt) ...................................................................................... 220 10.2.7 timer general register (tgr) ............................................................................ 221 10.2.8 timer start register (tstr)................................................................................ 221 10.2.9 timer synchro register (tsyr) ......................................................................... 222 10.3 bus master interface ......................................................................................................... 2 24 10.3.1 16-bit registers ................................................................................................... 224 10.3.2 8-bit registers ..................................................................................................... 224 10.4 operation...................................................................................................................... ..... 226 10.4.1 overview.............................................................................................................. 226 10.4.2 basic functions.................................................................................................... 226 10.4.3 synchronous op eration........................................................................................ 232 10.4.4 buffer operation .................................................................................................. 235 10.4.5 cascade connection mode................................................................................... 238 10.4.6 pwm mode.......................................................................................................... 240 rev.5.00 sep. 27, 2007 page xxvi of xxxiv rej09b0398-0500 10.4.7 phase counting mode.......................................................................................... 244 10.5 interrupts..................................................................................................................... ...... 251 10.5.1 interrupt sources and priority ranking................................................................ 251 10.5.2 dmac activation................................................................................................ 252 10.5.3 a/d converter activation.................................................................................... 252 10.6 operation timing.............................................................................................................. 253 10.6.1 input/output timing ............................................................................................ 253 10.6.2 interrupt signal timing........................................................................................ 258 10.7 usage notes .................................................................................................................... .. 262 10.7.1 input clock li mitations ....................................................................................... 262 10.7.2 note on cycle setting .......................................................................................... 262 10.7.3 contention between tcnt write and clear........................................................ 263 10.7.4 contention between tcnt write and increment ................................................ 264 10.7.5 contention between buffer register write and compare match ........................ 265 10.7.6 contention between tgr read and input capture.............................................. 266 10.7.7 contention between tgr write and input capture............................................. 267 10.7.8 contention between buffer register write and input capture ............................ 268 10.7.9 contention between tgr write and compare match ......................................... 269 10.7.10 tcnt2 write and overflow/underflow c ontention in cascade connection ..... 269 10.7.11 contention between overflow/underflow and counter clearing........................ 271 10.7.12 contention between tcnt write and overflow/underflow............................... 272 10.7.13 cautions on carrying out buffer operatio n of channel 0 in pwm mode 1....... 272 10.8 mtu output pin initialization.......................................................................................... 273 10.8.1 operating modes.................................................................................................. 273 10.8.2 reset start operation ........................................................................................... 273 10.8.3 operation in case of re-setting due to error during operation, etc.................. 273 10.8.4 overview of initialization procedures and mode transitions in case of error during operation, etc. .......................................................................................... 274 section 11 watchdog timer (wdt) .............................................................................. 291 11.1 overview....................................................................................................................... .... 291 11.1.1 features................................................................................................................ 291 11.1.2 block diagram..................................................................................................... 292 11.1.3 pin configuration................................................................................................. 292 11.1.4 register configuration......................................................................................... 293 11.2 register descriptions ........................................................................................................ 2 93 11.2.1 timer counter (tcnt)........................................................................................ 293 11.2.2 timer control/status register (tcsr)................................................................ 294 11.2.3 reset control/status register (rstcsr)............................................................ 296 11.2.4 register access.................................................................................................... 297 rev.5.00 sep. 27, 2007 page xxvii of xxxiv rej09b0398-0500 11.3 operation...................................................................................................................... ..... 298 11.3.1 watchdog timer mode ........................................................................................ 298 11.3.2 interval timer mode ............................................................................................ 300 11.3.3 clearing the st andby mode .................................................................................. 300 11.3.4 timing of setting the ove rflow flag (ovf) ....................................................... 301 11.3.5 timing of setting the watchdog time r overflow flag (wovf)........................ 301 11.4 usage notes .................................................................................................................... .. 302 11.4.1 tcnt write and increment contention............................................................... 302 11.4.2 changing cks2 to cks0 bit values................................................................... 302 11.4.3 changing between watchdog timer/ interval timer modes................................ 302 11.4.4 system reset with wdtovf .............................................................................. 303 11.4.5 internal reset with the watchdog timer ............................................................. 303 section 12 serial communication interface (sci) .................................................... 305 12.1 overview....................................................................................................................... .... 305 12.1.1 features................................................................................................................ 305 12.1.2 block diagram ..................................................................................................... 306 12.1.3 pin configuration................................................................................................. 307 12.1.4 register configuration......................................................................................... 307 12.2 register descriptions ........................................................................................................ 3 08 12.2.1 receive shift register (rsr) .............................................................................. 308 12.2.2 receive data register (rdr) .............................................................................. 308 12.2.3 transmit shift register (tsr) ............................................................................. 308 12.2.4 transmit data register (tdr)............................................................................. 309 12.2.5 serial mode register (smr)................................................................................ 309 12.2.6 serial control regi ster (scr).............................................................................. 312 12.2.7 serial status register (ssr) ................................................................................ 316 12.2.8 bit rate register (brr) ...................................................................................... 320 12.3 operation...................................................................................................................... ..... 331 12.3.1 overview.............................................................................................................. 331 12.3.2 operation in async hronous m ode ....................................................................... 333 12.3.3 multiprocessor communication........................................................................... 343 12.3.4 clock synchronous operation ............................................................................. 351 12.4 sci interrupt sources and the dmac .............................................................................. 362 12.5 usage notes .................................................................................................................... .. 363 12.5.1 tdr write and tdre flags................................................................................ 363 12.5.2 simultaneous multiple receive errors ................................................................ 363 12.5.3 break detection and processing........................................................................... 364 12.5.4 sending a break signal........................................................................................ 364 rev.5.00 sep. 27, 2007 page xxviii of xxxiv rej09b0398-0500 12.5.5 receive error flags and transmitter operation (clock synchronous mode only) ........................................................................ 364 12.5.6 receive data sampling timing and recei ve margin in the asynchronous mode .................................................................................................................... 364 12.5.7 constraints on dmac use .................................................................................. 366 12.5.8 cautions for clock synchronou s external clock mode ...................................... 366 12.5.9 caution for clock synchronous internal clock mode......................................... 366 section 13 high speed a/d converter ? sh7014 ? ............................................. 367 13.1 overview....................................................................................................................... .... 367 13.1.1 features................................................................................................................ 367 13.1.2 block diagram..................................................................................................... 368 13.1.3 pin configuration................................................................................................. 368 13.1.4 register configuration......................................................................................... 369 13.2 register descriptions ........................................................................................................ 3 70 13.2.1 a/d data registers a to h (addra to addrh) ............................................. 370 13.2.2 a/d control/status register (adcsr) ............................................................... 371 13.2.3 a/d control register (adcr) ............................................................................ 374 13.3 bus master interface ......................................................................................................... 3 76 13.4 operation ...................................................................................................................... .... 378 13.4.1 select-singl e mode.............................................................................................. 378 13.4.2 select-scan mode ................................................................................................ 379 13.4.3 group-single mode ............................................................................................. 380 13.4.4 group-scan mode................................................................................................ 381 13.4.5 buffer operation .................................................................................................. 383 13.4.6 simultaneous sampling operation....................................................................... 386 13.4.7 conversion star t modes....................................................................................... 388 13.4.8 a/d conversion time.......................................................................................... 391 13.5 interrupts..................................................................................................................... ...... 393 13.6 usage notes .................................................................................................................... .. 394 13.6.1 analog input voltage range ............................................................................... 394 13.6.2 av cc , av ss input volta ges .................................................................................. 394 13.6.3 input port s............................................................................................................ 394 13.6.4 conversion star t modes....................................................................................... 394 13.6.5 a/d conversion terminatio n (hd6417014r only)............................................. 394 13.6.6 handling of analog input pins ............................................................................ 395 section 14 mid-speed a/d converter ? sh7016, sh7017 ? ........................... 397 14.1 overview....................................................................................................................... .... 397 14.1.1 features................................................................................................................ 397 rev.5.00 sep. 27, 2007 page xxix of xxxiv rej09b0398-0500 14.1.2 block diagram ..................................................................................................... 398 14.1.3 pin configuration................................................................................................. 399 14.1.4 register configuration......................................................................................... 400 14.2 register descriptions ........................................................................................................ 4 01 14.2.1 a/d data register a to d (addra to addrd) ............................................... 401 14.2.2 a/d control/status register (adcsr) ............................................................... 402 14.2.3 a/d control register (adcr) ............................................................................ 404 14.3 interface with cpu............................................................................................................ 405 14.4 operation...................................................................................................................... ..... 407 14.4.1 single mode (scan = 0)..................................................................................... 407 14.4.2 scan mode (scan = 1)....................................................................................... 409 14.4.3 input sampling and a/d conversion time.......................................................... 411 14.4.4 mtu trigger input timing.................................................................................. 413 14.5 interrupt...................................................................................................................... ....... 414 14.6 a/d conversion precisi on definitions.............................................................................. 415 14.7 usage notes .................................................................................................................... .. 417 14.7.1 analog voltage settings ...................................................................................... 417 14.7.2 handling of analog input pins ............................................................................ 417 section 15 compare match timer (cmt) ................................................................... 419 15.1 overview....................................................................................................................... .... 419 15.1.1 features................................................................................................................ 419 15.1.2 block diagram ..................................................................................................... 419 15.1.3 register configuration......................................................................................... 421 15.2 register descriptions ........................................................................................................ 4 22 15.2.1 compare match timer start register (cmstr) ................................................. 422 15.2.2 compare match timer control/status register (cmcsr).................................. 423 15.2.3 compare match timer counter (cmcnt) ......................................................... 424 15.2.4 compare match timer constant register (cmcor).......................................... 425 15.3 operation...................................................................................................................... ..... 426 15.3.1 period count op eration ....................................................................................... 426 15.3.2 cmcnt count timing........................................................................................ 426 15.4 interrupts ..................................................................................................................... ...... 427 15.4.1 interrupt sources.................................................................................................. 427 15.4.2 compare match flag set timing......................................................................... 427 15.4.3 compare match flag clear timing ..................................................................... 428 15.5 usage notes .................................................................................................................... .. 429 15.5.1 contention between cmcnt write and compare match................................... 429 15.5.2 contention between cmcnt word write and incrementation........................... 430 15.5.3 contention between cmcnt byte write and incrementation ............................ 431 rev.5.00 sep. 27, 2007 page xxx of xxxiv rej09b0398-0500 section 16 pin function controller (pfc) ................................................................... 433 16.1 overview....................................................................................................................... .... 433 16.2 register configuration...................................................................................................... 44 4 16.3 register descriptions ........................................................................................................ 4 45 16.3.1 port a i/o register l (paiorl)......................................................................... 445 16.3.2 port a control registers l1, l2 (pacrl1 and pacrl2) ................................. 446 16.3.3 port b i/o register (pbior) ............................................................................... 452 16.3.4 port b control registers (pbcr1 and pbcr2)................................................... 453 16.3.5 port c i/o register (pcior) ? sh7016, sh7017 ? ........................................ 458 16.3.6 port c control register (pccr) ? sh7016, sh7017 ? ................................... 459 16.3.7 port d i/o register l (pdiorl) ? sh7016, sh7017 ? .................................. 464 16.3.8 port d control register l (pdcrl) ? sh7016, sh7017 ? ............................. 465 16.3.9 port e i/o register (peior)................................................................................ 470 16.3.10 port e control registers 1, 2 (pecr1 and pecr2) ............................................ 471 section 17 i/o ports (i/o) ................................................................................................. 475 17.1 overview....................................................................................................................... .... 475 17.2 port a......................................................................................................................... ....... 475 17.2.1 register configuration......................................................................................... 476 17.2.2 port a data register l (padrl) ........................................................................ 477 17.3 port b ......................................................................................................................... ....... 478 17.3.1 register configuration......................................................................................... 478 17.3.2 port b data register (pbdr) .............................................................................. 479 17.4 port c ? sh7016, sh7017 ? ......................................................................................... 480 17.4.1 register configuration......................................................................................... 480 17.4.2 port c data register (pcdr) .............................................................................. 481 17.5 port d ? sh7016, sh7017 ? ......................................................................................... 482 17.5.1 register configuration......................................................................................... 482 17.5.2 port d data register l (pddrl) ........................................................................ 483 17.6 port e ......................................................................................................................... ....... 484 17.6.1 register configuration......................................................................................... 484 17.6.2 port e data register (pedr)............................................................................... 485 17.7 port f......................................................................................................................... ........ 486 17.7.1 register configuration......................................................................................... 486 17.7.2 port f data regi ster (pfdr) ............................................................................... 487 section 18 128 kb flash memory (f-ztat) .............................................................. 489 18.1 features....................................................................................................................... ...... 489 18.2 overview....................................................................................................................... .... 490 18.2.1 block diagram..................................................................................................... 490 rev.5.00 sep. 27, 2007 page xxxi of xxxiv rej09b0398-0500 18.2.2 mode transitions ................................................................................................. 491 18.2.3 on-board programming modes........................................................................... 492 18.2.4 flash memory emulation in ram ...................................................................... 494 18.2.5 differences between boot mode and user program mode.................................. 495 18.2.6 block configuration............................................................................................. 496 18.3 pin configuration.............................................................................................................. 496 18.4 register configuration...................................................................................................... 49 7 18.5 register descriptions ........................................................................................................ 4 98 18.5.1 flash memory control register 1 (flmcr1)..................................................... 498 18.5.2 flash memory control register 2 (flmcr2)..................................................... 501 18.5.3 erase block register 1 (ebr1)............................................................................ 502 18.5.4 ram emulation register (ramer)................................................................... 503 18.6 on-board programming modes ........................................................................................ 504 18.6.1 boot m ode ........................................................................................................... 505 18.6.2 user program mode............................................................................................. 509 18.7 programming/erasing flash memory ............................................................................... 510 18.7.1 program mo de ..................................................................................................... 510 18.7.2 program-verify mode.......................................................................................... 511 18.7.3 erase mode .......................................................................................................... 517 18.7.4 erase-verify mode............................................................................................... 518 18.8 protection ..................................................................................................................... ..... 524 18.8.1 hardware protection ............................................................................................ 524 18.8.2 software protection.............................................................................................. 525 18.8.3 error protection.................................................................................................... 526 18.9 flash memory emulation in ram.................................................................................... 528 18.10 note on flash memory programming/erasing ................................................................. 530 18.11 flash memory prog rammer mode .................................................................................... 530 18.11.1 socket adapter pin correspondence diagram..................................................... 531 18.11.2 programmer mode operation .............................................................................. 533 18.11.3 memory read mode ............................................................................................ 534 18.11.4 auto-program mode ............................................................................................ 538 18.11.5 auto-erase mode ................................................................................................. 540 18.11.6 status read mode ................................................................................................ 542 18.11.7 status po lling ....................................................................................................... 543 18.11.8 programmer mode transition time..................................................................... 544 18.11.9 notes on memory programmi ng.......................................................................... 545 section 19 mask rom ....................................................................................................... 547 19.1 overview....................................................................................................................... .... 547 rev.5.00 sep. 27, 2007 page xxxii of xxxiv rej09b0398-0500 section 20 ram .................................................................................................................. 549 20.1 overview....................................................................................................................... .... 549 section 21 power-down state ......................................................................................... 551 21.1 overview....................................................................................................................... .... 551 21.1.1 power-down states.............................................................................................. 551 21.1.2 related register ................................................................................................... 552 21.2 standby control regist er (sbycr) ................................................................................. 553 21.3 sleep mode ..................................................................................................................... .. 554 21.3.1 transition to sleep mode..................................................................................... 554 21.3.2 canceling sleep mode ......................................................................................... 554 21.4 standby mode ................................................................................................................... 554 21.4.1 transition to standby mode................................................................................. 554 21.4.2 canceling the st andby m ode ............................................................................... 556 21.4.3 standby mode applica tion exampl e ................................................................... 557 section 22 electrical ch aracteristics (5 v 28.7 mhz) .............................................. 559 22.1 absolute maximum ratings ............................................................................................. 559 22.2 dc character istics ............................................................................................................ 560 22.3 ac character istics ............................................................................................................ 562 22.3.1 clock timi ng ....................................................................................................... 562 22.3.2 control signal timing ......................................................................................... 564 22.3.3 bus timing .......................................................................................................... 566 22.3.4 direct memory access controller timing .......................................................... 579 22.3.5 multifunction timer puls e unit timing .............................................................. 581 22.3.6 i/o port timing.................................................................................................... 582 22.3.7 watchdog timer timing...................................................................................... 583 22.3.8 serial communication in terface timing.............................................................. 583 22.3.9 high speed a/d converter timing ? sh7014 ? ............................................. 584 22.3.10 mid-speed converter timing ? sh7016, sh7017 ? ........................................ 586 22.3.11 measuring conditions for ac characteristics ..................................................... 588 22.4 a/d converter characteristics .......................................................................................... 589 appendix a on-chip s upporting module registers ................................................ 591 a.1 addresses ...................................................................................................................... .... 591 a.2 functions...................................................................................................................... ..... 600 appendix b i/o port block diagrams ........................................................................... 682 appendix c pin states ....................................................................................................... 707 rev.5.00 sep. 27, 2007 page xxxiii of xxxiv rej09b0398-0500 c.1 pin states..................................................................................................................... ...... 707 c.2 pin states of bus related signals ..................................................................................... 709 appendix d notes when converting the f-ztat application software to the mask-rom versions ................................................................................. 713 appendix e product code lineup .................................................................................. 714 appendix f package dimensions ................................................................................... 715 rev.5.00 sep. 27, 2007 page xxxiv of xxxiv rej09b0398-0500 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 1 of 716 rej09b0398-0500 section 1 sh7014/16/17 overview 1.1 sh7014/16/17 overview the sh7014/16/17 cmos single-chip microprocessors integrate a renesas technology-original architecture, high-speed cpu with peripheral functions required for system configuration. the cpu has a risc-type instruction set . most instructions can be ex ecuted in one clock cycle, which greatly improves instruction execution speed . in addition, the 32-bit internal-bus architecture enhances data processing power. with this cpu, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds. in particular, the sh7040 series has a 1-kbyte on-chip cache, which allows an improvement in cpu performance during external memory access. in addition, this lsi includes on-chip peripheral functions necessary for system configuration, such as large-capacity rom (ex cept the sh7014, which is romless) and ram, timers, a serial communication interface (sci), an a/d converter, an interrupt controller, and i/o ports. memory or peripheral lsis can be connected efficiently with an external memory access support function. this greatly reduces system cost. this lsi has an f-ztat tm * version with on-chip flash memory and a mask rom version. these versions enable users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. notes: f-ztat (flexible ztat) is a trademark of renesas technology corp. 1.1.1 sh7014/16/17 series features cpu: ? original renesas technology architecture ? 32-bit internal data bus ? general-register machine ? sixteen 32-bit general registers ? three 32-bit control registers ? four 32-bit system registers ? risc-type instruction set ? instruction length: 16-bit fixed length for improved code efficiency ? load-store architecture (basic operati ons are executed between registers) 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 2 of 716 rej09b0398-0500 ? delayed branch instructions reduce pipeline disruption during branch ? instruction set based on c language ? instruction execution time: one instruction/cycle (35 ns/instruc tion at 28.7-mhz operation) ? address space: architect ure supports 4 gbytes ? on-chip multiplier: multiplication operations (32 bits 32 bits 64 bits) and multiplication/accumulation operations (32 bits 32 bits + 64 bits 64 bits) executed in two to four cycles ? five-stage pipeline cache memory: ? 1-kbyte instruction cache ? caching of instruction codes and pc relative read data ? 4-byte line length (1 longword: 2 instruction lengths) ? 256 entry cache tags ? direct map method ? on-chip rom/ram, and on-chip i/o areas not objects of cache ? used in common with on-chip ram; 2 kbytes of on-chip ram used as address array/data array when cache is enabled interrupt controller (intc): ? seven external interrupt pins (nmi, irq 6) ? twenty-eight internal interrupt sources ? sixteen programmable priority levels bus state controller (bsc): ? supports external extended memory access ? 8-bit, or 16-bit external data bus ? memory address space divided into five areas (four areas of sram space, one area of dram space) with the followi ng settable features: ? number of wait cycles ? outputs chip-select signals for each area ? during dram space access: ? outputs ras and cas signals for dram ? can generate a ras precharge time assurance tp cycle 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 3 of 716 rej09b0398-0500 ? dram burst access function ? supports high-speed access mode for dram ? dram refresh function ? programmable refresh interval ? supports cas-before-ras refresh and self-refresh modes ? wait cycles can be insert ed using an external wait signal ? address data multiplex i/o devices can be accessed note: no bus release direct memory access controll er (dmac) (2 channels): ? supports cycle-steal and burst transfers ? supports single address mode and dual address mode transfers ? priority order: fixed at channel 0 > channel 1 ? transfer counter: 16 bits ? transfer request sources: external dreq input, auto-request, and on-chip supporting modules ? address space: 4 gbytes ? choice of 8-, 16-, or 32-bit transfer data size multifunction timer/pulse unit (mtu) (3 channels): ? maximum 8 types of waveform output or maximum 16 types of pulse i/o processing possible based on 16-bit timer, 3 channels ? 8 dual-use output compare/input capture registers ? 8 independent comparators ? 8 types of counter input clock ? input capture function ? pulse output mode ? one shot, toggle, pwm ? phase calculation mode ? 2-phase encoder calculation processing compare match timer (cmt) (two channels): ? 16-bit free-running counter ? one compare register ? generates an interrupt request upon compare match 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 4 of 716 rej09b0398-0500 watchdog timer (wdt) (one channel): ? watchdog timer or interval timer ? count overflow can generate an internal reset, external signal, or interrupt serial communication interf ace (sci) (two channels): (per channel): ? asynchronous or clock-synchronous mode is selectable ? can transmit and receive simultaneously (full duplex) ? on-chip dedicated baud rate generator ? multiprocessor communication function i/o ports: ? sh7014 ? input/output: 35 ? input: 8 ? total: 43 ? sh7016/17 ? input/output: 74 ? input: 8 ? total: 82 a/d converter: ? 10 bits 8 channels ? the sh7014 has a high-speed a/d converter, while the sh7016 and sh7017 have a mid- speed a/d converter. on-chip memory: ? rom ? sh7014: romless ? sh7016: 64 kbytes (mask rom) ? sh7017: 128 kbytes (flash rom) ? ram: sh7014/16: 3 kbytes (1 kbyte when cache is used) sh7017: 4 kbytes (2 kbytes when cache is used) 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 5 of 716 rej09b0398-0500 operating modes: ? operating modes ? non-extended rom mode (sh7014/16/17) ? extended rom mode (sh7016/17) ? single-chip mode (sh7016/17) ? processing states ? program execution state ? exception processing state ? power-down modes ? sleep mode ? software standby mode clock pulse generator (cpg): ? on-chip clock pulse generator ? on-chip clock-doubling pll circuit product lineup: product code on-chip rom on-chip ram a/d precision frequency/ voltage temperature package hd6417014f28 romless 3 kb 15 lsb (high-speed a/d) 28.7 mhz/5 v ? 20 to +75c fp-112 hd6417014rf28 romless 3 kb 8 lsb (high-speed a/d) 28.7 mhz/5 v ? 20 to +75c fp-112 hd6437016f28 64 kb mask rom 3 kb 4 lsb (mid-speed a/d) 28.7 mhz/5 v ? 20 to +75c fp-112 hd64f7017f28 128 kb flash memory 4 kb 4lsb (mid-speed a/d) 28.7 mhz/5 v ? 20 to +75c fp-112 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 6 of 716 rej09b0398-0500 1.2 block diagram figure 1.1 is a block diagram of the sh7014. figure 1.2 is a block diagram of the sh7016/17. a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 md3 md2 md1 md0 nmi extal xtal v cc v cc v cc pllvcc pllcap pllvss v cc v cc v ss v ss v ss v ss v ss v ss v ss v ss av cc av ss res wdtovf pb9/ irq7 /a21 pb8/ irq6 /a20/ wait pb7/a19 pb6/a18 pb5/ irq3 /rdwr pb4/ irq2 / cash pb3/ irq1 / casl pb2/ irq0 / ras a17 a16 pa15/ck rd wrh wrl cs1 cs0 pa9/tclkd/ irq3 pa8/tclkc/ irq2 pa7/tclkb/ cs3 pa6/tclka/ cs2 pa5/sck1/ dreq1 / irq1 pa4/txd1 pa3/rxd1 pa2/sck0/ dreq0 / irq0 pa1/txd0 pa0/rxd0 pe15/dack1 pe14/dack0/ ah pe13 pe12 pe11 pe10 pe9 pe8 pe7/tioc2b pe6/tioc2a pe5/tioc1b pe4/tioc1a pe3/tioc0d/drak1 pe2/tioc0c/ dreq1 pe1/tioc0b/drak0 pe0/tioc0a/ dreq0 : peripheral address bus : peripheral data bus : internal address bus : internal upper data bus : internal lower data bus pll pf7/an7 pf6/an6 pf5/an5 pf4/an4 pf3/an3 pf2/an2 pf1/an1 pf0/an0 ram (3 kb)/ cache (1 kb) cpu direct memory access controller interrupt controller bus state controller serial communi- cation interface ( 2 channels) multifunction timer/ pulse unit compare match timer ( 2 channels) a/d converter watch- dog timer v ss v ss v ss figure 1.1 block diagram of the sh7014 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 7 of 716 rej09b0398-0500 pa15/ck pa14/ rd pa13/ wrh pa12/ wrl pa11/ cs1 pa10/ cs0 pa9/tclkd/ irq3 pa8/tclkc/ irq2 pa7/tclkb/ cs3 pa6/tclka/ cs2 pa5/sck1/ dreq1 / irq1 pa4/txd1 pa3/rxd1 pa2/sck0/ dreq0 / irq0 pa1/txd0 pa0/rxd0 pb9/ irq7 /a21 pb8/ irq6 /a20/ wait pb7/a19 pb6/a18 pb5/ irq3 /rdwr pb4/ irq2 / cash pb3/ irq1 / casl pb2/ irq0 / ras pb1/a17 pb0/a16 pc15/a15 pc14/a14 pc13/a13 pc12/a12 pc11/a11 pc10/a10 pc9/a9 pc8/a8 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 pd15/d15 pd14/d14 pd13/d13 pd12/d12 pd11/d11 pd10/d10 pd9/d9 pd8/d8 pd7/d7 pd6/d6 pd5/d5 pd4/d4 pd3/d3 pd2/d2 pd1/d1 pd0/d0 pf7/an7 pf6/an6 pf5/an5 pf4/an4 pf3/an3 pf2/an2 pf1/an1 pf0/an0 pe14/dack0/ ah pe13 pe12 pe11 pe10 pe9 pe8 pe7/tioc2b pe6/tioc2a pe5/tioc1b pe4/tioc1a pe3/tioc0d/drak1 pe2/tioc0c/ dreq1 pe1/tioc0b/drak0 pe0/tioc0a/ dreq0 : peripheral address bus : peripheral data bus : internal address bus : internal upper data bus : internal lower data bus res wdtovf md3 md2 md1 md0 nmi extal xtal pllv cc pllcap pllv ss v cc /fwp * v cc v cc v cc v cc v ss v ss v ss vss vss v ss v ss v ss v ss v ss v ss av cc av ss serial communi- cation interface ( 2 channels) multifunction timer/ pulse unit interrupt controller bus state controller compare match timer ( 2 channels) a/d converter watch- dog timer cpu direct memory access controller flash rom (128 kb)/ mask rom (64 kb) ram (4 kb/3 kb)/ cache (1 kb) pll pe15/dack1 note: * v cc in the sh7016, fwp in the sh7017 (except fwe pin in the programmer mode). figure 1.2 block diagram of the sh7016, sh7017 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 8 of 716 rej09b0398-0500 1.3 pin arrangement and pin functions 1.3.1 pin arrangement figure 1.3 shows the pin arrangement for the sh7014 (top view). pb13 pe12 pe11 v ss pe10 pe9 pe8 pe7/tioc2b pe6/tioc2a v cc pe5/tioc1b v ss av cc pf7/an7 pf6/an6 av ss pf5/an5 pf4/an4 pf3/an3 pf2/an2 pf1/an1 pf0/an0 v ss pe4/tioc1a pe3/tioc0d/drak1 pe2/tioc0c/ dreq1 pe1/tioc0b/drak0 pe0/tioc0a/ dreq0 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 pb6/a18 pb7/a19 pb8/ irq6 /a20/ wait pb9/ irq7 /a21 v ss rd wdtovf wrh v cc wrl v ss cs0 pa9/tclkd/ irq3 pa7/tclkb/ cs3 pa6/tclka/ cs2 pa5/sck1/ dreq1 / irq 1 pa4/txd1 pa3/rxd1 pa2/sck0/ dreq0 / irq 0 pa1/txd0 pa0/rxd0 d15 d14 d13 v ss d12 res pa15/ck pllv ss pllcap pllv cc md0 md1 v cc nmi md2 extal md3 xtal v ss d0 d1 d2 d3 d4 v cc d5 d6 d7 v ss d8 d9 d10 d11 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 cs1 pa8/tclkc/ irq2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 pe14/dack0/ ah pe15/dack1 v ss a0 a1 a2 a3 a4 a5 a6 a7 a11 a12 a13 a14 a15 a16 v cc a17 pb2/ irq0 / ras pb3/ irq1 / casl pb4/ irq2 / cash v ss pb5/ irq3 /rdwr a8 a9 a10 v ss fp-112 figure 1.3 sh7014 pin arrangement (fp-112 top view) 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 9 of 716 rej09b0398-0500 figure 1.4 shows the pin arrangement for the 144-pin qfp pin arrangement. fp-112 pe14/dack0/ ah pe15/dack1 v ss pc0/a0 pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pc6/a6 pc7/a7 pc8/a8 pc9/a9 pc10/a10 pc11/a11 pc12/a12 pc13/a13 pc14/a14 pc15a15 pb0/a16 v cc pb1/a17 v ss pb2 /irq0 / ras pb3/ irq1 / casl pb4/ irq2 / cash v ss pb5/ irq3 /rdwr res pa15/ck pllv ss pllcap pllv cc md0 md1 vcc/fwp * nmi md2 extal md3 xtal v ss pd0/d0 pd1/d1 pd2/d2 pd3/d3 pd4/d4 v cc pd5/d5 pd6/d6 pd7/d7 v ss pd8/d8 pd9/d9 pd10/d10 pd11/d11 pe0/tioc0a/ dreq0 pe1/tioc0b/drak0 pe2/tioc0c/ dreq1 pe3/tioc0d/drak1 pe4/tioc1a v ss pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 av ss pf6/an6 pf7/an7 av cc v ss pe5/tioc1b v cc pe6/tioc2a pe7/tioc2b pe8 pe9 pe10 vss pe11 pe12 pe13 pd12/d12 v ss pd13/d13 pd14/d14 pd15/d15 pa0/rxd0 pa1/txd0 pa2/sck0/ dreq0 / irq 0 pa3/rxd1 pa4/txd1 pa5/sck1/ dreq1 / irq 1 pa6/tclka/ cs2 pa7/tclkb/ cs3 pa8/tclkc/ irq2 pa9/tclkd/ irq3 pa10/ cs0 pa11/ cs1 vss pa12/ wrl vcc pa13/ wrh wdtovf pa14/ rd vss pb9/ irq7 /a21 pb8/ irq6 /a20/ wait pb7/a19 pb6/a18 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 note: * v cc in the sh7016, fwp in the sh7017 (except fwe pin in the programmer mode). figure 1.4 sh7016, sh7017 pin arrangement (qfp-112 top view) 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 10 of 716 rej09b0398-0500 1.3.2 pin arrangement by mode table 1.1 pin arrangement by mode for sh7017f (fp-112 pin) pin no. mcu mode programmer mode 1 pe14/dack0/ ah nc 2 pe15/dack1 nc 3 v ss v ss 4 pc0/a0 a0 5 pc1/a1 a1 6 pc2/a2 a2 7 pc3/a3 a3 8 pc4/a4 a4 9 pc5/a5 a5 10 pc6/a6 a6 11 pc7/a7 a7 12 pc8/a8 a8 13 pc9/a9 a9 14 pc10/a10 a10 15 pc11/a11 a11 16 pc12/a12 a12 17 pc13/a13 a13 18 pc14/a14 a14 19 pc15/a15 a15 20 pb0/a16 a16 21 v cc v cc 22 pb1/a17 nc 23 v ss v ss 24 pb2/ irq0 / ras nc 25 pb3/ irq1 / casl nc 26 pb4/ irq2 / cash a17 27 v ss v ss 28 pb5/ irq3 /rdwr nc 29 pb6/a18 nc 30 pb7/a19 nc 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 11 of 716 rej09b0398-0500 pin no. mcu mode programmer mode 31 pb8/ irq6 /a20/ wait nc 32 pb9/ irq7 /a21 nc 33 v ss v ss 34 pa14/ rd nc 35 wdtovf nc 36 pa13/ wrh nc 37 v cc v cc 38 pa12/ wrl nc 39 v ss v ss 40 pa11/ cs1 nc 41 pa10/ cs0 nc 42 pa9/tclkd/ irq3 ce 43 pa8/tclkc/ irq2 oe 44 pa7/tclkb/ cs3 we 45 pa6/tclka/ cs2 nc 46 pa5/sck1/ dreq1 / irq1 v cc 47 pa4/txd1 nc 48 pa3 /rxd1 nc 49 pa2/sck0/ dreq0 / irq0 v cc 50 pa1/txd0 v cc 51 pa0/rxd0 nc 52 pd15/d15 nc 53 pd14/d14 nc 54 pd13/d13 nc 55 v ss v ss 56 pd12/d12 nc 57 pd11/d11 nc 58 pd10/d10 nc 59 pd9/d9 nc 60 pd8/d8 nc 61 v ss v ss 62 pd7/d7 d7 63 pd6/d6 d6 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 12 of 716 rej09b0398-0500 pin no. mcu mode programmer mode 64 pd5/d5 d5 65 v cc v cc 66 pd4/d4 d4 67 pd3/d3 d3 68 pd2/d2 d2 69 pd1/d1 d1 70 pd0/d0 d0 71 v ss v ss 72 xtal xtal 73 md3 md3 74 extal extal 75 md2 md2 76 nmi v cc 77 v cc (fwp) fwe 78 md1 md1 79 md0 md0 80 pllv cc pllv cc 81 pllcap pllcap 82 pllv ss pllv ss 83 pa15/ck nc 84 res res 85 pe0/tioc0a/ dreq0 nc 86 pe1/tioc0b/drak0 nc 87 pe2/tioc0c/ dreq1 nc 88 pe3/tioc0d/drak1 nc 89 pe4/tioc1a nc 90 v ss v ss 91 pf0/an0 v ss 92 pf1/an1 v ss 93 pf2/an2 v ss 94 pf3/an3 v ss 95 pf4/an4 v ss 96 pf5/an5 v ss 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 13 of 716 rej09b0398-0500 pin no. mcu mode programmer mode 97 av ss v ss 98 pf6/an6 v ss 99 pf7/an7 v ss 100 av cc v cc 101 v ss v ss 102 pe5/tioc1b nc 103 v cc v cc 104 pe6/tioc2a nc 105 pe7/tioc2b nc 106 pe8 nc 107 pe9 nc 108 pe10 nc 109 v ss v ss 110 pe11 nc 111 pe12 nc 112 pe13 nc 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 14 of 716 rej09b0398-0500 1.3.3 pin functions table 1.2 lists the pin functions. table 1.2 pin functions classification symbol i/o name function power supply v cc i supply connects to power supply. connect all v cc pins to the system supply. no operation will occur if there are any open pins. v ss i ground connects to ground. connect all v ss pins to the system ground. no operation will occur if there are any open pins. clock pllv cc i pll supply on-chip pll oscillator supply. pllv ss i pll ground on-chip pll oscillator ground. pllcap i pll capacitance on-chip pll oscillator external capacitance connection pin. extal i external clock connect a crystal oscillator. also, an external clock can be input to the extal pin. xtal i crystal connect a crystal oscillator. ck o system clock supplies the system clock to peripheral devices. system control res i power-on reset power-on reset when low wdtovf o watchdog timer overflow overflow output signal from wdt operating mode control md0 to md3 i mode set determines the operating mode. do not change input value during operation. fwp i flash memory write protect protects flash memory from being written or deleted. interrupts nmi i non-maskable interrupt non-maskable interrupt request pin. enables selection of whether to accept on the rising or falling edge. irq0 to irq3 , irq6 , irq7 i interrupt requests 0 to 3, 6,7 maskable interrupt request pins. allows selection of level input and edge input. address bus a0 to a21 o address bus outputs addresses. 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 15 of 716 rej09b0398-0500 classification symbol i/o name function data bus d0 to d15 i/o data bus 16-bit bidirectional data bus bus control cs0 to cs3 o chip selects 0 to 3 chip select signals for external memory or devices. rd o read indicates reading from an external device. wrh o upper write indicates writing the upper 8 bits of external data. wrl o lower write indicates writing the lower 8 bits of external data. wait i wait input causes insertion of wait cycles into the bus cycle during external space access. ras o row address strobe timing signal for dram row address strobe. cash o upper column address strobe timing signal for dram column address strobe. output when the upper 8 bits of data are accessed. casl o lower column address strobe timing signal for dram column address strobe. output when the lower 8 bits of data are accessed. rdwr o dram read/write dram write strobe signal. ah o address hold address hold timing signal for devices using an address/data multiplex bus. multifunction timer pulse unit (mtu) tclka tclkb tclkc tclkd i mtu timer clock input input pins for external clocks to the mtu counter. tioc0a tioc0b tioc0c tioc0d i/o mtu input capture/output compare (channel 0) channel 0 input capture input/output compare output/pwm output pins. 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 16 of 716 rej09b0398-0500 classification symbol i/o name function multifunction timer pulse unit (mtu) tioc1a tioc1b i/o mtu input capture/output compare (channel 1) channel 1 input capture input/output compare output/pwm output pins. tioc2a tioc2b i/o mtu input capture/output compare (channel 2) channel 2 input capture input/output compare output/pwm output pins. dreq0 to dreq1 i dma transfer request (channels 0, 1) input pin for external requests for dma transfer. direct memory access controller (dmac) drak0 to drak1 o dreq request acknowledgment (channels 0, 1) output the input sampling acknowledgment of external dma transfer requests. dack0 to dack1 o dma transfer strobe (channels 0, 1) output a strobe to the external i/o of external dma transfer requests. txd0 to txd1 o transmit data (channels 0, 1) sci0, sci1 transmit data output pins. serial communication interface (sci) rxd0 to rxd1 i receive data (channels 0, 1) sci0, sci1 receive data input pins. sck0 to sck1 i/o serial clock (channels 0, 1) sci0, sci1 clock input/output pins. a/d converter av cc i analog supply analog supply; connected to v cc . av ss i analog ground analog supply; connected to v ss . an0 to an7 i analog input analog signal input pins. i/o ports pa0 to pa9, pa15 (sh7014) pa0 to pa15 (sh7016/17) i/o general purpose port general purpose input/output port pins. each bit can be designated for input/output. pb2 to pb9 (sh7014) pb0 to pb9 (sh7016/17) i/o general purpose port general purpose input/output port pins. each bit can be designated for input/output. pc0 to pc15 (sh7016/17) i/o general purpose port general purpose input/output port pins. each bit can be designated for input/output. 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 17 of 716 rej09b0398-0500 classification symbol i/o name function i/o ports pd0 to pd15 (sh7016/17) i/o general purpose port general purpose input/output port pins. each bit can be designated for input/output. pe0 to pe15 i/o general purpose port general purpose input/output port pins. each bit can be designated for input/output. pf0 to pf7 i general purpose port general purpose input port pins. usage notes 1. unused input pins should be pulled up or pulled down. 2. the wdtovf pin should not be pulled down in the sh7017 f-ztat version. however, if it is necessary to pull this pin down, a resistance of 100 k or higher should be used. 1. sh7014/16/17 overview rev.5.00 sep. 27, 2007 page 18 of 716 rej09b0398-0500 2. cpu rev.5.00 sep. 27, 2007 page 19 of 716 rej09b0398-0500 section 2 cpu 2.1 register configuration the register set consists of sixteen 32-bit general registers, three 32-bit control registers and four 32-bit system registers. 2.1.1 general registers (rn) the sixteen 32-bit general registers (rn) are numbered r0 to r15. general registers are used for data processing and address calculation. r0 is also used as an index register. several instructions have r0 fixed as their only usable register. r15 is used as the hardware stack pointer (sp). saving and recovering the status register (sr) and program counter (pc) in exception processing is accomplished by referencing the stack using r15. figure 2.1 shows the general registers. r0 * 1 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15, sp (hardware stack pointer) * 2 0 31 1. 2. r0 functions as an index register in the indirect indexed register addressing mode and indirect indexed gbr addressing mode. in some instructions, r0 functions as a fixed source register or destination register. r15 functions as a hardware stack pointer (sp) during exception processing. notes: figure 2.1 general registers 2. cpu rev.5.00 sep. 27, 2007 page 20 of 716 rej09b0398-0500 2.1.2 control registers the 32-bit control registers consist of the 32-bit status register (sr), global base register (gbr), and vector base register (vbr). the status register indicates processing states. the global base register functions as a base address for the indirect gbr addressing mode to transfer data to the registers of on-chip peripheral modules. the vector base register functions as the base address of the exception processing vector area (including interrupts). figure 2.2 shows a control register. 9876543210 m q i3 i2 i1 i0 st 0 0 31 31 gbr vbr sr 31 s bit: used by the mac instruction. reserved bits. this bit always read 0. the write value should always be 0. reserved bits. this bit always read 0. the write value should always be 0. bits i0 to i3: interrupt mask bits. m and q bits: used by the div0u, div0s, and div1 instructions. global base re g ister (gbr): indicates the base address of the indirect gbr addressin g mode. the indirect gbr addressin g mode is used in data transfer for on-chip peripheral modules re g ister areas and in lo g ic operations. vector base re g ister (vbr): stores the base address of the exception processin g vector area. sr: status re g ister t bit: the movt, cmp/cond, tas, tst, bt (bt/s), bf (bf/s), sett, and clrt instructions use the t bit to indicate true (1) or false (0). the addv, addc, subv, subc, div0u, div0s, div1, negc, shar, shal, shlr, shll, rotr, rotl, rotcr, and rotcl instructions also use the t bit to indicate carry/borrow or overflow/underflow. figure 2.2 control registers 2. cpu rev.5.00 sep. 27, 2007 page 21 of 716 rej09b0398-0500 2.1.3 system registers system registers consist of four 32-bit registers: high and low multiply and accumulate registers (mach and macl), the procedure register (pr), and the program counter (pc). the multiply and accumulate registers store the results of multiply and accumulate operations. the procedure register stores the return address from the subroutine procedure. the program counter stores program addresses to control the flow of the processing. figure 2.3 shows a system register. macl pr pc mach 31 0 0 0 31 31 multiply and accumulate (mac) registers high and low (mach, macl): stores the results of multiply and accumulate operations. procedure register (pr): stores a return address from a subroutine procedure. program counter (pc): indicates the fourth byte (second instruction) after the current instruction. figure 2.3 system registers 2.1.4 initial values of registers table 2.1 lists the values of the registers after reset. table 2.1 initial values of registers classification register initial value general registers r0 to r14 undefined r15 (sp) value of the stack pointer in the vector address table control registers sr bits i3 to i0 are 1111 (h'f), reserved bits are 0, and other bits are undefined gbr undefined vbr h'00000000 system registers mach, macl, pr undefined pc value of the program counter in the vector address table 2. cpu rev.5.00 sep. 27, 2007 page 22 of 716 rej09b0398-0500 2.2 data formats 2.2.1 data format in registers register operands are always longwords (32 bits). when the memory operand is only a byte (8 bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register (figure 2.4). 31 0 longword figure 2.4 longword operand 2.2.2 data format in memory memory data formats are classified into bytes, words, and longwords. byte data can be accessed from any address, but an address error will occur if you try to access word data starting from an address other than 2n or longword data starting from an address other than 4n. in such cases, the data accessed cannot be guaranteed. the hardware stack area, referr ed to by the hardware stack pointer (sp, r15), uses only l ongword data starting from address 4n because this area holds the program counter and status register (figure 2.5). 31 0 15 23 7 byte byte byte byte word word address 2n address 4n longword address m address m + 2 address m + 1 address m + 3 figure 2.5 byte, word, and longword alignment 2.2.3 immediate data format byte (8-bit) immediate data resides in an inst ruction code. immediate data accessed by the mov, add, and cmp/eq instructions is sign-extended and handled in registers as longword data. immediate data accessed by the tst, and, or, and xor instructions is zero-extended and handled as longword data. consequently, and instructions with immediate data always clear the upper 24 bits of the destination register. 2. cpu rev.5.00 sep. 27, 2007 page 23 of 716 rej09b0398-0500 word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. an immediate data transfer inst ruction (mov) accesses the memory table using the pc relative addressing mode with displacement. 2.3 instruction features 2.3.1 risc-type instruction set all instructions are risc type. th is section details their functions. 16-bit fixed length : all instructions are 16 bits long, increasing program code efficiency. one instruction per cycle : the microprocessor can execute basic instructions in one cycle using the pipeline system. instructions are executed in 35 ns at 28.7 mhz. data length : longword is the standard data length for all operations. memory can be accessed in bytes, words, or longwords. byte or word data accessed from memory is sign-extended and handled as longword data. immediate data is sign-extended for arithmetic operations or zero- extended for logic operations. it also is handled as longword data (table 2.2). table 2.2 sign extension of word data sh7014/16/17 cpu description example of conventional cpu mov.w @(disp,pc),r1 add r1,r0 .data.w h'1234 data is sign-extended to 32 bits, and r1 becomes h'00001234. it is next operated upon by an add instruction. add.w #h'1234,r0 note: @(disp, pc) accesses the immediate data. load-store architecture : basic operations are executed betw een registers. for operations that involve memory access, data is loaded to the registers and executed (l oad-store architecture). instructions such as and that manipulate bits, however, are executed directly in memory. delayed branch instructions : unconditional branch instructions are delayed. executing the instruction that follows the branch instruction and then branching reduces pipeline disruption during branching (table 2.3). there are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions. 2. cpu rev.5.00 sep. 27, 2007 page 24 of 716 rej09b0398-0500 table 2.3 delayed branch instructions sh7014/16/17 cpu description example of conventional cpu bra trget add r1,r0 executes an add before branching to trget add.w r1,r0 bra trget multiplication/accumulation operation : 16-bit 16-bit 32-bit multiplication operations are executed in one to two cycles. 16-bit 16-bit + 64-bit 64-bit multiplication/accumulation operations are executed in tw o to three cycles. 32-bit 32-bit 64-bit and 32-bit 32-bit + 64bit 64-bit multiplication/accumulation operations are executed in two to four cycles. t bit : the t bit in the status register changes acco rding to the result of the comparison, and in turn is the condition (true/false) that determines if the program will branch. the number of instructions that change the t bit is kept to a minimum to improve the processing speed (table 2.4). table 2.4 t bit sh7014/16/17 cpu description example of conventional cpu cmp/ge r1,r0 bt trget0 bf trget1 t bit is set when r0 r1. the program branches to trget0 when r0 r1 and to trget1 when r0 < r1. cmp.w r1,r0 bge trget0 blt trget1 add #1,r0 cmp/eq #0,r0 bt trget t bit is not changed by add. t bit is set when r0 = 0. the program branches if r0 = 0. sub.w #1,r0 beq trget immediate data : byte (8-bit) immediate data resides in instruction code. word or longword immediate data is not input via instruction codes but is stored in a memory table. an immediate data transfer instruction (mov) accesses the memo ry table using the pc relative addressing mode with displacement (table 2.5). 2. cpu rev.5.00 sep. 27, 2007 page 25 of 716 rej09b0398-0500 table 2.5 immediate data accessing classification sh7014/16/17 cpu example of conventional cpu 8-bit immediate mov #h'12,r0 mov.b #h'12,r0 16-bit immediate mov.w @(disp,pc),r0 ................. .data.w h'1234 mov.w #h'1234,r0 32-bit immediate mov.l @(disp,pc),r0 ................. .data.l h'12345678 mov.l #h'12345678,r0 note: @(disp, pc) accesses the immediate data. absolute address : when data is accessed by absolute addre ss, the value already in the absolute address is placed in the memory table. loadi ng the immediate data when the instruction is executed transfers that value to the register and the data is acce ssed in the indirect register addressing mode (table 2.6). table 2.6 absolute address accessing classification sh7014/16/17 cpu example of conventional cpu absolute address mov.l @(disp,pc),r1 mov.b @r1,r0 .................. .data.l h'12345678 mov.b @h'12345678,r0 note: @(disp,pc) accesses the immediate data. 16-bit/32-bit displacement : when data is accessed by 16-bit or 32-bit displacement, the pre- existing displacement value is placed in the memory table. loadi ng the immediate data when the instruction is executed transfers th at value to the register and the data is accessed in the indirect indexed register addressing mode (table 2.7). table 2.7 displacement accessing classification sh7014/16/17 cpu example of conventional cpu 16-bit displacement mov.w @(disp,pc),r0 mov.w @(r0,r1),r2 .................. .data.w h'1234 mov.w @(h'1234,r1),r2 note: @(disp,pc) accesses the immediate data. 2. cpu rev.5.00 sep. 27, 2007 page 26 of 716 rej09b0398-0500 2.3.2 addressing modes table 2.8 describes addressing mode s and effective address calculation. table 2.8 addressing modes and effective addresses addressing mode instruction format effective addresses calculation equation direct register addressing rn the effective address is register rn. (the operand is the contents of register rn.) ? indirect register addressing @rn the effective address is the content of register rn. rn rn rn post-increment indirect register addressing @rn+ the effective address is the content of register rn. a constant is added to the content of rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. rn rn 1/2/4 + rn + 1/2/4 rn (after the instruction executes) byte: rn + 1 rn word: rn + 2 rn longword: rn + 4 rn pre-decrement indirect register addressing @?rn the effective address is the value obtained by subtracting a constant from rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. rn 1/2/4 rn ? 1/2/4 ? rn ? 1/2/4 byte: rn ? 1 rn word: rn ? 2 rn longword: rn ? 4 rn (instruction executed with rn after calculation) 2. cpu rev.5.00 sep. 27, 2007 page 27 of 716 rej09b0398-0500 addressing mode instruction format effective addresses calculation equation indirect register addressing with displacement @(disp:4, rn) the effective address is rn plus a 4-bit displacement (disp). the value of disp is zero- extended, and remains the same for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. rn rn + disp 1/2/4 + 1/2/4 disp (zero-extended) byte: rn + disp word: rn + disp 2 longword: rn + disp 4 indirect indexed register addressing @(r0, rn) the effective address is the rn value plus r0. rn r0 rn + r0 + rn + r0 indirect gbr addressing with displacement @(disp:8, gbr) the effective address is the gbr value plus an 8-bit displacement (disp). the value of disp is zero- extended, and remains the same for a byte opera- tion, is doubled for a word operation, and is quadrupled for a longword operation. gbr 1/2/4 gbr + disp 1/2/4 + disp (zero-extended) byte: gbr + disp word: gbr + disp 2 longword: gbr + disp 4 2. cpu rev.5.00 sep. 27, 2007 page 28 of 716 rej09b0398-0500 addressing mode instruction format effective addresses calculation equation indirect indexed gbr addressing @(r0, gbr) the effective address is the gbr value plus the r0. gbr r0 gbr + r0 + gbr + r0 pc relative addressing with displacement @(disp:8, pc) the effective address is the pc value plus an 8-bit displacement (disp). the value of disp is zero- extended, and is doubled for a word operation, and quadrupled for a longword operation. for a longword operation, the lowest two bits of the pc value are masked. pc h'fffffffc pc + disp 2 or pc & h'fffffffc + disp 4 + 2/4 & (for longword) disp (zero-extended) word: pc + disp 2 longword: pc & h'fffffffc + disp 4 2. cpu rev.5.00 sep. 27, 2007 page 29 of 716 rej09b0398-0500 addressing mode instruction format effective addresses calculation equation pc relative addressing disp:8 the effective address is the pc value sign-extended with an 8-bit displacement (disp), doubled, and added to the pc value. pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2 disp:12 the effective address is the pc value sign-extended with a 12-bit displacement (disp), doubled, and added to the pc value. pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2 rn the effective address is the register pc value plus rn. pc rn pc + rn + pc + rn immediate addressing #imm:8 the 8-bit immediate data (imm) for the tst, and, or, and xor instructions are zero-extended. ? #imm:8 the 8-bit immediate data (imm) for the mov, add, and cmp/eq instructions are sign-extended. ? #imm:8 the 8-bit immediate data (imm) for the trapa instruction is zero-extended and is quadrupled. ? 2. cpu rev.5.00 sep. 27, 2007 page 30 of 716 rej09b0398-0500 2.3.3 instruction format table 2.9 lists the instruction formats for the source operand and the destination operand. the meaning of the operand depends on the instruction code. the symbols are used as follows: ? xxxx: instruction code ? mmmm: source register ? nnnn: destination register ? iiii: immediate data ? dddd: displacement table 2.9 instruction formats instruction formats source operand destination operand example 0 format xxxx xxxx xxxx xxxx 15 0 ? ? nop ? nnnn: direct register movt rn n format xxxx xxxx xxxx nnnn 15 0 control register or system register nnnn: direct register sts mach,rn control register or system register nnnn: indirect pre- decrement register stc.l sr,@-rn mmmm: direct register control register or system register ldc rm,sr m format xxxx mmmm xxxx xxxx 15 0 mmmm: indirect post-increment register control register or system register ldc.l @rm+,sr mmmm: direct register ? jmp @rm mmmm: pc relative using rm ? braf rm 2. cpu rev.5.00 sep. 27, 2007 page 31 of 716 rej09b0398-0500 instruction formats source operand destination operand example mmmm: direct register nnnn: direct register add rm,rn nm format nnnn xxxx xxxx 15 0 mmmm mmmm: direct register nnnn: indirect register mov.l rm,@rn mmmm: indirect post-increment register (multiply/ accumulate) nnnn * : indirect post-increment register (multiply/ accumulate) mach, macl mac.w @rm+,@rn+ mmmm: indirect post-increment register nnnn: direct register mov.l @rm+,rn mmmm: direct register nnnn: indirect pre- decrement register mov.l rm,@-rn mmmm: direct register nnnn: indirect indexed register mov.l rm,@(r0,rn) md format xxxx dddd 15 0 mmmm xxxx mmmmdddd: indirect register with displacement r0 (direct register) mov.b @(disp,rm),r0 nd4 format xxxx xxxx dddd 15 0 nnnn r0 (direct register) nnnndddd: indirect register with displacement mov.b r0,@(disp,rn) nmd format nnnn xxxx dddd 15 0 mmmm mmmm: direct register nnnndddd: indirect register with displacement mov.l rm,@(disp,rn) mmmmdddd: indirect register with displacement nnnn: direct register mov.l @(disp,rm),rn 2. cpu rev.5.00 sep. 27, 2007 page 32 of 716 rej09b0398-0500 instruction formats source operand destination operand example d format dddd xxxx 15 0 xxxx dddd dddddddd: indirect gbr with displacement r0 (direct register) mov.l @(disp,gbr),r0 r0 (direct register) dddddddd: indirect gbr with displacement mov.l r0,@(disp,gbr) dddddddd: pc relative with displacement r0 (direct register) mova @(disp,pc),r0 dddddddd: pc relative ? bf label d12 format dddd xxxx 15 0 dddd dddd dddddddddddd: pc relative ? bra label (label = disp + pc) nd8 format dddd nnnn xxxx 15 0 dddd dddddddd: pc relative with displacement nnnn: direct register mov.l @(disp,pc),rn iiiiiiii: immediate indirect indexed gbr and.b #imm,@(r0,gbr) i format xxxx xxxx i i i i 15 0 i i i i iiiiiiii: immediate r0 (direct register) and #imm,r0 iiiiiiii: immediate ? trapa #imm ni format nnnn i i i i xxxx 15 0 i i i i iiiiiiii: immediate nnnn: direct register add #imm,rn note: * in multiply/accumulate instructions, nnnn is the source register. 2. cpu rev.5.00 sep. 27, 2007 page 33 of 716 rej09b0398-0500 2.4 instruction set by classification table 2.10 classification of instructions classification types operation code function no. of instructions data transfer 5 mov data transfer, immediate data transfer, peripheral module data transfer, structure data transfer 39 mova effective address transfer movt t bit transfer swap swap of upper and lower bytes xtrct extraction of the middle of registers connected 21 add binary addition 33 arithmetic operations addc binary addition with carry addv binary addition with overflow check cmp/cond comparison div1 division div0s initialization of signed division div0u initialization of unsigned division dmuls signed double-length multiplication dmulu unsigned double-length multiplication dt decrement and test exts sign extension extu zero extension mac multiply/accumulate, double-length multiply/accumulate operation mul double-length multiply operation muls signed multiplication mulu unsigned multiplication neg negation negc negation with borrow sub binary subtraction subc binary subtraction with borrow subv binary subtraction with underflow 2. cpu rev.5.00 sep. 27, 2007 page 34 of 716 rej09b0398-0500 classification types operation code function no. of instructions 6 and logical and 14 logic operations not bit inversion or logical or tas memory test and bit set tst logical and and t bit set xor exclusive or shift 10 rotl one-bit left rotation 14 rotr one-bit right rotation rotcl one-bit left rotation with t bit rotcr one-bit right rotation with t bit shal one-bit arithmetic left shift shar one-bit arithmetic right shift shll one-bit logical left shift shlln n-bit logical left shift shlr one-bit logical right shift shlrn n-bit logical right shift branch 9 bf conditional branch, conditional branch with delay (branch when t = 0) 11 bt conditional branch, conditional branch with delay (branch when t = 1) bra unconditional branch braf unconditional branch bsr branch to subroutine procedure bsrf branch to subroutine procedure jmp unconditional branch jsr branch to subroutine procedure rts return from subroutine procedure 2. cpu rev.5.00 sep. 27, 2007 page 35 of 716 rej09b0398-0500 classification types operation code function no. of instructions 11 clrt t bit clear 31 system control clrmac mac register clear ldc load to control register lds load to system register nop no operation rte return from exception processing sett t bit set sleep shift into power-down mode stc storing control register data sts storing system register data trapa trap exception handling total: 62 142 table 2.11 shows the format used in tables 2.12 to 2.17, which list instruction codes, operation, and execution states in order by classification. 2. cpu rev.5.00 sep. 27, 2007 page 36 of 716 rej09b0398-0500 table 2.11 instruction code format item format explanation instruction op.sz src,dest op: operation code sz: size (b: byte, w: word, or l: longword) src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement * 1 instruction code msb ? lsb mmmm: source register nnnn: destination register 0000: r0 0001: r1 . . . 1111: r15 iiii: immediate data dddd: displacement operation , direction of transfer (xx) memory operand m/q/t flag bits in the sr & logical and of each bit | logical or of each bit ^ exclusive or of each bit ~ logical not of each bit < 2. cpu rev.5.00 sep. 27, 2007 page 37 of 716 rej09b0398-0500 table 2.12 data transfer instructions instruction instruction code operation exec. cycles t bit mov #imm,rn 1110nnnniiiiiiii #imm sign extension rn 1 ? mov.w @(disp,pc),rn 1001nnnndddddddd (disp 2 + pc) sign extension rn 1 ? mov.l @(disp,pc),rn 1101nnnndddddddd (disp 4 + pc) rn 1 ? mov rm,rn 0110nnnnmmmm0011 rm rn 1 ? mov.b rm,@rn 0010nnnnmmmm0000 rm (rn) 1 ? mov.w rm,@rn 0010nnnnmmmm0001 rm (rn) 1 ? mov.l rm,@rn 0010nnnnmmmm0010 rm (rn) 1 ? mov.b @rm,rn 0110nnnnmmmm0000 (rm) sign extension rn 1 ? mov.w @rm,rn 0110nnnnmmmm0001 (rm) sign extension rn 1 ? mov.l @rm,rn 0110nnnnmmmm0010 (rm) rn 1 ? mov.b rm,@?rn 0010nnnnmmmm0100 rn ? 1 rn, rm (rn) 1 ? mov.w rm,@?rn 0010nnnnmmmm0101 rn ? 2 rn, rm (rn) 1 ? mov.l rm,@?rn 0010nnnnmmmm0110 rn ? 4 rn, rm (rn) 1 ? mov.b @rm+,rn 0110nnnnmmmm0100 (rm) sign extension rn,rm + 1 rm 1 ? mov.w @rm+,rn 0110nnnnmmmm0101 (rm) sign extension rn,rm + 2 rm 1 ? mov.l @rm+,rn 0110nnnnmmmm0110 (rm) rn,rm + 4 rm 1 ? mov.b r0,@(disp,rn) 10000000nnnndddd r0 (disp + rn) 1 ? mov.w r0,@(disp,rn) 10000001nnnndddd r0 (disp 2 + rn) 1 ? mov.l rm,@(disp,rn) 0001nnnnmmmmdddd rm (disp 4 + rn) 1 ? mov.b @(disp,rm),r0 10000100mmmmdddd (disp + rm) sign extension r0 1 ? mov.w @(disp,rm),r0 10000101mmmmdddd (disp 2 + rm) sign extension r0 1 ? mov.l @(disp,rm),rn 0101nnnnmmmmdddd (disp 4 + rm) rn 1 ? mov.b rm,@(r0,rn) 0000nnnnmmmm0100 rm (r0 + rn) 1 ? 2. cpu rev.5.00 sep. 27, 2007 page 38 of 716 rej09b0398-0500 instruction instruction code operation exec. cycles t bit mov.w rm,@(r0,rn) 0000nnnnmmmm0101 rm (r0 + rn) 1 ? mov.l rm,@(r0,rn) 0000nnnnmmmm0110 rm (r0 + rn) 1 ? mov.b @(r0,rm),rn 0000nnnnmmmm1100 (r0 + rm) sign extension rn 1 ? mov.w @(r0,rm),rn 0000nnnnmmmm1101 (r0 + rm) sign extension rn 1 ? mov.l @(r0,rm),rn 0000nnnnmmmm1110 (r0 + rm) rn 1 ? mov.b r0,@(disp,gbr) 11000000dddddddd r0 (disp + gbr) 1 ? mov.w r0,@(disp,gbr) 11000001dddddddd r0 (disp 2 + gbr) 1 ? mov.l r0,@(disp,gbr) 11000010dddddddd r0 (disp 4 + gbr) 1 ? mov.b @(disp,gbr),r0 11000100dddddddd (disp + gbr) sign extension r0 1 ? mov.w @(disp,gbr),r0 11000101dddddddd (disp 2 + gbr) sign extension r0 1 ? mov.l @(disp,gbr),r0 11000110dddddddd (disp 4 + gbr) r0 1 ? mova @(disp,pc),r0 11000111dddddddd disp 4 + pc r0 1 ? movt rn 0000nnnn00101001 t rn 1 ? swap.b rm,rn 0110nnnnmmmm1000 rm swap the bottom two bytes rn 1 ? swap.w rm,rn 0110nnnnmmmm1001 rm swap two consecutive words rn 1 ? xtrct rm,rn 0010nnnnmmmm1101 rm: middle 32 bits of rn rn 1 ? 2. cpu rev.5.00 sep. 27, 2007 page 39 of 716 rej09b0398-0500 table 2.13 arithmetic operation instructions instruction instruction code operation exec. cycles t bit add rm,rn 0011nnnnmmmm1100 rn + rm rn 1 ? add #imm,rn 0111nnnniiiiiiii rn + imm rn 1 ? addc rm,rn 0011nnnnmmmm1110 rn + rm + t rn, carry t 1 carry addv rm,rn 0011nnnnmmmm1111 rn + rm rn, overflow t 1 overflow cmp/eq #imm,r0 10001000iiiiiiii if r0 = imm, 1 t 1 comparison result cmp/eq rm,rn 0011nnnnmmmm0000 if rn = rm, 1 t 1 comparison result cmp/hs rm,rn 0011nnnnmmmm0010 if rn rm with unsigned data, 1 t 1 comparison result cmp/ge rm,rn 0011nnnnmmmm0011 if rn rm with signed data, 1 t 1 comparison result cmp/hi rm,rn 0011nnnnmmmm0110 if rn > rm with unsigned data, 1 t 1 comparison result cmp/gt rm,rn 0011nnnnmmmm0111 if rn > rm with signed data, 1 t 1 comparison result cmp/pl rn 0100nnnn00010101 if rn > 0, 1 t 1 comparison result cmp/pz rn 0100nnnn00010001 if rn 0, 1 t 1 comparison result cmp/str rm,rn 0010nnnnmmmm1100 if rn and rm have an equivalent byte, 1 t 1 comparison result div1 rm,rn 0011nnnnmmmm0100 single-step division (rn/rm) 1 calculation result div0s rm,rn 0010nnnnmmmm0111 msb of rn q, msb of rm m, m ^ q t 1 calculation result div0u 0000000000011001 0 m/q/t 1 0 2. cpu rev.5.00 sep. 27, 2007 page 40 of 716 rej09b0398-0500 instruction instruction code operation exec. cycles t bit dmuls.l rm,rn 0011nnnnmmmm1101 signed operation of rn rm mach, macl 32 32 64 bit 2 to 4 * ? dmulu.l rm,rn 0011nnnnmmmm0101 unsigned operation of rn rm mach, macl 32 32 64 bit 2 to 4 * ? dt rn 0100nnnn00010000 rn ? 1 rn, when rn is 0, 1 t. when rn is nonzero, 0 t 1 comparison result exts.b rm,rn 0110nnnnmmmm1110 a byte in rm is sign- extended rn 1 ? exts.w rm,rn 0110nnnnmmmm1111 a word in rm is sign- extended rn 1 ? extu.b rm,rn 0110nnnnmmmm1100 a byte in rm is zero- extended rn 1 ? extu.w rm,rn 0110nnnnmmmm1101 a word in rm is zero- extended rn 1 ? mac.l @rm+,@rn+ 0000nnnnmmmm1111 signed operation of (rn) (rm) + mac mac 32 32 64 bit 3/ (2 to 4) * ? mac.w @rm+,@rn+ 0100nnnnmmmm1111 signed operation of (rn) (rm) + mac mac 16 16 + 64 64 bit 3/(2) * ? mul.l rm,rn 0000nnnnmmmm0111 rn rm macl, 32 32 32 bit 2 to 4 * ? muls.w rm,rn 0010nnnnmmmm1111 signed operation of rn rm mac 16 16 32 bit 1 to 3 * ? mulu.w rm,rn 0010nnnnmmmm1110 unsigned operation of rn rm mac 16 16 32 bit 1 to 3 * ? neg rm,rn 0110nnnnmmmm1011 0 ? rm rn 1 ? negc rm,rn 0110nnnnmmmm1010 0 ? rm ? t rn, borrow t 1 borrow 2. cpu rev.5.00 sep. 27, 2007 page 41 of 716 rej09b0398-0500 instruction instruction code operation exec. cycles t bit sub rm,rn 0011nnnnmmmm1000 rn ? rm rn 1 ? subc rm,rn 0011nnnnmmmm1010 rn ? rm ? t rn, borrow t 1 borrow subv rm,rn 0011nnnnmmmm1011 rn ? rm rn, underflow t 1 overflow note: * the normal minimum number of execution cycles. (the number in parentheses is the number of cycles when there is contention with following instructions.) 2. cpu rev.5.00 sep. 27, 2007 page 42 of 716 rej09b0398-0500 table 2.14 logic opera tion instructions instruction instruction code operation exec. cycles t bit and rm,rn 0010nnnnmmmm1001 rn & rm rn 1 ? and #imm,r0 11001001iiiiiiii r0 & imm r0 1 ? and.b #imm,@(r0,gbr) 11001101iiiiiiii (r0 + gbr) & imm (r0 + gbr) 3 ? not rm,rn 0110nnnnmmmm0111 rm rn 1 ? or rm,rn 0010nnnnmmmm1011 rn | rm rn 1 ? or #imm,r0 11001011iiiiiiii r0 | imm r0 1 ? or.b #imm,@(r0,gbr) 11001111iiiiiiii (r0 + gbr) | imm (r0 + gbr) 3 ? tas.b @rn * 0100nnnn00011011 if (rn) is 0, 1 t; 1 msb of (rn) * 4 test result tst rm,rn 0010nnnnmmmm1000 rn & rm; if the result is 0, 1 t 1 test result tst #imm,r0 11001000iiiiiiii r0 & imm; if the result is 0, 1 t 1 test result tst.b #imm,@(r0,gbr) 11001100iiiiiiii (r0 + gbr) & imm; if the result is 0, 1 t 3 test result xor rm,rn 0010nnnnmmmm1010 rn ^ rm rn 1 ? xor #imm,r0 11001010iiiiiiii r0 ^ imm r0 1 ? xor.b #imm,@(r0,gbr) 11001110iiiiiiii (r0 + gbr) ^ imm (r0 + gbr) 3 ? note: * the on-chip dmac bus cycles are not inserted between the read and write cycles of tas instruction execution. 2. cpu rev.5.00 sep. 27, 2007 page 43 of 716 rej09b0398-0500 table 2.15 shift instructions instruction instruction code operation exec. cycles t bit rotl rn 0100nnnn00000100 t rn msb 1 msb rotr rn 0100nnnn00000101 lsb rn t 1 lsb rotcl rn 0100nnnn00100100 t rn t 1 msb rotcr rn 0100nnnn00100101 t rn t 1 lsb shal rn 0100nnnn00100000 t rn 0 1 msb shar rn 0100nnnn00100001 msb rn t 1 lsb shll rn 0100nnnn00000000 t rn 0 1 msb shlr rn 0100nnnn00000001 0 rn t 1 lsb shll2 rn 0100nnnn00001000 rn<<2 rn 1 ? shlr2 rn 0100nnnn00001001 rn>>2 rn 1 ? shll8 rn 0100nnnn00011000 rn<<8 rn 1 ? shlr8 rn 0100nnnn00011001 rn>>8 rn 1 ? shll16 rn 0100nnnn00101000 rn<<16 rn 1 ? shlr16 rn 0100nnnn00101001 rn>>16 rn 1 ? 2. cpu rev.5.00 sep. 27, 2007 page 44 of 716 rej09b0398-0500 table 2.16 branch instructions instruction instruction code operation exec. cycles t bit bf label 10001011dddddddd if t = 0, disp 2 + pc pc; if t = 1, nop 3/1 * ? bf/s label 10001111dddddddd delayed branch, if t = 0, disp 2 + pc pc; if t = 1, nop 3/1 * ? bt label 10001001dddddddd if t = 1, disp 2 + pc pc; if t = 0, nop 3/1 * ? bt/s label 10001101dddddddd delayed branch, if t = 1, disp 2 + pc pc; if t = 0, nop 2/1 * ? bra label 1010dddddddddddd delayed branch, disp 2 + pc pc 2 ? braf rm 0000mmmm00100011 delayed branch, rm + pc pc 2 ? bsr label 1011dddddddddddd delayed branch, pc pr, disp 2 + pc pc 2 ? bsrf rm 0000mmmm00000011 delayed branch, pc pr, rm + pc pc 2 ? jmp @rm 0100mmmm00101011 delayed branch, rm pc 2 ? jsr @rm 0100mmmm00001011 delayed branch, pc pr, rm pc 2 ? rts 0000000000001011 delayed branch, pr pc 2 ? note: one state when it does not branch. 2. cpu rev.5.00 sep. 27, 2007 page 45 of 716 rej09b0398-0500 table 2.17 system co ntrol instructions instruction instruction code operation exec. cycles t bit clrt 0000000000001000 0 t 1 0 clrmac 0000000000101000 0 mach, macl 1 ? ldc rm,sr 0100mmmm00001110 rm sr 1 lsb ldc rm,gbr 0100mmmm00011110 rm gbr 1 ? ldc rm,vbr 0100mmmm00101110 rm vbr 1 ? ldc.l @rm+,sr 0100mmmm00000111 (rm) sr, rm + 4 rm 3 lsb ldc.l @rm+,gbr 0100mmmm00010111 (rm) gbr, rm + 4 rm 3 ? ldc.l @rm+,vbr 0100mmmm00100111 (rm) vbr, rm + 4 rm 3 ? lds rm,mach 0100mmmm00001010 rm mach 1 ? lds rm,macl 0100mmmm00011010 rm macl 1 ? lds rm,pr 0100mmmm00101010 rm pr 1 ? lds.l @rm+,mach 0100mmmm00000110 (rm) mach, rm + 4 rm 1 ? lds.l @rm+,macl 0100mmmm00010110 (rm) macl, rm + 4 rm 1 ? lds.l @rm+,pr 0100mmmm00100110 (rm) pr, rm + 4 rm 1 ? nop 0000000000001001 no operation 1 ? rte 0000000000101011 delayed branch, stack area pc/sr 4 ? sett 0000000000011000 1 t 1 1 sleep 0000000000011011 sleep 3 * ? stc sr,rn 0000nnnn00000010 sr rn 1 ? stc gbr,rn 0000nnnn00010010 gbr rn 1 ? stc vbr,rn 0000nnnn00100010 vbr rn 1 ? stc.l sr,@?rn 0100nnnn00000011 rn ? 4 rn, sr (rn) 2 ? stc.l gbr,@?rn 0100nnnn00010011 rn ? 4 rn, gbr (rn) 2 ? stc.l vbr,@?rn 0100nnnn00100011 rn ? 4 rn, br (rn) 2 ? sts mach,rn 0000nnnn00001010 mach rn 1 ? sts macl,rn 0000nnnn00011010 macl rn 1 ? sts pr,rn 0000nnnn00101010 pr rn 1 ? 2. cpu rev.5.00 sep. 27, 2007 page 46 of 716 rej09b0398-0500 instruction instruction code operation exec. cycles t bit sts.l mach,@?rn 0100nnnn00000010 rn ? 4 rn, mach (rn) 1 ? sts.l macl,@?rn 0100nnnn00010010 rn ? 4 rn, macl (rn) 1 ? sts.l pr,@?rn 0100nnnn00100010 rn ? 4 rn, pr (rn) 1 ? trapa #imm 11000011iiiiiiii pc/sr stack area, (imm) pc 8 ? note: the number of execution cycles before the chip enters sleep mode: the execution cycles shown in the table are minimums. the actual number of cycles may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) and the register used by the next instruction are the same. 2.5 processing states 2.5.1 state transitions the cpu has four processing states: reset, exception processing, program execution and power- down. figure 2.6 shows the transitions between the states. 2. cpu rev.5.00 sep. 27, 2007 page 47 of 716 rej09b0398-0500 power-on reset state sleep mode standby mode program execution state exception processing state res = 1 when an interrupt source or dma address error occurs nmi interrupt source occurs exception processing ends exception processing source occurs sby bit cleared for sleep instruction sby bit set for sleep instruction from any state when res = 0 reset states power-down state figure 2.6 transitions between processing states 2. cpu rev.5.00 sep. 27, 2007 page 48 of 716 rej09b0398-0500 reset state: the cpu resets in the reset state. when the res pin level goes low, a power-on reset results. exception processing state: the exception processing state is a transient state th at occurs when exception processing sources such as resets or interrupts alter the cpu's processing state flow. for a reset, the initial values of the program counter (pc) (execution start address) and stack pointer (sp) are fetched from the exception pro cessing vector table and stored; the cpu then branches to the execution start address and execution of the program begins. for an interrupt, the stack pointer (sp) is acce ssed and the program counter (pc) and status register (sr) are saved to the stack area. the exception service routine st art address is fetched from the exception processing vector table; the cpu then branches to that address and the program starts executing, thereby enteri ng the program execution state. program execution state: in the program execution state, the cpu sequentially executes the program. power-down state: in the power-down state, the cpu operation halts and power consumption declines. the sleep instruction places the cpu in the power-down state. this state has two modes: sleep mode and standby mode. 2.5.2 power-down state besides the ordinary program execution states, the cpu also has a power-down state in which cpu operation halts, lowering power consumption. there are two power-down state modes: sleep mode and standby mode. sleep mode: when standby bit sby (in the standby control register sbycr) is cleared to 0 and a sleep instruction executed, the cpu moves from program execution state to sleep mode. in the sleep mode, the cpu halts and the c ontents of its internal registers and the data in on-chip cache (or on-chip ram) is maintained. the on-chip peripheral modules other than the cpu do not halt in the sleep mode. to return from sleep mode, use a power-on reset, any interrupt, or a dma address error; the cpu returns to the ordinary program execution state through the exception processing state. standby mode: to enter the standby mode, set the standby bit sby (in the standby control register sbycr) to 1 and execute a sleep instruction. in standby mode, all cpu, on-chip peripheral module, and oscillator functions are halte d. however, when entering standby mode, the dma master enable bit of the dmac should be set to 0. if multiplication-re lated instructions are being executed at the time of entry into standby mode, the values of mach and macl will become undefined. 2. cpu rev.5.00 sep. 27, 2007 page 49 of 716 rej09b0398-0500 to return from standby mode, use a power-on reset or an nmi interrupt. for resets, the cpu returns to ordinary program execution state throu gh the exception processing state when placed in a reset state for the duration of the oscillator stabilization time. for nmi interrupts, the cpu returns to ordinary program execution state through the exception processing state after the oscillator stabilization time has elapsed. in this mode, power consumption drops markedly, since the oscillator stops (table 2.18). table 2.18 power-down state state mode transition conditions clock cpu on-chip peripheral modules cpu registers on-chip cache or on-chip ram i/o port pins canceling sleep execute sleep instruction with sby bit cleared to 0 in sbycr run halt run held held held ? interrupt ? dma address error ? power-on reset stand- by execute sleep instruction with sby bit set to 1 in sbycr halt halt halt and initialize * held held held or hi-z (select- able) ? nmi interrupt ? power-on reset note: * differs depending on the peripheral module and pin. 2. cpu rev.5.00 sep. 27, 2007 page 50 of 716 rej09b0398-0500 3. operating modes rev.5.00 sep. 27, 2007 page 51 of 716 rej09b0398-0500 section 3 operating modes 3.1 operating modes, types, and selection this lsi has five operating modes and three clock modes, determined by the setting of the mode pins (md3 to md0). do not change the mode pin settings during lsi operation (while power is on). table 3.1 indicates the setting method for the operating mode. table 3.1 operating mode setting pin setting mode no. fwp md3 * 1 md2 * 1 md1 md0 mode name on-chip rom cs0 area 0 1 x x 0 0 mcu mode 0 not active 8-bit space 1 1 x x 0 1 mcu mode 1 not active 16-bit space 2 * 4 1 x x 1 0 mcu mode 2 active 8/16-bit space * 2 3 * 4 1 x x 1 1 single chip mode active ? 0 x x 0 0 boot mode * 3 active 8/16-bit space * 2 0 x x 0 1 ? 0 x x 1 0 active 8/16-bit space * 2 0 x x 1 1 user programming mode * 3 ? 1 1 1 0 1 flash programmer mode * 3 active ? notes: 1. md2 and md3 pins select the clock mode in modes 0 to 3 (table 3.2). 2. set by bcr1 of bsc. 3. only f-ztat. 4. only sh7016, sh7017. table 3.2 indicates the setting method for the clock mode. table 3.2 clock mode setting md3 md2 clock mode 0 0 pll on 1 0 1 pll on 2 1 0 pll on 4 1 1 reserved 3. operating modes rev.5.00 sep. 27, 2007 page 52 of 716 rej09b0398-0500 3.2 explanation of operating modes table 3.3 describes the operating modes. table 3.3 operating modes mode description (mcu) mode 0 cs0 area becomes an external memory space with 8-bit bus width. (mcu) mode 1 cs0 area becomes an external memory space with 16-bit bus width. (mcu) mode 2 the on-chip rom becomes effective. the bus width for the on-chip rom space is 32 bit. mode 3 (single chip mode) any port can be used, but external addresses can not be employed. clock mode the input waveform frequency can be used as is, doubled or quadrupled as an internal clock in modes 0 to 3. 3.3 pin configuration table 3.4 describes the function of each operating mode related pin. table 3.4 operating mode pin function pin name input/output function xtal input connects to a crystal oscillator extal input connects to a crystal oscillator, or used for external clock input pin pllcap input connects to a capacitor for pll circuit operation md0 input designates operating mode through the level applied to this pin md1 input designates operating mode through the level applied to this pin md2 input designates clock mode through the level applied to this pin md3 input designates clock mode through the level applied to this pin 4. clock pulse generator (cpg) rev.5.00 sep. 27, 2007 page 53 of 716 rej09b0398-0500 section 4 clock pulse generator (cpg) 4.1 overview this lsi has an on-chip clock pulse generator (cpg) that generates the system clock ( ), as well as the internal clock ( /2 to /8192). the cpg consists of an oscillator, a pll, and a prescaler. 4.1.1 block diagram a block diagram of the clock pulse generator is shown in figure 4.1. pllcap ck extal xtal md2 md3 oscillator pll circuit clock mode control circuitry prescaler within the lsi /2 to /8192 figure 4.1 block diagram of the clock pulse generator 4. clock pulse generator (cpg) rev.5.00 sep. 27, 2007 page 54 of 716 rej09b0398-0500 4.2 oscillator clock pulses can be supplied from a connected crystal resonator or an external clock. 4.2.1 connecting a crystal oscillator circuit configuration: a crystal oscillator can be connected as shown in figure 4.2. use the damping resistance (rd) listed in table 4.1. use a 4 to 10 mhz crystal oscillator (consult your dealer concerning the compatibility of the crystal oscillator and the lsi). xtal extal c l1 c l2 r d 4 to 10 mhz c l1 = c l2 = 18 to 22 pf (recommended value) figure 4.2 connection of the crystal oscillator (example) table 4.1 damping resistance values (recommended values) frequency (mhz) parameter 4 8 10 rd ( ) 500 200 0 crystal oscillator: figure 4.3 shows an equivalent circuit of the crystal oscillator. use a crystal oscillator with the characteristics listed in table 4.2. co extal c l lrs xtal figure 4.3 crystal oscillator equivalent circuit 4. clock pulse generator (cpg) rev.5.00 sep. 27, 2007 page 55 of 716 rej09b0398-0500 table 4.2 crystal oscillator parameters frequency (mhz) parameter 4 8 10 rs max ( ) 120 80 60 co max (pf) 7 7 7 notes on board design: when connecting a crystal oscillator, observe the following precautions: ? to prevent induction from interfering with correct oscillation, do not route any signal lines near the oscillator circuitry. ? when designing the board, place the crystal oscillator and its load capacitors as close as possible to the xtal and extal pins. figures 4.4 and 4.5 show the precautions regarding oscillator block board settings. crossin g of si g nal lines prohibited c l1 xtal extal c l2 figure 4.4 cautions for oscillator circuit system board design 4. clock pulse generator (cpg) rev.5.00 sep. 27, 2007 page 56 of 716 rej09b0398-0500 external circuitry such as that shown in figure 4.5 is recommended around the pll. pllcap pllv cc pllv ss v cc v ss r1: 3 k c1: 470 pf rp: 200 cpb: 0.1 f * cb: 0.1 f * note: * cb and cpb are laminated ceramic capacitors (recommended values) figure 4.5 cautions for use of pll oscillator circuit place oscillation stabilization capacitor c1 and resistor r1 near the pll cap pin, and ensure that these lines do not cross any other signal lines. supply the c1 ground from pll v ss . also, separate pll v cc and pll v ss , and the other v cc and v ss pins, from the board power supply source, and be sure to insert bypass capacitors cpb and cb close to the pins. 4.2.2 external clock input method figure 4.6 shows an example of an external clock input connection. in this case, make the external clock high level to stop it when in standby mode. during operation, make the external input clock frequency 4 to 10 mhz. when leaving the xtal pin open, make sure the parasitic capacitance is less than 10 pf. even when inputting an external clock, be sure to delay until after the oscillation stabilization time (upon power-on) or after release from standby, in order to ensure the pll stabilization time. 4. clock pulse generator (cpg) rev.5.00 sep. 27, 2007 page 57 of 716 rej09b0398-0500 extal xtal open external clock input 4 to 10 mhz figure 4.6 example of external clock connection 4.3 prescaler the prescaler divides the system clock ( ) to generate an internal clock ( /2 to /8192) for supply to peripheral modules. 4. clock pulse generator (cpg) rev.5.00 sep. 27, 2007 page 58 of 716 rej09b0398-0500 5. exception processing rev.5.00 sep. 27, 2007 page 59 of 716 rej09b0398-0500 section 5 exception processing 5.1 overview 5.1.1 types of exception processing and priority exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority shown in table 5.1. when several exception processing sources occur at once, they are processed according to the priority shown. table 5.1 types of exception pr ocessing and priority order exception source priority reset power-on reset high cpu address error address error dmac address error interrupt nmi user break irq on-chip peripheral modules: ? direct memory access controller (dmac) ? multifunction timer/pulse unit (mtu) ? serial communication interface (sci) ? a/d converter (a/d) ? compare match timer (cmt) ? watchdog timer (wdt) ? bus state controller (bsc) instructions trap instruction (trapa instruction) general illegal instructions (undefined code) illegal slot instructions (undefined code placed directly after a delay branch instruction * 1 or instructions that rewrite the pc * 2 ) low notes: 1. delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf. 2. instructions that rewrite the pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf. 5. exception processing rev.5.00 sep. 27, 2007 page 60 of 716 rej09b0398-0500 5.1.2 exception processing operations the exception processing sources are detected and begin processing according to the timing shown in table 5.2. table 5.2 timing of exception source detect ion and the start of exception processing exception source timing of source detection and start of processing power-on reset starts when the res pin changes from low to high. address error detected when instruction is decoded and starts when the previous executing instruction finishes executing. interrupts detected when instruction is decoded and starts when the previous executing instruction finishes executing. instructions trap instruction starts from the execution of a trapa instruction. general illegal instructions starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). illegal slot instructions starts from the decoding of undefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the pc. when exception processing starts , the cpu operates as follows: 1. exception processing triggered by reset: the initial values of the program counter (pc) and stack pointer (sp) are fetched from the exception processing vector table (pc and sp are respectively the h'00000000 and h'00000004 addresses). see section 5.1.3, exception processing vector table, for more information. 0 is then written to the vector base register (vbr) and 1111 is written to the interrupt mask bits (i3 to i0) of the status register (sr). the program begins running from the pc address fetched from the exception processing vector table. 2. exception processing triggered by address errors, interrupts and instructions: sr and pc are saved to the stack indicated by r15. for interrupt exception processing, the interrupt priority level is written to the sr's interrupt mask bits (i3 to i0). for address error and instruction exception processing, the i3 to i0 b its are not affected. the start address is then fetched from the exception processing vector table and the program begins running from that address. 5. exception processing rev.5.00 sep. 27, 2007 page 61 of 716 rej09b0398-0500 5.1.3 exception processing vector table before exception processing begins running, the exception processing vector table must be set in memory. the exception processing vector table st ores the start addresses of exception service routines. (the reset exception processing table holds the initial values of pc and sp.) all exception sources are given different vector numbers and vector table address offsets, from which the vector table addresses are calculated. du ring exception processing, the start addresses of the exception service routines are fetched from the exception processing vector table, which indicated by this vector table address. table 5.3 shows the vector numbers and vector table address offsets. table 5.4 shows how vector table addresses are calculated. table 5.3 exception processing vector table exception sources vector numbers vector table address offset power-on reset pc 0 h'00000000 to h'00000003 sp 1 h'00000004 to h'00000007 (reserved by system) 2 h'00000008 to h'0000000b (reserved by system) 3 h'0000000c to h'0000000f general illegal instruction 4 h'00000010 to h'00000013 (reserved by system) 5 h'00000014 to h'00000017 slot illegal instruction 6 h'00000018 to h'0000001b (reserved by system) 7 h'0000001c to h'0000001f (reserved by system) 8 h'00000020 to h'00000023 cpu address error 9 h'00000024 to h'00000027 dmac address error 10 h'00000028 to h'0000002b interrupts nmi 11 h'0000002c to h'0000002f user break 12 h'00000030 to h'00000033 (reserved by system) 13 : 31 h'00000034 to h'00000037 : h'0000007c to h'0000007f trap instruction (user vector) 32 : 63 h'00000080 to h'00000083 : h'000000fc to h'000000ff 5. exception processing rev.5.00 sep. 27, 2007 page 62 of 716 rej09b0398-0500 exception sources vector numbers vector table address offset interrupts irq0 64 h'00000100 to h'00000103 irq1 65 h'00000104 to h'00000107 irq2 66 h'00000108 to h'0000010b irq3 67 h'0000010c to h'0000010f (reserved by system) 68 h'00000110 to h'00000113 (reserved by system) 69 h'00000114 to h'00000117 interrupt irq6 70 h'00000118 to h'0000011b irq7 71 h'0000011c to h'0000011f on-chip peripheral module * 72 : 255 h'00000120 to h'00000124 : h'000003fc to h'000003ff note: * the vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in section 6, interrupt controller, and table 6.3, interrupt exception processing vectors and priorities. table 5.4 calculating exception pr ocessing vector table addresses exception source vector table address calculation resets vector table address = (vector table address offset) = (vector number) 4 address errors, interrupts, instructions vector table address = vbr + (vector table address offset) = vbr + (vector number) 4 notes: 1. vbr: vector base register 2. vector table address offset: see table 5.3. 3. vector number: see table 5.3. 5. exception processing rev.5.00 sep. 27, 2007 page 63 of 716 rej09b0398-0500 5.2 resets 5.2.1 power-on reset when the res pin is driven low, the lsi does a power-on reset. to reliably reset the lsi, the res pin should be kept at low for at least the duration of the os cillation settling time when applying power or when in standby mode (when the clock circuit is halted) or at least 20 t cyc (when the clock circuit is running). during power-on reset, cpu internal status and all registers of on-chip peripheral modules are initialized. see appendix b, pin status, for the status of individual pins during the power-on reset status. in the power-on reset status, power-on reset exception processing starts when the res pin is first driven low for a set period of time and then returned to high. the cpu will then operate as follows: 1. the initial value (execution start address) of the program counter (pc) is fetched from the exception processing vector table. 2. the initial value of the stack pointer (sp) is fetched from the exception processing vector table. 3. the vector base register (vbr) is cleared to h'00000000 and the interrupt mask bits (i3 to i0) of the status register (sr) are set to h'f (1111). 4. the values fetched from the exception processing vector table are set in the program counter (pc) and sp and the program begins executing. be certain to always perform power-on reset processing when turning the system power on. 5. exception processing rev.5.00 sep. 27, 2007 page 64 of 716 rej09b0398-0500 5.3 address errors 5.3.1 address error sources address errors occur when instructions are fetched or data read or written, as shown in table 5.5. table 5.5 bus cycles and address errors bus cycle type bus master bus cycle description address errors cpu instruction fetched from even address none (normal) instruction fetch instruction fetched from odd address address error occurs instruction fetched from other than on-chip peripheral module space * none (normal) instruction fetched from on-chip peripheral module space * address error occurs instruction fetched from external memory space when in single chip mode address error occurs word data accessed from even address none (normal) data read/write cpu or dmac word data accessed from odd address address error occurs longword data accessed from a longword boundary none (normal) longword data accessed from other than a long-word boundary address error occurs byte or word data accessed in on-chip peripheral module space * none (normal) longword data accessed in 16-bit on-chip peripheral module space * none (normal) longword data accessed in 8-bit on-chip peripheral module space * address error occurs external memory space accessed in single-chip mode address error occurs note: * see section 8, bus state controller. 5. exception processing rev.5.00 sep. 27, 2007 page 65 of 716 rej09b0398-0500 5.3.2 address error exception processing when an address error occurs, the bus cycle in which the address error occurred ends. when the executing instruction then finishes, address error exception processing starts up. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the start address of the instruction to be executed after the last executed instruction. 3. the exception service routine start address is fetched from the exception processing vector table that corresponds to the address error that occurred and the program starts executing from that address. the jump that occurs is not a delayed branch. 5.4 interrupts 5.4.1 interrupt sources table 5.6 shows the sources that start up interrupt exception processing. these are divided into nmi, irq and on-chip peripheral modules. table 5.6 interrupt sources type request source number of sources nmi nmi pin (external input) 1 irq irq0 to irq3 , irq6 , irq7 (external input) 6 on-chip peripheral module direct memory access controller (dmac) 2 multifunction timer pulse unit (mtu) 13 serial communication interface (sci) 8 a/d converter 1 compare match timer (cmt) 2 watchdog timer (wdt) 1 bus state controller (bsc) 1 each interrupt source is allocated a different vector number and vector table offset. see section 6, interrupt controller, and table 6.3, interrupt exception processing vectors and priorities, for more information on vector numbers and vector table address offsets. 5. exception processing rev.5.00 sep. 27, 2007 page 66 of 716 rej09b0398-0500 5.4.2 interrupt priority level the interrupt priority order is predetermined. when multiple interrupts occur simultaneously (overlap), the interrupt controller (intc) determines their relative priorities and starts up processing according to the results. the priority order of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. the nmi interrupt has priority 16 and cannot be masked, so it is always accepted. irq interrupts and on-chip periphera l module interrupt priority levels can be set freely using the intc's interrupt priority level setting registers a through h (ipra to iprh) as shown in table 5.7. the priority levels that can be set are 0 to 15. level 16 cannot be set. see section 6.3.1, interrupt priority registers a to h (ipra to iprh), for more information on ipra to iprh. table 5.7 interrupt priority order type priority level comment nmi 16 fixed priority level. cannot be masked. irq 0 to 15 set with interrupt priority level setting registers a through h (ipra to iprh). on-chip peripheral module 0 to 15 set with interrupt priority level setting registers a through h (ipra to iprh). 5.4.3 interrupt exception processing when an interrupt occurs, its priority level is ascertained by the interrupt controller (intc). nmi is always accepted, but other inte rrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (i3 to i0) of the status register (sr). when an interrupt is accepted, ex ception processing begins. in inte rrupt exception processing, the cpu saves sr and the program counter (pc) to th e stack. the priority leve l value of the accepted interrupt is written to sr bits i3 to i0. for nmi, however, the priority level is 16, but the value set in i3 to i0 is h'f (level 15). next, the start a ddress of the exception service routine is fetched from the exception processing vector table for the accept ed interrupt, that addr ess is jumped to and execution begins. see section 6.4, interrupt operation, for more information on the interrupt exception processing. 5. exception processing rev.5.00 sep. 27, 2007 page 67 of 716 rej09b0398-0500 5.5 exceptions triggered by instructions 5.5.1 types of exceptions tr iggered by instructions exception processing can be triggered by trap instructions, general illegal instructions, and illegal slot instructions, as shown in table 5.8. table 5.8 types of exceptions triggered by instructions type source instruction comment trap instructions trapa ? illegal slot instructions undefined code placed immediately after a delayed branch instruction (delay slot) and instructions that rewrite the pc delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf instructions that rewrite the pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf general illegal instructions undefined code anywhere besides in a delay slot ? 5.5.2 trap instructions when a trapa instruction is executed, trap instruction exception processing starts up. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the start address of the instruction to be executed after the trapa instruction. 3. the exception service routine start address is fetched from the exception processing vector table that corresponds to the vector number speci fied in the trapa instruction. that address is jumped to and the program st arts executing. the jump that o ccurs is not a delayed branch. 5. exception processing rev.5.00 sep. 27, 2007 page 68 of 716 rej09b0398-0500 5.5.3 illegal slot instructions an instruction placed immedi ately after a delayed branch instructi on is said to be placed in a delay slot. when the instruction plac ed in the delay slot is undefined code, illegal slot exception processing starts up when that undefined code is decoded. illegal slot exception processing also starts up when an instruction that rewrites the program counter (pc) is placed in a delay slot. the processing starts when the instruction is decoded. the cpu handles an illegal slot instruction as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the jump address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the pc. 3. the exception service routine start address is fetched from the exception processing vector table that corresponds to the exception that o ccurred. that address is jumped to and the program starts executing. the jump that occurs is not a delayed branch. 5.5.4 general illegal instructions when undefined code placed anywhe re other than immediately afte r a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts up. the cpu handles general illegal instructions the same as illegal slot instructions. unlike processing of illegal slot instructions, however, the program counter value stored is the start address of the undefined code. 5. exception processing rev.5.00 sep. 27, 2007 page 69 of 716 rej09b0398-0500 5.6 when exception sour ces are not accepted when an address error or interrupt is generated after a delayed branch instruction or interrupt- disabled instruction, it is sometimes not accepte d immediately but stored instead, as shown in table 5.9. when this happens, it will be accepted when an instruction that can accept the exception is decoded. table 5.9 generation of ex ception sources immediatel y after a delayed branch instruction or interrupt-disabled instruction exception source point of occurrence address error interrupt immediately after a delayed branch instruction * 1 not accepted not accepted immediately after an interrupt-disabled instruction * 2 accepted not accepted notes: 1. delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf 2. interrupt-disabled instructions: ldc, ldc.l, stc, stc.l, lds, lds.l, sts, sts.l 5.6.1 immediately after a delayed branch instruction when an instruction placed immediat ely after a delayed branch instru ction (delay slot) is decoded, neither address errors nor interrupts are accepte d. the delayed branch instruction and the instruction located imme diately after it (delay slot) are al ways executed consecutively, so no exception processing occurs during this period. 5.6.2 immediately after an interrupt-disabled instruction when an instruction immediately following an interrupt-disabled instruction is decoded, interrupts are not accepted. address errors are accepted. 5. exception processing rev.5.00 sep. 27, 2007 page 70 of 716 rej09b0398-0500 5.7 stack status after excep tion processing ends the status of the stack after exception processing ends is as shown in table 5.10. table 5.10 types of stack status after exception processing ends types stack status address error 32 bits 32 bits sr address of instruction after executed instruction sp trap instruction 32 bits 32 bits sr address of instruction after trapa instruction sp general illegal instruction 32 bits 32 bits sr start address of illegal instruction sp interrupt 32 bits 32 bits sr address of instruction after executed instruction sp illegal slot instruction 32 bits 32 bits sr jump destination address of delay branch instruction sp 5. exception processing rev.5.00 sep. 27, 2007 page 71 of 716 rej09b0398-0500 5.8 usage notes 5.8.1 value of stack pointer (sp) the value of the stack pointer must always be a multiple of four. if it is not, an address error will occur when the stack is accesse d during exception processing. 5.8.2 value of vector base register (vbr) the value of the vector base register must always be a multiple of four. if it is not, an address error will occur when the stack is accessed during exception processing. 5.8.3 address errors caused by stacking of address error exception processing when the stack pointer is not a multiple of four, an address error will occur during stacking of the exception processing (interrupts, etc.) and address error exception processing will start up as soon as the first exception processing is ended. address errors will then also occur in the stacking for this address error exception processing. to ensure that address error exception processing does not go into an endless loop, no address errors are accep ted at that point. this allows program control to be shifted to the address error exception service routine and enables error processing. when an address error occurs during exception pr ocessing stacking, the stacking bus cycle (write) is executed. during stacking of the status register (sr) and program counter (pc), the sp is ? 4 for both, so the value of sp will not be a multiple of four after the stacking either. the address value output during stacking is the sp value, so the address where the error o ccurred is itself output. this means the write data stacked will be undefined. 5. exception processing rev.5.00 sep. 27, 2007 page 72 of 716 rej09b0398-0500 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 73 of 716 rej09b0398-0500 section 6 interrupt controller (intc) 6.1 overview the interrupt controller (intc) ascertains the priority of interrupt sources and controls interrupt requests to the cpu. the intc has registers for se tting the priority of each interrupt which can be used by the user to order the priorities in which the interrupt requests are processed. 6.1.1 features the intc has the following features: ? 16 levels of interrupt priority: by setting the eight interrupt-priority level registers, the priorities of irq interrupts and on-chip peripheral module interrupts can be set in 16 levels for different request sources. ? nmi noise canceler function: nmi input level bits indicate the nmi pin status. by reading these bits with the interrupt exception service routine, the pin status can be confirmed, enabling it to be used as a noise canceler. 6.1.2 block diagram figure 6.1 is a block diagram of the intc. 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 74 of 716 rej09b0398-0500 cpu sr interrupt request com- parator cpu priority rankin g jud g - ment input control (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) isr icr ipr ipra to iprh module bus bus interface internal bus i3 i2 i1 i0 intc nmi irq0 irq1 irq2 irq3 irq6 irq7 dmac mtu cmt sci a/d wdt (interrupt request) bsc le g end: dmac: mtu: cmt: sci: a/d: wdt: bsc: direct memory access controller multifunction timer pulse unit compare match timer serial communication interface a/d converter watchdo g timer bus state controller (dram icr: isr: ipra to iprh: sr: interrupt control re g ister irq ststus re g ister interrupt priority re g isters a to h status re g ister figure 6.1 intc block diagram 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 75 of 716 rej09b0398-0500 6.1.3 pin configuration table 6.1 shows the intc pin configuration. table 6.1 pin configuration name abbreviation i/o function non-maskable interrupt input pin nmi i input of non-maskable interrupt request signal interrupt request input pins irq0 to irq3 , irq6 , irq7 i input of maskable interrupt request signals 6.1.4 register configuration the intc has the 10 registers shown in table 6.2. these registers set the priority of the interrupts and control external interrupt input signal detection. table 6.2 register configuration name abbr. r/w initial value address access sizes interrupt priority register a ipra r/w h'0000 h'ffff8348 8, 16, 32 interrupt priority register b iprb r/w h'0000 h'ffff834a 8, 16, 32 interrupt priority register c iprc r/w h'0000 h'ffff834c 8, 16, 32 interrupt priority register d iprd r/w h'0000 h'ffff834e 8, 16, 32 interrupt priority register e ipre r/w h'0000 h'ffff8350 8, 16, 32 interrupt priority register f iprf r/w h'0000 h'ffff8352 8, 16, 32 interrupt priority register g iprg r/w h'0000 h'ffff8354 8, 16, 32 interrupt priority register h iprh r/w h'0000 h'ffff8356 8, 16, 32 interrupt control register icr r/w * 1 h'ffff8358 8, 16, 32 irq status register isr r(w) * 2 h'0000 h'ffff835a 8, 16, 32 notes: 1. the value when the nmi pin is high is h'8000; when the nmi pin is low, it is h'0000. 2. only 0 can be written, in order to clear flags. 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 76 of 716 rej09b0398-0500 6.2 interrupt sources there are three types of interrupt sources: nmi, irq, and on-chip peripheral modules. each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). giving an interrupt a priority level of 0 masks it. 6.2.1 nmi interrupts the nmi interrupt has priority 16 and is always accepted. input at the nmi pin is detected by edge. use the nmi edge select bit (nmie) in the in terrupt control register (icr) to select either the rising or falling edge. nmi interrupt exception processing sets the interrupt mask level bits (i3 to i0) in the status register (sr) to level 15. 6.2.2 irq interrupts irq interrupts are requested by input from pins irq0 to irq3 , irq6 , irq7 . set the irq sense select bits (irq0s to irq3s, irq6s, irq7s) of the interrupt control register (icr) to select low level detection or falling edge det ection for each pin. the priority level can be set from 0 to 15 for each pin using the interrupt priority registers a and b (ipra and iprb). when irq interrupts are set to low level detection, an interrupt request signal is sent to the intc during the period the irq pin is low level. interrupt request signals are not sent to the intc when the irq pin becomes high level. interrupt request levels can be confirmed by reading the irq flags (irq0f to irq3f, irq6f, irq7f) of the irq status register (isr). when irq interrupts are set to falling edge detection, interrupt request signals are sent to the intc upon detecting a change on the irq pin from high to low level. irq interrupt request detection results are maintained until the interrupt request is accepted. confirmation that irq interrupt requests have been detected is possible by reading the irq flags (irq0f to irq3f, irq6f, irq7f) of the irq status register (isr), and by writing a 0 after reading a 1, irq interrupt request detection results can be withdrawn. in irq interrupt exception processing, the interrupt mask bits (i3 to i0) of the status register (sr) are set to the priority level va lue of the accepted irq interrupt. 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 77 of 716 rej09b0398-0500 6.2.3 on-chip peripheral module interrupts on-chip peripheral module interrupts are interrupt s generated by the following on-chip peripheral modules: ? direct memory access controller (dmac) ? multifunction timer pulse unit (mtu) ? compare match timer (cmt) ? serial communicati on interface (sci) ? a/d converter (a/d) ? watchdog timer (wdt) ? bus state controller (bsc) a different interrupt vector is assigned to each interrupt source, so the exception service routine does not have to decide which interrupt has occurred. priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers c to h (iprc to iprh). on-chip peripheral module interrupt exception processing sets the interrupt mask level bits (i3 to i0) in the status register (sr) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.2.4 interrupt exception v ectors and priority rankings table 6.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. each interrupt source is allocated a different vector number and vector table address offset. vector table addresses are calculated from vector numb ers and address offsets. in interrupt exception processing, the exception service r outine start address is fetched fr om the vector table indicated by the vector table address. see table 5.4, calculating exception processing vector table addresses. irq interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers a to h (ipra to iprh). the ranking of interrupt sources for iprc to iprh, however, must be the order listed under priority order within ipr setting range in table 6.3 and cannot be changed. a power-on reset assigns priority level 0 to irq interrupts and on-chip peripheral module interrupts. if the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, their priority order is the default priority order indicated at the right in table 6.3. 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 78 of 716 rej09b0398-0500 table 6.3 interrupt exception pro cessing vectors and priorities interrupt vector interrupt source vector no. vector table address offset interrupt priority (initial value) corresponding ipr (bits) priority within ipr setting range default priority nmi 11 h'0000002c to h'0000002f 16 ? ? high irq0 64 h'00000100 to h'00000103 0 to 15 (0) ipra (15 to 12) ? irq1 65 h'00000104 to h'00000107 0 to 15 (0) ipra (11 to 8) ? irq2 66 h'00000108 to h'0000010b 0 to 15 (0) ipra (7 to 4) ? irq3 67 h'0000010c to h'0000010f 0 to 15 (0) ipra (3 to 0) ? irq6 70 h'00000118 to h'0000011b 0 to 15 (0) iprb (7 to 4) ? irq7 71 h'0000011c to h'0000011f 0 to 15 (0) iprb (3 to 0) ? dmac0 dei0 72 h'00000120 to h'00000123 0 to 15 (0) iprc (15 to 12) ? dmac1 dei1 76 h'00000130 to h'00000133 0 to 15 (0) iprc (11 to 8) ? mtu0 tgi0a 88 h'00000160 to h'00000163 0 to 15 (0) iprd (15 to 12) high tgi0b 89 h'00000164 to h'00000167 0 to 15 (0) tgi0c 90 h'00000168 to h'0000016b 0 to 15 (0) tgi0d 91 h'0000016c to h'0000016f 0 to 15 (0) low tci0v 92 h'00000170 to h'00000173 0 to 15 (0) iprd (11 to 8) ? low 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 79 of 716 rej09b0398-0500 interrupt vector interrupt source vector no. vector table address offset interrupt priority (initial value) corresponding ipr (bits) priority within ipr setting range default priority mtu1 tgi1a 96 h'00000180 to h'00000183 0 to 15 (0) iprd (7 to 4) high high tgi1b 97 h'00000184 to h'00000187 0 to 15 (0) low tci1v 100 h'00000190 to h'00000193 0 to 15 (0) iprd (3 to 0) high tci1u 101 h'00000194 to h'00000197 0 to 15 (0) low mtu2 tgi2a 104 h'000001a0 to h'000001a3 0 to 15 (0) ipre (15 to 12) high tgi2b 105 h'000001a4 to h'000001a7 0 to 15 (0) low tci2v 108 h'000001b0 to h'000001b3 0 to 15 (0) ipre (11 to 8) high tci2u 109 h'000001b4 to h'000001b7 0 to 15 (0) low sci0 eri0 128 h'00000200 to h'00000203 0 to 15 (0) iprf (7 to 4) high rxi0 129 h'00000204 to h'00000207 0 to 15 (0) txi0 130 h'00000208 to h'0000020b 0 to 15 (0) tei0 131 h'0000020c to h'0000020f 0 to 15 (0) low sci1 eri1 132 h'00000210 to h'00000213 0 to 15 (0) iprf (3 to 0) high rxi1 133 h'00000214 to h'00000217 0 to 15 (0) txi1 134 h'00000218 to h'0000021b 0 to 15 (0) tei1 135 h'0000021c to h'0000021f 0 to 15 (0) low low 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 80 of 716 rej09b0398-0500 interrupt vector interrupt source vector no. vector table address offset interrupt priority (initial value) corresponding ipr (bits) priority within ipr setting range default priority a/d * adi 136 h'00000220 to h'00000223 0 to 15 (0) iprg (15 to 12) ? high 138 h'00000228 to h'0000022b cmt0 cmi0 144 h'00000240 to h'00000243 0 to 15 (0) iprg (7 to 4) ? cmt1 cmi1 148 h'00000250 to h'00000253 0 to 15 (0) iprg (3 to 0) ? wdt iti 152 h'00000260 to h'00000263 0 to 15 (0) iprh (15 to 12) high bsc cmi 153 h'00000264 to h'00000267 0 to 15 (0) low low note: * vector no. 136 = sh7014 only 138 = sh7016, sh7017 only 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 81 of 716 rej09b0398-0500 6.3 description of registers 6.3.1 interrupt priority registers a to h (ipra to iprh) interrupt priority registers a to h (ipra to iprh) are 16-bit readable/writable registers that set priority levels from 0 to 15 for irq interrupts and on-chip peripheral module interrupts. correspondence between interrupt request sources and each of the ipra to iprh bits is shown in table 6.4. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 6.4 interrupt request sources and ipra to iprh bits register 15 to 12 11 to 8 7 to 4 3 to 0 interrupt priority register a irq0 irq1 irq2 irq3 interrupt priority register b reserved reserved irq6 irq7 interrupt priority register c dmac0 dmac1 reserved reserved interrupt priority register d mtu0 mtu0 mtu1 mtu1 interrupt priority register e mtu2 mtu2 reserved reserved interrupt priority register f reserved reserved sci0 sci1 interrupt priority register g a/d reserved cmt0 cmt1 interrupt priority register h wdt, bsc reserved reserved reserved 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 82 of 716 rej09b0398-0500 as indicated in table 6.4, four irq pins or groups of 4 on-chip peripheral modules are allocated to each register. each of the corresponding interrupt priority ranks are established by setting a value from h'0 (0000) to h'f (1111) in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. interrupt priority rank becomes level 0 (lowest) by setting h'0, and level 15 (highest) by setting h'f. if multiple on-chip peripheral modules are assigned to wdt and bsc, those multiple modules are set to the same priority rank. ipra to iprh are initialized to h'0000 by a pow er-on reset. they are not initialized in standby mode. 6.3.2 interrupt control register (icr) the icr is a 16-bit register that sets the input signal detection mode of the external interrupt input pin nmi and irq0 to irq3 , irq6 , irq7 and indicates the input signal level to the nmi pin. it is initialized by power-on reset, but is not initialized by standby mode. bit: 15 14 13 12 11 10 9 8 nmil ? ? ? ? ? ? nmie initial value: * 0 0 0 0 0 0 0 r/w: r r r r r r r r/w bit: 7 6 5 4 3 2 1 0 irq0s irq1s irq2s irq3s ? ? irq6s irq7s initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r r/w r/w note: * when nmi input is high: 1; when nmi input is low: 0 bit 15 ? nmi input level (nmil): sets the level of the signal input at the nmi pin. this bit can be read to determine the nmi pin level. this bit cannot be modified. bit 15 nmil description 0 nmi input level is low 1 nmi input level is high bits 14 to 9, 3, 2 ? reserved: these bits always read as 0. th e write value should always be 0. 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 83 of 716 rej09b0398-0500 bit 8 ? nmi edge select (nmie) bit 8 nmie description 0 interrupt request is detected on falling edge of nmi input (initial value) 1 interrupt request is detected on rising edge of nmi input bits 7 to 4, 1, 0 ? irq0 to irq3, irq6, irq7 sense select (irq0s to irq3s, irq6s, irq7s): these bits set the irq0 to irq3, irq6, irq7 interrupt request detection mode. bits 7 to 4, 1, 0 irq0s to irq3s, irq6s, irq7s description 0 interrupt request is detected on low level of irq input (initial value) 1 interrupt request is detected on falling edge of irq input 6.3.3 irq status register (isr) the isr is a 16-bit register that indicates the interrupt request status of the external interrupt input pins irq0 to irq3 , irq6 , irq7 . when irq interrupts are set to edge detection, held interrupt requests can be withdrawn by writing a 0 to irqnf after reading an irqnf = 1. a power-on reset initializes isr but the standby mode does not. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 irq0f irq1f irq2f irq3f ? ? irq6f irq7f initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r r/w r/w bits 15 to 8, 3, 2 ? reserved: these bits always read as 0. th e write value should always be 0. 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 84 of 716 rej09b0398-0500 bits 7 to 4, 1, 0 ? irq0 to irq3, irq6, irq7 flags (irq0f to irq3f, irq6f, irq7f): these bits display the irq0 to irq3, irq6, irq7 interrupt request status. bits 7 to 4, 1, 0 irq0f to irq3f, irq6f, irq7f detection setting description 0 level detection no irqn interrupt request exists. clear conditions: when irqn input is high level edge detection no irqn interrupt request was detected. (initial value) clear conditions: 1. when a 0 is written after reading irqnf = 1 status 2. when irqn interrupt exception processing has been executed 1 level detection an irqn interrupt request exists. set conditions: when irqn input is low level edge detection an irqn interrupt request was detected. set conditions: when a falling edge occurs at an irqn input irq pin edge detection selection cpu interrupt request (irqn interrupt acceptance/irqnf = 0 write after irqnf = 1 read) s r resirqn q irqns (0: level, 1: edge) isr.irqnf level detection figure 6.2 external interrupt process 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 85 of 716 rej09b0398-0500 6.4 interrupt operation 6.4.1 interrupt sequence the sequence of interrupt operations is explained below. figure 6.3 is a flowchart of the operations. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest priority interrupt in the interrupt requests sent, following the priority levels set in interrupt priority level setting registers a to h (ipra to iprh). lower-priority interrupts are ignored. they are held pending until interrupt requests designated as edge-detect type are accepted. for irq interrupts, however, withdrawal is possible by accessing the irq status register (is r). see section 6.2.2, irq interrupts, for details. interrupts held pending due to edge detec tion are cleared by a power-on reset. if two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its ipr setting range (as indicated in table 6.3) is selected. 3. the interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (i3 to i0) in the cpu's status register (sr). if the request priority level is equal to or less than the level set in i3 to i0, the request is ignored. if the request priority level is higher than the level in bits i3 to i0, the interrupt contro ller accepts the interrupt and sends an interrupt request signal to the cpu. 4. the cpu detects the interrupt request sent from the interrupt controller when it decodes the next instruction to be executed. instead of executing the decoded instruction, the cpu starts interrupt exception processing (figure 6.4). 5. sr and pc are saved onto the stack. 6. the priority level of the accepted interrupt is copi ed to the interrupt mask level bits (i3 to i0) in the status register (sr). 7. the cpu reads the start address of the ex ception service routine fro m the exception vector table for the accepted interrupt, ju mps to that address, and star ts executing the program there. this jump is not a delay branch. 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 86 of 716 rej09b0398-0500 no yes nmi? no yes level 15 interrupt? no yes i3 to i0 level 14? no yes level 14 interrupt? no yes yes i3 to i0 level 13? no yes level 1 interrupt? no yes i3 to i0 = level 0? no pro g ram execution state save sr to stack save pc to stack branches to exception service routine le g end: i3 to i0: interrupt mask bits of status re g ister interrupt? copy accept-interrupt level to i3 to i0 reads exception vector table figure 6.3 interrupt sequence flowchart 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 87 of 716 rej09b0398-0500 6.4.2 stack after interrupt exception processing figure 6.4 shows the stack after interrupt exception processing. 32 bits 32 bits pc * 1 sr address 4n?8 4n?4 4n sp * 2 notes: 1. 2. pc: start address of the next instruction (return destination instruction) after the executing instruction always be certain that sp is a multiple of 4 figure 6.4 stack after interrupt exception processing 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 88 of 716 rej09b0398-0500 6.5 interrupt response time table 6.5 indicates the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. figure 6.5 shows the pipeline when an irq interrupt is accepted. table 6.5 interrupt response time number of states item nmi, peripheral module irq notes dmac active judgment 0 or 1 1 1 state required for interrupt signals for which dmac activation is possible compare identified inter- rupt priority with sr mask level 2 3 wait for completion of sequence currently being executed by cpu x ( 0) the longest sequence is for interrupt or address-error exception processing (x = 4 + m1 + m2 + m3 + m4). if an interrupt-masking instruction follows, however, the time may be even longer. time from start of interrupt exception processing until fetch of first instruction of exception service routine starts 5 + m1 + m2 + m3 performs the pc and sr saves and vector address fetch. total: 7 + m1 + m2 + m3 9 + m1 + m2 + m3 minimum: 10 12 0.35 to 0.42 s at 28.7 mhz interrupt response time maximum: 12 + 2 (m1 + m2 + m3) + m4 13 + 2 (m1 + m2 + m3) + m4 0.67 to 0.70 s at 28.7 mhz * note: when m1 = m2 = m3 = m4 = 1 m1 to m4 are the number of states needed for the following memory accesses. m1: sr save (longword write) m2: pc save (longword write) m3: vector address read (longword read) m4: fetch first instruction of interrupt service routine 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 89 of 716 rej09b0398-0500 fde mee mme ee fd f 3 1 3 interrupt acceptance irq m1 m2 1 m3 1 5 + m1 + m2 + m3 instruction (instruction replaced by interrupt exception processing) overrun fetch interrupt service routine start instruction legend: f: d: e: m: instruction fetch (instruction fetched from memory where program is stored). instruction decoding (fetched instruction is decoded). instruction execution (data operation and address calculation is performed according to the results of decoding). memory access (data in memory is accessed). figure 6.5 pipelin e when an irq interrupt is accepted 6. interrupt controller (intc) rev.5.00 sep. 27, 2007 page 90 of 716 rej09b0398-0500 6.6 data transfer with interrupt request signals the following data transfers can be done using interrupt request signals: ? activate dmac only, without generating cpu interrupt among interrupt sources, those designated as dmac activating sources are masked and not input to the intc. the masking condition is listed below: mask condition = dme (de0 source selection 0 + de1 ) figure 6.6 shows a control block diagram. interrupt source interrupt source flag clear (by dmac) interrupt source (those not designated as dmac activating sources) cpu interrupt request dmac figure 6.6 interrupt control block diagram 6.6.1 handling dmac activating sou rces but not cpu interrupt sources 1. select the dmac as a source and set the dme bit to 1. cpu interrupt sources and dtc activating sources are masked regardless of the interrupt priority level register settings or dtc register settings. 2. activating sources are applied to the dmac when interrupts occur. 3. the dmac clears activating sources at the time of data transfer. 6.6.2 treating cpu interrupt sou rces but not dmac activating sources 1. either do not select the dmac as a source, or clear the dme bit to 0. 2. when interrupts occur, interrupt requests are sent to the cpu. 3. the cpu clears the interrupt source and performs the necessary processing in the interrupt processing routine. 7. cache memory (cac) rev.5.00 sep. 27, 2007 page 91 of 716 rej09b0398-0500 section 7 cache memory (cac) 7.1 overview the lsi has an on-chip cache memory (cac: cache) with 1 kbyte of cache data and a 256-entry cache tag. the cache data and cache tag space can be used as on-chip ram space when the cache is not being used. 7.1.1 features the cac has the following featur es. the cache tag and cache data configuration is shown in figure 7.1. ? 1-kbyte capacity ? external memory (cs space and dram space) in struction code and pc relative data caching ? 256 entry cache tag (tag address 15 bits) ? 4-byte line length ? direct map replacement algorithm ? valid flag (1 bit) included for purges cache ta g 256 entries data (32 bits) ta g address (15 bits) cache data data bus hit si g nal cpu address ta g address entry address offset valid bit (1 bit) cmp 15 8 2 figure 7.1 cache tag and cache data configuration 7. cache memory (cac) rev.5.00 sep. 27, 2007 page 92 of 716 rej09b0398-0500 7.1.2 block diagram figure 7.2 shows a block diagram of the cache. le g end: ccr: cache control re g ister cache ta g cache controller cache data internal address bus internal data bus bus state controller external bus interface ccr cache figure 7.2 cache block diagram 7. cache memory (cac) rev.5.00 sep. 27, 2007 page 93 of 716 rej09b0398-0500 7.1.3 register configuration the cache has one register, which can be used to control the enabling or disabling of each cache space. the register configuration is shown in table 7.1. table 7.1 register configuration name abbreviation r/w initial value address access size (bits) cache control register ccr r/w h'0000 * h'ffff8740 8, 16, 32 note: * bits 15 to 5 are undefined. 7. cache memory (cac) rev.5.00 sep. 27, 2007 page 94 of 716 rej09b0398-0500 7.2 register explanation 7.2.1 cache control register (ccr) the cache control register (ccr) selects the cache enable/disab le of each space. the ccr is a 16-bit readable/writable register. it is initialized to h'0000 by power on resets, but is not initialized by standby mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: * * * * * * * * r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ce dram ce cs3 ce cs2 ce cs1 ce cs0 initial value: * * * 0 0 0 0 0 r/w: r r r r/w r/w r/w r/w r/w note: * bits 15 to 5 are undefined. bits 15 to 5 ? reserved: reading these bits gives undefined values. the write value should always be 0. bit 4 ? dram space cache enable (cedram): selects whether to use dram space as a cache object (enable) or to exclude it (disable ). a 0 disables, and a 1 enables such use. bit 4 cedram description 0 dram space cache disabled (initial value) 1 dram space cache enabled 7. cache memory (cac) rev.5.00 sep. 27, 2007 page 95 of 716 rej09b0398-0500 bit 3 ? cs3 space cache enable (cecs3): selects whether to use cs3 space as a cache object (enable) or to exclude it (disable). a 0 disables, and a 1 enables such use. bit 3 cecs3 description 0 cs3 space cache disabled (initial value) 1 cs3 space cache enabled bit 2 ? cs2 space cache enable (cecs2): selects whether to use cs2 space as a cache object (enable) or to exclude it (disable). a 0 disables, and a 1 enables such use. bit 2 cecs2 description 0 cs2 space cache disabled (initial value) 1 cs2 space cache enabled bit 1 ? cs1 space cache enable (cecs1): selects whether to use cs1 space as a cache object (enable) or to exclude it (disable). a 0 disables, and a 1 enables such use. bit 1 cecs1 description 0 cs1 space cache disabled (initial value) 1 cs1 space cache enabled bit 0 ? cs0 space cache enable (cecs0): selects whether to use cs0 space as a cache object (enable) or to exclude it (disable). a 0 disables, and a 1 enables such use. bit 0 cecs0 description 0 cs0 space cache disabled (initial value) 1 cs0 space cache enabled 7. cache memory (cac) rev.5.00 sep. 27, 2007 page 96 of 716 rej09b0398-0500 7.3 address array and data array there is a special cache space for controlling the cache. this space is divided into an address array and a data array, where addresses (tag address, including valid bit) and data (4-byte line length) for cache control are recorded. the special cache space is s hown in table 7.2. it can be used as on-chip ram space when the cache is not being used. table 7.2 special cache space space classification address size bus width address array h'fffff000 to h'fffff3ff 1 kbyte 32 bits data array h'fffff400 to h'fffff7ff 1 kbyte 32 bits 7.3.1 cache address array read/write space the cache address array has a compulsory read/write (figure 7.3). address upper 22 bits of the address array space address (22 bits) ? (2 bits) entry address (8 bits) 31 0 21 10 9 data ? (6 bits) ? (10 bits) ta g address (15 bits) valid bit (1 bit) 31 0 10 9 26 25 24 figure 7.3 cach e address array address array read: designates entry address and reads out the corresponding tag address value/valid bit value. address array write: designates entry address and writes the designated tag address value/valid bit value. 7. cache memory (cac) rev.5.00 sep. 27, 2007 page 97 of 716 rej09b0398-0500 7.3.2 cache data array read/write space the cache data array has a compul sory read/write (figure 7.4). address upper 22 bits of the data array space address (22 bits) ? (2 bits) entry address (8 bits) 31 0 21 10 9 data data (32 bits) 31 0 figure 7.4 cache data array data array read: designates entry address and reads out the corresponding line of data. data array write: designates entry address and writes designated data to the corresponding line. 7. cache memory (cac) rev.5.00 sep. 27, 2007 page 98 of 716 rej09b0398-0500 7.4 usage notes 7.4.1 cache initialization always initialize the cache before enabling it. specifically, use an address array write to write 0 to all valid bits for all entries (256 times), that is,thos e in the address range h' fffff000 to h'fffff3fff. 7.4.2 forced access to address array and data array while the cache is enabled, it is not possible to write to the addr ess array or data array via the cpu, or dmac, and a read will return an undefi ned value. the cache must be disabled before making a forced access to the address array or data array. 7.4.3 cache miss penalty and cache fill timing when a cache miss occurs, a single idle cycle is generated as a penalty immediately before the cache fill (access from external memory in the event of a cache miss), as shown in figure 7.5. however, in the case of consecutiv e cache misses, idle cycles are not generated for the second and subsequent cache misses, as shown in figure 7.6. as the timing for a cache fill from normal space, th e cs assert period immediately before the end of the bus cycle (or the last bus cycle when two or four bus cycles are generated, such as in a word access to 8-bit space) is extended by an additional cycle, as shown in figures 7.5 and 7.6. similarly, as the timing for a cache fill from dram space, the ras assert period immediately before the end of the bus cycle is extended by an additional cycle as shown in figure 7.7. in ras down mode, the next bus cycle is delayed by one cycle as shown in figure 7.8. 7. cache memory (cac) rev.5.00 sep. 27, 2007 page 99 of 716 rej09b0398-0500 mis-hit ck internal address address csn rd data idle cycle idle cycle idle cycle cs assert extension figure 7.5 cache fill timing in case of non-consecutive cache miss from normal space (no wait, no cs assert extension) miss-hit ck internal address address csn rd data cs assert additional extension figure 7.6 cache fill timing in case of consecutive cache misses from normal space (no wait, cs assert extension) 7. cache memory (cac) rev.5.00 sep. 27, 2007 page 100 of 716 rej09b0398-0500 idle cycle idle cycle idle cycle ck internal address address ras casx data row column miss-hit ras assert extension figure 7.7 cache fill timing in case of non-consecutive cache miss from dram space (normal mode, tpc = 0, rcd = 0, no wait) miss-hit row column cs space wait column ras assert extension ck internal address address ras casx data dram access cs space access dram access miss-hit figure 7.8 cache fill timing in case of consecutive cache misses from dram space (ras down mode, tpc = 0, rcd = 0, no wait) 7.4.4 cache hit after cache miss the first cache hit after a cache miss is regarded as a cache miss, and a cache fill without idle cycle generation is performed. the next hit operates as a cache hit. 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 101 of 716 rej09b0398-0500 section 8 bus state controller (bsc) 8.1 overview the bus state controller (bsc) divides up the addr ess spaces and outputs cont rol for various types of memory. this enables memories like dram, sr am, and rom to be linked directly to the lsi without external circuitry. 8.1.1 features the bsc has the following features: ? address space is divided into five spaces ? a maximum linear 2 mbytes for cs0 address space in modes with on-chip rom enabled, and a maximum linear 4 mbytes in modes with on-chip rom disabled ? a maximum linear 4 mbytes for each of address spaces cs1, cs2, and cs3 ? a maximum linear 16 mbytes for dram dedicated space ? bus width can be selected fo r each space (8 or 16 bits) ? wait states can be inserted by software for each space ? wait states can be inserted via the wait pin in external memory space accesses ? outputs control signals for each space accord ing to the type of memory connected ? on-chip rom/ram interfaces ? on-chip ram access of 32 bits in 1 state ? on-chip rom access of 32 bits in 1 state ? direct interface to dram ? multiplexes row/column addresses according to dram capacity ? supports high-speed page mode and ras down mode ? access control for each type of memory, peripheral lsi ? address/data multiplex function ? refresh ? supports cas-before-ras refresh (auto-refresh) and self-refresh ? refresh counter can be used as an interval timer ? interrupt request generated upon compare match (cmi interrupt request signal) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 102 of 716 rej09b0398-0500 8.1.2 block diagram figure 8.1 shows the bsc block diagram. wcr1 wcr2 bcr1 bcr2 dcr rd cmi interrupt request wait rtcsr rtcnt rtcor internal bus interrupt controller bus interface area control unit comparator module bus cs0 to cs3 ah rdwr wait control unit memory control unit peripheral bus wrh , wrl cash , casl ras bsc legend: wcr1: wcr2: bcr1: bcr2: wait control register 1 wait control register 2 bus control register 1 bus control register 2 dcr: rtcnt: rtcor: rtcsr: dram area control register refresh timer counter refresh timer constant register refresh timer control/status register figure 8.1 bsc block diagram 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 103 of 716 rej09b0398-0500 8.1.3 pin configuration table 8.1 shows the bus state controller pin configuration. table 8.1 pin configuration signal i/o description a21 to a0 o address output (a21 to a18 become input ports in power-on reset) d15 to d0 i/o 16-bit data bus. d15-d0 are address output and data i/o during address/data multiplex i/o. cs0 to cs3 o chip select rd o strobe that indicates the read cycle for ordinary space/multiplex i/o. also output during dram access. wrh o strobe that indicates a write cycle to the higher byte (d15 to d8) for ordinary space/multiplex i/o. also output during dram access. wrl o strobe that indicates a write cycle to the lower byte (d7 to d0) for ordinary space/multiplex i/o. also output during dram access. rdwr o strobe indicating a write cycle to dram (used for dram space) ras o ras signal for dram (used for dram space) cash o cas signal when accessing the higher byte (d15 to d8) of dram (used for dram space) casl o cas signal when accessing the lower byte (d7 to d0) of dram (used for dram space) ah o signal to hold the address during address/data multiplex wait i wait state request signal 8.1.4 register configuration the bsc has eight registers. these registers ar e used to control wait states, bus width, and interfaces with memories like dram, sram, and ro m, as well as refresh control. the register configurations are listed in table 8.2. all registers are 16 bits. do not access dram space before completing the memory interface settings. all bsc registers are all initialized by a pow er-on reset. values are maintained in standby mode. 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 104 of 716 rej09b0398-0500 table 8.2 register configuration name abbr. r/w initial value address access size bus control register 1 bcr1 r/w h'200f h'ffff8620 8, 16, 32 bus control register 2 bcr2 r/w h'ffff h'ffff8622 8, 16, 32 wait state control register 1 wcr1 r/w h'ffff h'ffff8624 8, 16, 32 wait state control register 2 wcr2 r/w h'000f h'ffff8626 8, 16, 32 dram area control register dcr r/w h'0000 h'ffff862a 8, 16, 32 refresh timer control/status register rtcsr r/w h'0000 h'ffff862c 8, 16, 32 refresh timer counter rtcnt r/w h'0000 h'ffff862e 8, 16, 32 refresh time constant register rtcor r/w h'0000 h'ffff8630 8, 16, 32 8.1.5 address map figure 8.2 shows the address format used by the sh7014. a31 to a24 a23, a22 a21 output address: output from the address pins space selection: not output externally; used to select the type of space on-chip rom space or cs space when 00000000 (h'00) dram space when 00000001 (h'01) reserved (do not access) when 00000010 to 11111110 (h'02 to h'fe) on-chip peripheral module space or on-chip ram space when 11111111 (h'ff) cs space selection: decoded, outputs cs0 to cs3 when a31 to a24 = 00000000 a0 figure 8.2 address format this lsi uses 32-bit addresses: ? a31 to a24 are used to select the type of space and are not output externally. ? bits a23 and a22 are decoded and output as chip select signals ( cs0 to cs3 ) for the corresponding areas when bits a31 to a24 are 00000000. ? a21 to a0 are output externally. 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 105 of 716 rej09b0398-0500 table 8.3 shows an address map. table 8.3 address map ? in on-chip rom enabled mode* 5 address space memory size bus width h'00000000 to h'0001ffff * 4 on-chip rom on-chip rom 128 kbytes 32 bits h'00020000 to h'001fffff reserved h'00200000 to h'003fffff cs0 space ordinary space 2 mbytes 8/16 bits * 1 h'00400000 to h'007fffff cs1 space ordinary space 4 mbytes 8/16 bits * 1 h'00800000 to h'00bfffff cs2 space ordinary space 4 mbytes 8/16 bits * 1 h'00c00000 to h'00ffffff cs3 space ordinary space or multiplex i/o space 4 mbytes 8/16 bits * 2 h'01000000 to h'01ffffff dram space dram 16 mbytes 8/16 bits * 1 h'02000000 to h'ffff7fff reserved h'ffff8000 to h'ffff87ff on-chip peripheral module on-chip peripheral module 2 kbytes 8/16 bits h'ffff8800 to h'ffffefff reserved h'fffff000 to h'ffffffff * 6 on-chip ram on-chip ram 4 kbytes 32 bits 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 106 of 716 rej09b0398-0500 ? in on-chip rom disabled mode address space memory size bus width h'00000000 to h'003fffff cs0 space ordinary space 4 mbytes 8/16 bits * 3 h'00400000 to h'007fffff cs1 space ordinary space 4 mbytes 8/16 bits * 1 h'00800000 to h'00bfffff cs2 space ordinary space 4 mbytes 8/16 bits * 1 h'00c00000 to h'00ffffff cs3 space ordinary space or multiplex i/o space 4 mbytes 8/16 bits * 2 h'01000000 to h'01ffffff dram space dram 16 mbytes 8/16 bits * 1 h'02000000 to h'ffff7fff reserved h'ffff8000 to h'ffff87ff on-chip peripheral module on-chip peripheral module 2 kbytes 8/16 bits h'ffff8800 to h'ffffefff reserved h'fffff000 to h'ffffffff * 6 on-chip ram on-chip ram 4 kbytes 32 bits notes: do not access reserved space, as operation cannot be guaranteed in this case. in single-chip mode, space other than on-chip rom, on-chip ram, and on-chip peripheral module space cannot be used. 1. selected by on-chip register settings. 2. ordinary space: selected by on-chip register settings. multiplex i/o space: 8/16 bits selected by the a14 bit. 3. 8/16 bits selected by the mode pin. 4. in the 64-kbyte on-chip rom version (sh7016), on-chip rom addresses are h'00000000 to h'0000ffff, and addresses h'00010000 to h'0001ffff are reserved space. 5. sh7016/17 only. 6. in the 3-kbyte on-chip ram versio ns (sh7014/16), on-chip ram addresses are h'fffff000 to h'fffffbff, and addresses h'fffffc00 to h'ffffffff are reserved space. 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 107 of 716 rej09b0398-0500 8.2 description of registers 8.2.1 bus control register 1 (bcr1) bcr1 is a 16-bit read/write register that selects multiplex i/o, and specifies the bus size of the cs spaces. write bits 8 to 0 of bcr1 during the initialization stage after a power-on reset, and do not change the values thereafter. in on-ch ip rom ineffective mode, do not access any cs space other than cs0 until after completion of register initialization. bcr1 is initialized by power-on resets to h'200f , but is not initialized by software standbys. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ioe initial value: 0 0 1 0 0 0 0 0 r/w: r r r r r r r r/w bit: 7 6 5 4 3 2 1 0 ? ? ? ? a3sz a2sz a1sz a0sz initial value: 0 0 0 0 1 1 1 1 r/w: r r r r r/w r/w r/w r/w note: do not write 1 to bits 4 to 7, as operation is not guaranteed in this case. bits 15, 14, 12 to 9 ? reserved: these bits always read as 0. the write value should always be 0. bit 13 ? reserved: this bit always read as 1. the write value should always be 1. bit 8 ? multiplex i/o enable (ioe): selects the use of cs3 space as ordinary space or address/data multiplex i/o space. a 0 selects ordi nary space and a 1 selects address/data multiplex i/o space. when address/data multiplex i/o space is selected, the address and data are multiplexed and output from the data bus. when cs3 space is an address/data multiplex i/o space, bus size is decided by the a14 bit (a14 = 0: 8 bit, a14 = 1: 16 bit). bit 8 ioe description 0 cs3 space is ordinary space (initial value) 1 cs3 space is address/data multiplex i/o space 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 108 of 716 rej09b0398-0500 bits 7 to 4 ? reserved: these bits read 0 after a reset. the write value should always be 0. operation is not guaranteed if the write value is 1. bit 3 ? cs3 space size specifi cation (a3sz): specifies the cs3 space bus size. this is effective only when cs3 space is ordinary space. when cs3 space is an address/data multiplex i/o space, bus size is decided by the a14 bit. bit 3 a3sz description 0 byte (8-bit) size (initial value) 1 word (16-bit) size bit 2 ? cs2 space size specifi cation (a2sz): specifies the cs2 space bus size. bit 2 a2sz description 0 byte (8-bit) size 1 word (16-bit) size (initial value) bit 1 ? cs1 space size specifi cation (a1sz): specifies the cs1 space bus size. bit 1 a1sz description 0 byte (8-bit) size 1 word (16-bit) size (initial value) bit 0 ? cs0 space size specifi cation (a0sz): specifies the cs0 space bus size. bit 0 a0sz description 0 byte (8-bit) size 1 word (16-bit) size (initial value) note: a0sz is effective only in on-chip rom effective mode. in on-chip rom ineffective mode, the cs0 space bus size is specified by the mode pin. 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 109 of 716 rej09b0398-0500 8.2.2 bus control register 2 (bcr2) bcr2 is a 16-bit read/write register that specifies the number of idle cycles and cs signal assert extension of each cs space. bcr2 is initialized by power-on resets to h'ffff, but is not initialized by software standbys. bit: 15 14 13 12 11 10 9 8 iw31 iw30 iw21 iw20 iw11 iw10 iw01 iw00 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 cw3 cw2 cw1 cw0 sw3 sw2 sw1 sw0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 8 ? idles between cycles (iw31, iw30, iw21, iw20, iw11, iw10, iw01, iw00): these bits specify idle cycles inserted between consecutive accesses when the second one is to a different cs area after a read. idles are used to prevent data conflict between rom (and other memories, which are slow to turn the read data buf fer off), fast memories, and i/o interfaces. even when access is to the same area, idle cycles must be inserted when a read access is followed immediately by a write access. the id le cycles to be inserted comp ly with the area specification of the previous access . refer to section 8.6, waits between access cycles, for details. iw31, iw30 specify the idle between cycles for cs3 space; iw21, iw20 specify the idle between cycles for cs2 space; iw11, iw10 specify the id le between cycles for cs1 space and iw01, iw00 specify the idle between cycles for cs0 space. bit 15 iw31 bit 14 iw30 description 0 0 no idle cycle after accessing cs3 space 1 inserts one idle cycle 1 0 inserts two idle cycles 1 inserts three idle cycles ( initial value) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 110 of 716 rej09b0398-0500 bit 13 iw21 bit 12 iw20 description 0 0 no idle cycle after accessing cs2 space 1 inserts one idle cycle 1 0 inserts two idle cycles 1 inserts three idle cycles ( initial value) bit 11 iw11 bit 10 iw10 description 0 0 no idle cycle after accessing cs1 space 1 inserts one idle cycle 1 0 inserts two idle cycles 1 inserts three idle cycles ( initial value) bit 9 iw01 bit 8 iw00 description 0 0 no idle cycle after accessing cs0 space 1 inserts one idle cycle 1 0 inserts two idle cycles 1 inserts three idle cycles ( initial value) bits 7 to 4 ? idle specification for continuous access (cw3, cw2, cw1, cw0): the continuous access idle specification makes inserti ons to clearly delineate the bus intervals by once negating the csn signal when doing consecutive accesses of the same cs space. when a write immediately follows a read, the number of idle cycl es inserted is the larger of the two values specified by iw and cw. refer to section 8. 6, waits between access cycles, for details. cw3 specifies the continuous access idles for cs 3 space; cw2 specifies the continuous access idles for cs2 space; cw1 specifies the continuo us access idles for cs1 space and cw0 specifies the continuous access idles for cs0 space. bit 7 cw3 description 0 no cs3 space continuous access idle cycles 1 one cs3 space continuous access idle cycle (initial value) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 111 of 716 rej09b0398-0500 bit 6 cw2 description 0 no cs2 space continuous access idle cycles 1 one cs2 space continuous access idle cycle (initial value) bit 5 cw1 description 0 no cs1 space continuous access idle cycles 1 one cs1 space continuous access idle cycle (initial value) bit 4 cw0 description 0 no cs0 space continuous access idle cycles 1 one cs0 space continuous access idle cycle (initial value) bits 3 to 0 ? cs assert extension specification (sw3, sw2, sw1, sw0): the cs assert cycle extension specification is for making insertions to prevent extension of the rd signal or wrx signal assert period beyond the length of the csn signal assert period. extended cycles insert one cycle before and after each bus cycle, which simp lifies interfaces with external devices and also has the effect of extending write data hold time. refer to section 8.3.3, cs assert extension function, for details. sw3 specifies the cs assert extension for cs3 space access; sw2 specifies the cs assert extension for cs2 space access; sw1 specifies the cs assert extension for cs1 space access and sw0 specifies the cs assert extension for cs0 space access. bit 3 sw3 description 0 no cs3 space cs assert extension 1 cs3 space cs assert extension (initial value) bit 2 sw2 description 0 no cs2 space cs assert extension 1 cs2 space cs assert extension (initial value) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 112 of 716 rej09b0398-0500 bit 1 sw1 description 0 no cs1 space cs assert extension 1 cs1 space cs assert extension (initial value) bit 0 sw0 description 0 no cs0 space cs assert extension 1 cs0 space cs assert extension (initial value) 8.2.3 wait control register 1 (wcr1) wcr1 is a 16-bit read/write regist er that specifies the number of wa it cycles (0 to 15) for each cs space. wcr1 is initialized by power-on resets to h'ffff, but is not initialized by software standbys. bit: 15 14 13 12 11 10 9 8 w33 w32 w31 w30 w23 w22 w21 w20 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 w13 w12 w11 w10 w03 w02 w01 w00 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 12 ? cs3 space wait specification (w33, w32, w31, w30): specifies the number of waits for cs3 space access. bit 15 w33 bit 14 w32 bit 13 w31 bit 12 w30 description 0 0 0 0 no wait (external wait input disabled) 0 0 0 1 1 wait external wait input enabled ??? 1 1 1 1 15 wait external wait input enabled (initial value) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 113 of 716 rej09b0398-0500 bits 11 to 8 ? cs2 space wait specification (w23, w22, w21, w20): specifies the number of waits for cs2 space access. bit 11 w23 bit 10 w22 bit 9 w21 bit 8 w20 description 0 0 0 0 no wait (external wait input disabled) 0 0 0 1 1 wait external wait input enabled ??? 1 1 1 1 15 wait external wait input enabled (initial value) bits 7 to 4 ? cs1 space wait specification (w13, w12, w11, w10): specifies the number of waits for cs1 space access. bit 7 w13 bit 6 w12 bit 5 w11 bit 4 w10 description 0 0 0 0 no wait (external wait input disabled) 0 0 0 1 1 wait external wait input enabled ??? 1 1 1 1 15 wait external wait input enabled (initial value) bits 3 to 0 ? cs0 space wait specification (w03, w02, w01, w00): specifies the number of waits for cs0 space access. bit 3 w03 bit 2 w02 bit 1 w01 bit 0 w00 description 0 0 0 0 no wait (external wait input disabled) 0 0 0 1 1 wait external wait input enabled ??? 1 1 1 1 15 wait external wait input enabled (initial value) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 114 of 716 rej09b0398-0500 8.2.4 wait control register 2 (wcr2) wcr2 is a 16-bit read/write re gister that specifies the number of access cycles for dram space and cs space for dma single address mode transfers. do not perform any dma single address transfers before wcr2 is set. wcr2 is initialized by power-on resets to h'000f , but is not initialized by software standbys. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ddw1 ddw0 dsw3 dsw2 dsw1 dsw0 initial value: 0 0 0 0 1 1 1 1 r/w: r r r/w r/w r/w r/w r/w r/w bits 15 to 6 ? reserved: these bits always read as 0. the write value should always be 0. bits 5 and 4 ? dram space dma single address mode access wait specification (ddw1, ddw0): specifies the number of waits for dram space access during dma single address mode accesses. these bits are independent of the dww and dwr bits of the dcr. bit 5 ddw1 bit 4 ddw0 description 0 0 2-cycle (no wait) external wait disabled ( initial value) 1 3-cycle (1 wait) external wait disabled 1 0 4-cycle (2 wait) external wait enabled 1 5-cycle (3 wait) external wait enabled 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 115 of 716 rej09b0398-0500 bits 3 to 0 ? cs space dma single address mode access wait specification (dsw3, dsw2, dsw1, dsw0): specifies the number of waits for cs space access (0 to 15) during dma single address mode accesses. these bits are i ndependent of the w bits of the wcr1. bit 3 dsw3 bit 2 dsw2 bit 1 dsw1 bit 0 dsw0 description 0 0 0 0 no wait (external wait input disabled) 0 0 0 1 1 wait (external wait input enabled) ??? 1 1 1 1 15 wait (external wait input enabled) (initial value) 8.2.5 dram area control register (dcr) dcr is a 16-bit read/write register that selects the number of waits, operation mode, number of address multiplex shifts and the like for dram control. after a power-on reset, write the initial values to the bits in dcr and do not change the values afterward. do not perform any dram space accesses before dcr initial settings are completed. dcr is initialized by power-on resets to h'0000, but is not initialized by software standbys. bit: 15 14 13 12 11 10 9 8 tpc rcd tras1 tras0 dww1 dww0 dwr1 dwr0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 diw ? be rasd ? sz0 amx1 amx0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r r/w r/w r r/w r/w r/w bit 15 ? ras precharge cycle count (tpc): specifies the minimum number of cycles after ras is negated before next assert. bit 15 tpc description 0 1.5 cycles (initial value) 1 2.5 cycles 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 116 of 716 rej09b0398-0500 bit 14 ? ras-cas delay cycle count (rcd): specifies the number of row address output cycles. bit 14 rcd description 0 1 cycle (initial value) 1 2 cycles bits 13 and 12 ? cas-before-ras refresh ras assert cycle count (tras1 and tras0): specify the number of ras assert cy cles for cas before ras refreshes. bit 13 tras1 bit 12 tras0 description 0 0 2.5 cycles (initial value) 1 3.5 cycles 1 0 4.5 cycles 1 5.5 cycles bits 11 and 10 ? dram write cycle wait count (dww1 and dww0): specifies the number of dram write cycle column address output cycles. bit 11 dww1 bit 10 dww0 description 0 0 2-cycle (no wait) external wait disabled ( initial value) 1 3-cycle (1 wait) external wait disabled 1 0 4-cycle (2 wait) external wait enabled 1 5-cycle (3 wait) external wait enabled bits 9 and 8 ? dram read cycle wait count (dwr1 and dwr0): specifies the number of dram read cycle column address output cycles. bit 9 dwr1 bit 8 dwr0 description 0 0 2-cycle (no wait) external wait disabled ( initial value) 1 3-cycle (1 wait) external wait disabled 1 0 4-cycle (2 wait) external wait enabled 1 5-cycle (3 wait) external wait enabled 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 117 of 716 rej09b0398-0500 bit 7 ? dram idle cycle count (diw): specifies whether to insert idle cycles, either when accessing a different external space (cs space) or when doing a dram write, after dram reads. bit 7 diw description 0 no idle cycles (initial value) 1 1 idle cycle bit 6 ? reserved: this bit always read as 0. the write value should always be 0. bit 5 ? burst enable (be): specifies the dram operation mode. bit 5 be description 0 burst disabled (initial value) 1 dram high-speed page mode enabled . bit 4 ? ras down mode (rasd): specifies the dram operation mode. bit 4 rasd description 0 access dram by ras up mode (initial value) 1 access dram by ras down mode bit 3 ? reserved: this bit read 0 after a reset. the write value should always be 0. operation is not guaranteed if the write value is 1. bit 2 ? dram bus width specification (sz0): specifies the dram space bus width. bit 2 sz0 description 0 byte (8-bit) ( initial value) 1 word (16-bit) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 118 of 716 rej09b0398-0500 bits 1 and 0 ? dram address multiplex (amx1 and amx0): specifies the dram address multiplex count. bit 1 amx1 bit 0 amx0 description 0 0 9 bit ( initial value) 1 10 bit 1 0 11 bit 1 12 bit 8.2.6 refresh timer control/status register (rtcsr) rtcsr is a 16-bit read/write register that sel ects the refresh mode and the clock input to the refresh timer counter (rtcnt), and controls compare match interrupts (cmi). rtcsr is initialized by power-on resets to h' 0000, but is not initialized by software standbys. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? cmf cmie cks2 cks1 cks0 rfsh rmd initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w bits 15 to 7 ? reserved: these bits always read as 0. the write value should always be 0 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 119 of 716 rej09b0398-0500 bit 6 ? compare match flag (cmf): this status flag, which indicat es that the values of rtcnt and rtcor match, is set/cleared under the following conditions: bit 6 cmf description 0 clear condition: after rtcsr is read when cmf is 1, 0 is written in cmf. (initial value) 1 set condition: rtcnt = rtcor. when both rtcnt and rtcor are in an initialized state (when values have not been rewritten since initialization, and rtcnt has not had its value changed due to a count- up), rtcnt and rtcor match, as both are h'0000, but in this case cmf is not set. bit 5 ? compare match interrupt enable (cmie): enables or disables an interrupt request caused by the cmf bit of the rtcsr when cmf is set to 1. bit 5 cmie description 0 disables an interrupt request caused by cmf (initial value) 1 enables an interrupt request caused by cmf bits 4 to 2 ? clock select (cks2 to cks0): select the clock to input to rtcnt from among the seven types of internal clock obtained from dividing the system clock ( ). bit 4 cks2 bit 3 cks1 bit 2 cks0 description 0 0 0 stops count-up (initial value) 1 /2 1 0 /8 1 /32 1 0 0 /128 1 /512 1 0 /2048 1 /4096 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 120 of 716 rej09b0398-0500 bit 1 ? refresh control (rfsh): selects whether to use refresh control for dram. bit 1 rfsh description 0 do not refresh dram (initial value) 1 refresh dram bit 0 ? refresh mode (rmd): when the rfsh bit is 1, this bit selects normal refresh or self- refresh. when the rfsh bit is 1, self-refresh mode is entered immediately after the rmd bit is set to 1. when rmd is cleared to 0, a cas-before-ras refresh is performed at the interval set in the refresh time constant register (rtcnt). when set for self-refresh, the this lsi enters self-refresh mode immediately unless it is in the middle of a dram access. if it is, it enters se lf-refresh mode when the access ends. refresh requests from the interval timer are ignored in self-refresh mode. bit 0 rmd description 0 cas-before-ras refresh (initial value) 1 self-refresh 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 121 of 716 rej09b0398-0500 8.2.7 refresh timer counter (rtcnt) rtcnt is a 16-bit read/write register that is used as an 8-bit up counter for refreshes or generating interrupt requests. rtcnt counts up with the clock selected by the cks2 to cks0 bits of the rtcsr. rtcnt values can always be read/written by the cp u. when rtcnt matche s rtcor, rtcnt is cleared to h'0000 and the cmf flag of the rtcsr is set to 1. if the rfsh bit of rtcsr is 1 and the rmd bit is 0 at this time, a cas-before-ras refresh is performed. additionally, if the cmie bit of rtcsr is a 1, a compare match interrupt (cmi) is generated. bits 15 to 8 are reserved and play no part in counter operation. they are always read as 0. rtcnt is initialized by power-on resets to h'0000, but is not initialized by software standbys. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 122 of 716 rej09b0398-0500 8.2.8 refresh time constant register (rtcor) rtcor is a 16-bit read/write register that establishes the compare match period with rtcnt. the values of rtcor and rtcnt are constantly compared. when the va lues correspond, the compare match flag of rtcsr is set and rtcnt is cleared to 0. when the refresh bit (rfsh) of the rtcsr is set to 1 and the rmd bit is 0, a refresh request signal is produced by this match. the refresh request signal is held until a refresh operation is performed. if the refresh request is not processed before the next match, the previous request becomes ineffective. when the cmie bit of the rtscr is set to 1, an interrupt request is sent to the interrupt controller by this match signal. the interrupt request is output continuously until the cmf bit of the rtscr is cleared. bits 15 to 8 are reserved and cannot be used in setting the period. they always read 0. rtcor is initialized by power-on resets to h'0000, but is not initialized by software standbys. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 123 of 716 rej09b0398-0500 8.3 accessing ordinary space a strobe signal is output by ordinary space acce sses to provide primarily for sram or rom direct connections. 8.3.1 basic timing figure 8.3 shows the basic timing of ordinary space accesses. ordinary access bus cycles are performed in 2 states. t 1 ck address csn rd read write data wrx data t 2 figure 8.3 basic timing of ordinary space access during a read, irrespective of operand size, all bits in the data bus width for the access space (address) are fetched by the lsi on rd , using the required byte locations. during a write, the following signals are associated with transfer of th ese actual byte locations: wrh (bits 15 to 8) and wrl (bits 7 to 0). 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 124 of 716 rej09b0398-0500 8.3.2 wait state control the number of wait states inserted into ordina ry space access states can be controlled using the wcr settings (figure 8.4). the specified number of tw cycles are inserted as software wait cycles at the timing shown in figure 8.4. t 1 t w ck read write address csn rd data wrx data t 2 figure 8.4 wait timing of ordina ry space access (so ftware wait only) when the wait is specified by software using wcr, the wait input wait signal from outside is sampled. figure 8.5 shows the wait signal sampling. the wait signal is sampled at the clock rise one cycle before the clock rise when t w state shifts to t 2 state. 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 125 of 716 rej09b0398-0500 t 1 t w ck read write address csn wait rd data wrx data t w t w 0 t 2 figure 8.5 wait state timi ng of ordinary space access (wait states from software wait 2 state + wait signal) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 126 of 716 rej09b0398-0500 8.3.3 cs assert period extension idle cycles can be inserted to prevent extension of the rd signal or wrx signal assert period beyond the length of the csn signal assert period by setting the sw3 to sw0 bits of bcr2. this allows for flexible interfaces w ith external circuitr y. the timing is shown in figure 8.6. t h and t f cycles are added respectively before and after the ordinary cycle. only csn is asserted in these cycles; rd and wrx signals are not. further, data is extended up to the t f cycle, which is effective for gate arrays and the like, which have slower write operations. t h t 1 ck read write address csn rd data wrx data dack t 2 t f figure 8.6 cs assert period extension function 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 127 of 716 rej09b0398-0500 8.4 dram access 8.4.1 dram direct connection when address space a31 to a24 = h'01 has been accessed, the corresponding space becomes a 16-mbyte dram space, and the dram interface func tion can be used to directly connect this lsi to dram. row address and column address are always multiplexed for dram space. the amount of row address multiplexing can be selected as from 9 to 12 bits by setting the amx1 and amx0 bits of the dcr. table 8.4 amx bits and address multiplex output row address column address amx1 amx0 shift amount output address output pins output address output pins 0 0 9 bits a21 to a15 a21 to a15 a21 to a0 a21 to a0 a14 to a0 a23 to a9 1 10 bits a21 to a14 a21 to a14 a21 to a0 a21 to a0 a13 to a0 a23 to a10 1 0 11 bits a21 to a13 a21 to a13 a21 to a0 a21 to a0 a12 to a0 a23 to a11 1 12 bits a21 to a12 a21 to a12 a21 to a0 a21 to a0 a11 to a0 a23 to a12 in addition to ordinary read and write accesses, burst mode access using high speed page mode is supported. 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 128 of 716 rej09b0398-0500 8.4.2 basic timing this lsi supports 2 cas format dram access. the dram access basic timing is a minimum of 3 cycles for normal mode. figure 8.7 shows the basic dram access timing. dram space access is controlled by ras , casx and rdwr signals. the following signals are associated with transfer of these actual byte locations: cash (bits 15 to 8) and casl (bits 7 to 0). however, the signals for ordinary space, wrx and rd, are also output during the dmac single transfer column address cycle period. t p is the precharge cycle, t r is the ras assert cycle, t c is the cas assert cycle and t c2 is the read data fetch cycle. t p t r t c1 t c2 ck write read address data ras casx rdwr data rdwr casx ras row column figure 8.7 dram bus cycle (normal mode, tpc = 0, rcd = 0, no waits) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 129 of 716 rej09b0398-0500 8.4.3 wait state control wait state insertion during dram space access is controlled by setting the tpc, rcd, dww1, dww0, dwr1, and dwr0 bits of the dcr. tpc and rcd are common to both reads and writes. the timing with waits inserted is shown in figures 8.8 through 8.11. external waits can be inserted at the time of software waits 2, 3. the sampling location is the same as that of ordinary space: at one cycle before the t c2 cycle clock rise. wait cycles are extended by external waits. t p t r t c1 t cw1 t c2 ck write read address data ras casx rdwr data rdwr casx ras row column figure 8.8 dram bus cycle (normal mode, tpc = 0, rcd = 0, one wait) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 130 of 716 rej09b0398-0500 t p t r t rw t c1 t cw1 t cw2 t cw2 t pw ck write read address data ras casx rdwr data rdwr casx ras row column figure 8.9 dram bus cycle (normal mode, tpc = 1, rcd = 1, two waits) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 131 of 716 rej09b0398-0500 t p t c1 t cw1 t cw2 t cw3 t c2 t r ck write read address data ras casx rdwr data rdwr casx ras row column figure 8.10 dram bus cycle (normal mode, tpc = 0, rcd = 0, three waits) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 132 of 716 rej09b0398-0500 t p t c1 t cw1 t cw2 t cw0 t c2 t r ck write read address data ras casx rdwr data rdwr casx ras row column wait figure 8.11 dram bus cycle (normal mode, tpc = 0, rcd = 0, two waits + wait due to wait signal) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 133 of 716 rej09b0398-0500 8.4.4 burst operation high-speed page mode: when the burst enable bit (be) of the dcr is set, burst accesses can be performed using high speed page mode. the timing is shown in figure 8.12. wait cycles can be inserted during burst accesses by using the dcr. t p t c1 t c2 t c1 t c2 t r ck write read address data ras casx rdwr data rdwr casx ras row column column figure 8.12 dram bus cycle (high-speed page mode) ras down mode: there are some instances where even if burst operation is selected, continuous accesses to dram will not occur, but another sp ace will be accessed instead part way through the access. in such cases, if the ras signal is maintained at low le vel during the time the other space is accessed, it is possible to continue burst operatio n at the time the next dram same row address is accessed. this is called ras down mode. to use ras down mode, set both the be and rasd bits of the dcr to 1. figures 8.13 and 8.14 show operation in ras up and down modes. 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 134 of 716 rej09b0398-0500 ck ras casx dram access dram access cs space access address data cs space tp tr tc1 tc2 t1 t2 tp tr tc1 tc2 column column row row figure 8.13 dram access normal operation (ras up mode) ck ras casx dram access dram access cs space access address data row column cs space tp tr tc1 tc2 t1 t2 tc1 tc2 column figure 8.14 ras down mode 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 135 of 716 rej09b0398-0500 8.4.5 refresh timing the bus state controller is equipped with a function to control refreshes of dram. cas-before- ras (cbr) refresh or self-refresh can be selected by setting the rtcsr's rmd bit. cas-before-ras refresh: for cbr refreshes, set the rcr's rmd bit to 0 and the rfsh bit to 1. also write the values in rtcnt and rtcor necessary to fulfill the refresh interval prescribed for the dram being used. when a clock is selected with the cks2 to cks0 bits of the rstcr, rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared to the rtcor value and a cbr refresh is perform ed when the two match. rtcnt is cleared at that time and the count starts again. figure 8.15 shows the timing for the cbr refresh operation. the number of ras assert cycles in the refresh cycle is set by the tras 1, tras0 bits of the dcr. ck casx ras t rp t rr1 t rr2 t rc t rc figure 8.15 cas-before-ras refresh timing (tras1, tras0 = 0, 0) self-refresh: when both the rmd and rfsh bits of the rtcsr are set to 1, the cas signal and ras signal are output and the dram enters self-refresh mode, as shown in figure 8.16. do not access dram during self-refreshes, in order to preserve dram data. when performing dram accesses, first cancel the self-refresh, then access only after doing individual refreshes for all row addresses within the time prescribed for the particular dram. 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 136 of 716 rej09b0398-0500 ck casx ras t rp t rr1 t rr2 t rc t rc figure 8.16 self-refresh timing 8.5 address/data multiplex i/o space access when the bcr1 register ioe bit is set to 1, the d15 to d0 pins can be used for multiplexed address/data i/o for the cs3 space. consequen tly, peripheral lsis requiring address/data multiplexing can be directly connected to this lsi. address/data multiplex i/o space bus width is selected by the a14 bit, and is 8 bit when a14 = 0 and 16 bit when a14 = 1. 8.5.1 basic timing when the ioe bit of the bcr1 is set to 1, cs3 space becomes address/data multiplex i/o space. when this space is accessed, addresses and data are multiplexed. when the a14 address bit is 0, the bus size becomes 8 bit and addresses and data are input and output through the d7 to d0 pins. when the a14 address bit is 1, the bus size becomes 16 bit and address output and data i/o occur through the d15 to d0 pins. access for the address/data multiplex i/o space is controlled by the ah , rd and wrx signals. address/data multiplex i/o space accesses are done af ter a 3-cycle (fixed) address output, as an ordinary space type access (figure 8.17). 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 137 of 716 rej09b0398-0500 ck cs3 ah rd data wrx data address t a1 t a2 t a3 t a4 t 1 t 2 read write address output address output data output data input figure 8.17 address/data multiple x i/o space access timing (no waits) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 138 of 716 rej09b0398-0500 8.5.2 wait state control setting the wcr controls waits during address/data multiplex i/o space accesses. software wait and external wait insertion timing is the same as during ordinary space accesses. the timing for one software wait + one external wait inserted is shown in figure 8.18. ck cs3 ah rd data wrx data wait address t a1 t a2 t a3 t a4 t 1 t w t wo t 2 read write address output address output data output data input figure 8.18 address/data multiplex i/o spa ce access wait state ti ming (one software wait + one external wait) 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 139 of 716 rej09b0398-0500 8.5.3 cs assertion extension the timing diagram when cs assertion extension is set for address/data multiplexed i/o space access is shown in figure 8.19. cs3 ah rd data wrx data address t a1 t a2 t a3 t a4 t h t 1 t 2 t f read write address output address output data output data input figure 8.19 wait timing for a ddress/data multiplexed i/o space when cs assertion extension is set 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 140 of 716 rej09b0398-0500 8.6 waits between access cycles when a read from a slow device is completed, data buffers may not go off in time to prevent data conflicts with the next access. if there is a data conflict during memory access, the problem can be solved by inserting a wait in the access cycle. to enable detection of bus cycle starts, wait s can be inserted between access cycles during continuous accesses of the same cs space by negating the csn signal once. 8.6.1 prevention of data bus conflicts for the two cases of write cycles after read cycles, and read cycles for a different area after read cycles, waits are inserted so that the number of idle cycles specified by the iw31 to iw00 bits of the bcr2 and the diw of the dcr occur. when id le cycles already exist between access cycles, only the number of empty cycles remaining beyond the specified number of idle cycles are inserted. figure 8.20 shows an example of idles between cy cles. in this example, 1 idle between csn space cycles has been specified, so when a csm sp ace write immediately follows a csn space read cycle, 1 idle cycle is inserted. 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 141 of 716 rej09b0398-0500 ck csn csm rd data csn space read csm space write idle cycle wrx address t 1 t 2 t 1 t 2 t idle figure 8.20 idle cycle insertion example iw31 and iw30 specify the number of idle cycles required after a cs3 space read either to read other external spaces, or for this lsi, to do write accesses. in the same manner, iw21 and iw20 specify the number of idle cycles after a cs 2 space read, iw11 and iw10, the number after a cs1 space read, and iw01 and iw00, the number after a cs0 space read. diw specifies the number of idle cycles required, after a dram space read either to read other external spaces (cs space), or for this lsi, to do write accesses. 0 to 3 cycles can be specified for cs space, and 0 to 1 cycle for dram space. 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 142 of 716 rej09b0398-0500 8.6.2 simplification of bus cycle start detection for consecutive accesses of the same cs space, waits ar e inserted so that the number of idle cycles designated by the cw3 to cw0 bits of the bcr2 occur. however, for write cycles after reads, the number of idle cycles inserted will be the larger of the two values defined by the iw and cw bits. when idle cycles already exist between access cycles, waits are not inserted. figure 8.21 shows an example. a continuous access idle is specified for csn space, and csn space is consecutively write accessed. ck csn rd wrx data csn space access csn space access idle cycle address t 1 t 2 t 1 t 2 t idle figure 8.21 same space consecutive access idle cycle insertion example 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 143 of 716 rej09b0398-0500 8.7 bus arbitration it has two internal bus masters, the cpu and the dmac. the priority ranking for determining bus right transfer between these bus masters is: refresh > dmac > cpu 8.8 memory connection examples figures 8.22 to 8.27 show examples of the memory connections. as a21 to a18 become input ports in power-on reset, they should be handled (e.g. pulled down) as necessary. sh7014/16/17 32 k 8 bits ce oe csn rd a0 to a14 d0 to d7 a0 to a14 i/o0 to i/o7 rom figure 8.22 8-bit data bus width rom connection sh7014/16/17 256 k 16 bits rom ce oe csn rd a0 a1 to a18 d0 to d15 a0 to a17 i/o0 to i/o15 figure 8.23 16-bit data bus width rom connection 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 144 of 716 rej09b0398-0500 sh7014/16/17 csn rd wrl we cs oe a0 to a16 a0 to a16 d0 to d7 i/o0 to i/o7 123 k 8 bits sram figure 8.24 8-bit data bus width sram connection sh7014/16/17 128 k 8 bits sram csn rd cs oe a0 a1 to a17 a0 to a16 wrh we d8 to d15 i/o0 to i/o7 wrl d0 to d7 cs oe a0 to a16 we i/o0 to i/o7 figure 8.25 16-bit data bus width sram connection 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 145 of 716 rej09b0398-0500 sh7014/16/17 ras rdwr a0 to a9 casl ad0 to ad7 ras we a0 to a9 cas i/o0 to i/o7 oe 512 k 8 bits dram figure 8.26 8-bit data bus width dram connection ras ras rdwr we a0 oe a1 to a9 cash ucas casl lcas ad0 to ad15 i/o0 to i/o15 sh7014/16/17 256 k 16 bits dram a0 to a8 figure 8.27 16-bit data bus width dram connection 8.9 on-chip peripheral i/o register access on-chip peripheral i/o registers ar e accessed from the bus state controller, as shown in table 8.5. table 8.5 on-chip peripheral i/o register access on-chip peripheral module sci mtu intc pfc, port cmt a/d * wdt dmac cache connected bus width 8bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit access cycle 2cyc 2cyc 2cyc 2cyc 2cyc 2cyc 3cyc 3cyc 3cyc note: * the a/d in the sh7016 and sh7017 has an 8-bit width and is accessed in 3 cyc. 8. bus state controller (bsc) rev.5.00 sep. 27, 2007 page 146 of 716 rej09b0398-0500 8.10 cpu operation when progr am is in external memory in the sh7014, sh7016, and sh7017 f-ztat?, two words (equivalent to two instructions) are normally fetched in a single instruction fetch. this is also true when the program is located in external memory, irrespective of whether the external memory bus width is 8 or 16 bits. if the program counter value immediately after th e program branches is an odd-word (2n + 1) address, or if the program counter value immediat ely before the program branches is an even-word (2n) address, the cpu will always fetch 32 bits (equivalent to two instructions) that include the respective word instruction. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 147 of 716 rej09b0398-0500 section 9 direct memory access controller (dmac) 9.1 overview the sh7014 includes an on-chip two-channel direct memory access controller (dmac). the dmac can be used in place of the cpu to perfo rm high-speed data transfers among external devices equipped with dack (transfer request acknowledge signal), external memories, memory- mapped external devices, and on-chip peripheral modules (except for the dmac and bsc). using the dmac reduces the burden on the cpu and incr eases operating efficiency of the lsi as a whole. 9.1.1 features the dmac has the following features: ? two channels ? four gbytes of address space in the architecture ? byte, word, or longword selectable data transfer unit ? 64 k (65,536) transfers ? single or dual address mode. ? single address mode: either the transfer source or transfer destination (peripheral device) is accessed by a dack signal while the other is accessed by address. one transfer unit of data is transferred in each bus cycle. ? dual address mode: both the transfer s ource and transfer destination are accessed by address. values set in a dmac internal regi ster indicate the accessed address for both the transfer source and transfer destination. two bus cycles are required for one data transfer. ? channel function: dual address mode and single address mode external requests can be accepted. ? transfer requests: there are th ree dmac transfer activation requests, as indicated below. ? external request: from two dreq pins. dreq can be detected either by falling edge or by low level. these can be received by all channels. ? requests from on-chip peripheral modules: transfer requests from on-chip modules such as sci or a/d. these can be received by all channels. ? auto-request: the transfer request is generated automatically within the dmac. ? selectable bus modes: cycle-steal mode or burst mode ? the dmac priority order is fixed at 0 > 1. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 148 of 716 rej09b0398-0500 9.1.2 block diagram figure 9.1 is a block diagram of the dmac. peripheral bus internal bus on-chip ram dreq0 , dreq1 circuit control sarn dmac module re g ister control activation control request priority control bus interface bus state controller on-chip peripheral module darn dmatcrn chcrn dmaor mtu sci0, sci1 a/d converter dein external rom external ram external i/o (memory mapped) external i/o (with acknowled g e) dack0, dack1 drak0, drak1 on-chip rom * le g end: sarn: darn: dmatcrn: chcrn: dmaor: dmac source address re g ister dmac destination address re g ister dmac transfer count re g ister dmac channel control re g ister dmac operation re g ister notes: n = 0, 1 * sh7016, sh7017 only figure 9.1 dmac block diagram 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 149 of 716 rej09b0398-0500 9.1.3 pin configuration table 9.1 shows the dmac pins. table 9.1 dmac pin configuration channel name symbol i/o function 0 dma transfer request dreq0 i dma transfer request input from external device to channel 0 dma transfer request acknowledge dack0 o dma transfer strobe output from channel 0 to external device dreq0 acceptance confirmation drak0 o sampling receive acknowledge output for dma transfer request input from external source 1 dma transfer request dreq1 i dma transfer request input from external device to channel 1 dma transfer request acknowledge dack1 o dma transfer strobe output from channel 1 to external device dreq1 acceptance confirmation drak1 o sampling receive acknowledge output for dma transfer request input from external source 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 150 of 716 rej09b0398-0500 9.1.4 register configuration table 9.2 summarizes the dmac registers. dmac has a total of 9 registers. each channel has four control registers. one other control register is shared by all channels. table 9.2 dmac registers channel name abbrevi- ation r/w initial value address register size access size 0 dma source address register 0 sar0 r/w undefined h'ffff86c0 32 bit 16, 32 * 2 dma destination address register 0 dar0 r/w undefined h'ffff86c4 32 bit 16, 32 * 2 dma transfer count register 0 dmatcr0 r/w undefined h'ffff86c8 32 bit 16, 32 * 3 dma channel control register 0 chcr0 r/w * 1 h'00000000 h'ffff86cc 32 bit 16, 32 * 2 1 dma source address register 1 sar1 r/w undefined h'ffff86d0 32 bit 16, 32 * 2 dma destination address register 1 dar1 r/w undefined h'ffff86d4 32 bit 16, 32 * 2 dma transfer count register 1 dmatcr1 r/w undefined h'ffff86d8 32 bit 16, 32 * 3 dma channel control register 1 chcr1 r/w * 1 h'00000000 h'ffff86dc 32 bit 16, 32 * 2 shared dma operation register dmaor r/w * 1 h'0000 h'ffff86b0 16 bit 16 * 4 notes: 1. write 0 after reading 1 in bit 1 of chcr0, chcr1 and in bits 1 and 2 of the dmaor to clear flags. no other writes are allowed. 2. for 16-bit access of sar0, sar1, dar0, dar1, and chcr0, chcr1, the 16-bit value on the side not accessed is held. 3. dmatcr has a 16-bit configuration: bits 0 to 15. writing to the upper 16 bits (bits 16 to 31) is invalid, and these bits always read 0. 4. only 16-bit access for dmaor. 5. do not attempt to access an empty address. if an access is attemped, the system operation is not guarenteed. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 151 of 716 rej09b0398-0500 9.2 register descriptions 9.2.1 dma source address re gisters 0, 1 (sar0, sar1) dma source address registers 0, 1 (sar0, sar1) ar e 32-bit read/write regi sters that specify the source address of a dma transfer. these registers have a count function, and during a dma transfer, they indicate the next source address. in single-address mode, sar values are ignored when a device with dack has been sp ecified as the transfer source. specify a 16-bit or 32-bit boundary address when doing 16-bit or 32-bit data transfers. operation cannot be guaranteed on any other addresses. the initial value after power-on resets or in software standby mode is undefined. bit: 31 30 29 28 27 26 25 24 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 ? ? 2 1 0 ? ? initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w ? ? r/w r/w r/w 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 152 of 716 rej09b0398-0500 9.2.2 dma destination address registers 0, 1 (dar0, dar1) dma destination address registers 0, 1 (dar0, dar1) are 32-bit read/write registers that specify the destination address of a dm a transfer. these registers have a count function, and during a dma transfer, they indicate the ne xt destination address. in single-address mode, dar values are ignored when a device with dack has been specified as the transfer destination. specify a 16-bit or 32-bit boundary address when doing 16-bit or 32-bit data transfers. operation cannot be guaranteed on any other address. the in itial value after power-on resets or in software standby mode, is undefined. bit: 31 30 29 28 27 26 25 24 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 23 22 21 ? ? 2 1 0 ? ? initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w ? ? r/w r/w r/w 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 153 of 716 rej09b0398-0500 9.2.3 dma transfer count registers 0, 1 (dmatcr0, dmatcr1) dma transfer count registers 0, 1 (dmatcr0, dmatcr1) are 16-bit read/write registers that specify the transfer count for the channel (byte count, word count, or longword count). specifying a h'000001 gives a transfer count of 1, while h'000000 gives the maximum setting, 65,536 transfers. while dmac is in operation, the number of transfers to be performed is indicated. the initial value after power-on resets or in software standby mode is undefined. upper sixteen bits of this register are read as 0 and the write value should always be 0. bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ? ? initial value: ? ? ? ? ? ? ? ? r/w: r r r r r r r r bit: 15 14 13 12 11 10 9 8 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: ? ? ? ? ? ? ? ? r/w: r/w r/w r/w r/w r/w r/w r/w r/w 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 154 of 716 rej09b0398-0500 9.2.4 dma channel control registers 0, 1 (chcr0, chcr1) dma channel control registers 0, 1 (chcr0, chcr1) is a 32-bit read/write register where the operation and transmission of each channel is designa ted. bits 31 to 19 and bit 7 should always read 0. the written value should also be 0. they are initialized to 0 by a power-on reset and in software standby mode. bit: 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 23 22 21 20 19 18 17 16 ? ? ? ? ? rl am al initial value: 0 0 0 0 0 0 0 0 r r r r r r/w r/w r/w bit: 15 14 13 12 11 10 9 8 dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 ? ds tm ts1 ts0 ie te de initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/(w) * r/w note: * te bit: allows only 0 write after reading 1. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 155 of 716 rej09b0398-0500 bit 18 ? request check level (rl): selects whether to output drak notifying external device of dreq received, with active high or active low. bit 18 rl description 0 output drak with active high (initial value) 1 output drak with active low bit 17 ? acknowledge mode (am): in dual address mode, selects whether to output dack in the data write cycle or data read cycle. in single address mode, dack is always output irrespective of the setting of this bit. bit 17 am description 0 outputs dack during read cycle (initial value) 1 outputs dack during write cycle bit 16 ? acknowledge level (al): specifies whether to set dack (acknowledge) signal output to active high or active low. bit 16 al description 0 active high output (initial value) 1 active low output bits 15 and 14 ? destination address mode 1, 0 (dm1 and dm0): these bits specify increment/decrement of the dma transfer destination address. these bit specifications are ignored when transferring data from an external de vice to address space in single address mode. bit 15 dm1 bit 14 dm0 description 0 0 destination address fixed (initial value) 1 destination address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) 1 0 destination address decremented ( ? 1 during 8-bit transfer, ? 2 during 16-bit transfer, ? 4 during 32-bit transfer) 1 setting prohibited 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 156 of 716 rej09b0398-0500 bits 13 and 12 ? source address mode 1, 0 (sm1 and sm0): these bits specify increment/decrement of th e dma transfer source address. these bit specifications are ignored when transferring data from an external de vice to address space in single address mode. bit 13 sm1 bit 12 sm0 description 0 0 source address fixed (initial value) 1 source address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) 1 0 source address decremented ( ? 1 during 8-bit transfer, ? 2 during 16-bit transfer, ? 4 during 32-bit transfer) 1 setting prohibited bits 11 to 8 ? resource select 3 to 0 (rs3 to rs0): these bits specify the transfer request source. bit 11 rs3 bit 10 rs2 bit 9 rs1 bit 8 rs0 description 0 0 0 0 external request, dual address mode (initial value) 1 prohibited 1 0 external request, single address mode. external address space external device. 1 external request, single address mode. external device external address space. 1 0 0 auto-request 1 prohibited 1 0 mtu tgi0a 1 mtu tgi1a 1 0 0 0 mtu tgi2a 1 prohibited 1 0 prohibited 1 a/d adi 1 0 0 sci0 txi0 1 sci0 rxi0 1 0 sci1 txi1 1 sci1 rxi1 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 157 of 716 rej09b0398-0500 bit 6 ? dreq select (ds): sets the sampling method for the dreq pin in external request mode to either low-level detection or falling-edge de tection. when specifying an on-chip peripheral module or auto-request as the transfer request source, this bit setting is ignored. the sampling method is fixed at falling- edge detection in cases other than auto-request. bit 6 ds description 0 low-level detection (initial value) 1 falling-edge detection bit 5 ? transfer mode (tm): specifies the bus mode for data transfer. bit 5 tm description 0 cycle steal mode (initial value) 1 burst mode bits 4 and 3 ? transfer size 1, 0 (ts1, ts0): specifies size of data for transfer. bit 4 ts1 bit 3 ts0 description 0 0 specifies byte size (8 bits) (initial value) 1 specifies word size (16 bits) 1 0 specifies longword size (32 bits) 1 prohibited bit 2 ? interrupt enable (ie): when this bit is set to 1, interrupt requests are generated after the number of data transfers specified in the dmatcr (when te = 1). bit 2 ie description 0 interrupt request not generated after dmatcr-specified transfer count (initial value) 1 interrupt request enabled on completion of dmatcr specified number of transfers 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 158 of 716 rej09b0398-0500 bit 1 ? transfer end flag (te): this bit is set to 1 after the number of data transfers specified by the dmatcr. at this time, if the ie bit is set to 1, an interrupt request is generated. if data transfer ends before te is set to 1 (for example, due to an nmi or address error, or clearing of the de bit or dme bit of the dmaor) the te is not set to 1. with this bit set to 1, data transfer is disabled even if the de bit is set to 1. bit 1 te description 0 dmatcr-specified transfer count not ended (initial value) clear condition: 0 write after te = 1 read, power-on reset, standby mode 1 dmatcr specified number of transfers completed bit 0 ? dmac enable (de): de enables operation in the corresponding channel. bit 0 de description 0 operation of the corresponding channel disabled (initial value) 1 operation of the corresponding channel enabled transfer mode is entered if this bit is set to 1 when auto-request is specified (rs3 to rs0 settings). with an external request or on-chip module request, when a transfer request occurs after this bit is set to 1, transfer is enabled. if this bit is cleared during a data transfer, transfer is suspended. if the de bit has been set, but te = 1, then if the dme bit of the dmaor is 0, and the nmi or ae bit of the dmaor is 1, transfer enable mode is not entered. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 159 of 716 rej09b0398-0500 9.2.5 dmac operation register (dmaor) the dmaor is a 16-bit read/write register that specifies the transfer mode of the dmac. bits 15 to 3 of this register always read as 0. the write value should always be 0. register values are initialized to 0 during pow er-on reset or in software standby mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ae nmif dme initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/(w) * r/(w) * r note: * 0 write only is valid after 1 is read. bit 2 ? address error flag (ae): indicates that an address e rror has occurred during dma transfer. if this bit is set during a data transfer, transfers on all channels are suspended. the cpu cannot write a 1 to the ae bit. clearing is effected by 0 write after 1 read. bit 2 ae description 0 no address error, dma transfer enabled (initial value) clearing condition: write ae = 0 after reading ae = 1 1 address error, dma transfer disabled setting condition: address error due to dmac 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 160 of 716 rej09b0398-0500 bit 1 ? nmi flag (nmif): indicates input of an nmi. this bit is set irrespective of whether the dmac is operating or suspended. if this bit is set during a data transfer, transfers on all channels are suspended. the cpu is unable to write a 1 to the nmif. clearing is effected by a 0 write after 1 read. bit 1 nmif description 0 no nmi interrupt, dma transfer enabled (initial value) clearing condition: write nmif = 0 after reading nmif = 1 1 nmi has occurred, dmc transfer prohibited set condition: nmi interrupt occurrence bit 0 ? dmac master enable (dme): this bit enables activation of the entire dmac. when the dme bit and de bit of the chcr for the corresponding channel are set to 1, that channel is transfer-enabled. if this bit is cleared during a data transfer, transfers on all channels are suspended. even when the dme bit is set, when the te bit of th e chcr is 1, or its de bit is 0, transfer is disabled in the case of an nmi of the dmaor or when ae = 1. bit 0 dme description 0 disable operation on all channels (initial value) 1 enable operation on all channels 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 161 of 716 rej09b0398-0500 9.3 operation when there is a dma transfer request, the dmac starts the tran sfer according to the predetermined channel priority order; when the transfer end conditions ar e satisfied, it ends the transfer. transfers can be requested in three mode s: auto-request, external request, and on-chip peripheral module request. transfer can be in eith er the single address mode or the dual address mode. the bus mode can be either burst or cycle steal. 9.3.1 dma transfer flow after the dma source address registers (sar), dma destination address registers (dar), dma transfer count register (dmatcr), dma channel control registers (chcr), and dma operation register (dmaor) are set to the desired transf er conditions, the dmac transfers data according to the following procedure: 1. the dmac checks to see if transfer is enabled (de = 1, dme = 1, te = 0, nmif = 0, ae = 0). 2. when a transfer request comes and transfer ha s been enabled, the dmac transfers 1 transfer unit of data (determined by ts0 and ts1 setting). for an auto-request, the transfer begins automatically when the de bit and dme bit are set to 1. the dmatcr value will be decremented by 1 upon each transfer. the actual transfer flows vary by address mode and bus mode. 3. when the specified number of transfers have been completed (when dmatcr reaches 0), the transfer ends normally. if the ie bit of the chcr is set to 1 at this time, a dei interrupt is sent to the cpu. 4. when an address error occurs in the dmac or an nmi interrupt is generated, the transfer is aborted. transfers are also aborted when the de bit of the chcr or the dme bit of the dmaor are changed to 0. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 162 of 716 rej09b0398-0500 figure 9.2 is a flowchart of this procedure. normal end does nmif = 1, ae = 1, de = 0, or dme = 0? bus mode, transfer request mode, dreq detection selection system initial settin g s (sar, dar, dmatcr, chcr, dmaor) transfer (1 transfer unit); dmatcr ? 1 dmatcr, sar and dar updated dei interrupt request (when ie = 1) no yes no yes no yes yes no yes no * 3 * 2 start transfer aborted notes: 1. 2. 3. in auto-request mode, transfer be g ins when nmif, ae, and te are all 0, and the de and dme bits are set to 1. dreq level detection in burst mode (external request) or cycle-steal mode. dreq ed g e detection in burst mode (external request), or auto-request mode in burst mode. dmatcr = 0? transfer request occurs? * 1 de, dme = 1 and nmif, ae, te = 0? does nmif = 1, ae = 1, de = 0, or dme = 0? transfer ends figure 9.2 dmac transfer flowchart 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 163 of 716 rej09b0398-0500 9.3.2 dma transfer requests dma transfer requests are usually generated in either the data transfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. the request mode is selected in the rs3 to rs0 bits of the dma channel control registers 0, 1 (chcr0, chcr1). auto-request mode: when there is no transfer request signa l from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the dmac to automatically generate a transfer request signal internally. when the de bits of chcr0, chcr1 and the dme bit of the dmaor are set to 1, the transfer begins (so long as the te bits of chcr0, chcr1 and the nmif and ae bits of dmaor are all 0). external request mode: in this mode a transfer is performed at the request signal ( dreq ) of an external device. choose one of the modes shown in table 9.3 according to the application system. when this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, nmif = 0, ae = 0), a transfer is performed upon a request at the dreq input. choose to detect dreq by either the falling edge or low level of the signal input with the ds bit of chcr0, chcr1 (ds = 0 is level detection, ds = 1 is edge detection). the source of the transfer request does not have to be the data transfer source or destination. table 9.3 selecting external re quest modes with the rs bits rs3 rs2 rs1 rs0 address mode source destination 0 0 0 0 dual address mode any * any * 1 0 single address mode external memory or memory-mapped external device external device with dack 1 single address mode external device with dack external memory or memory-mapped external device note: * external memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding dmac, bsc). 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 164 of 716 rej09b0398-0500 on-chip peripheral module request mode: in this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-c hip peripheral module. as indicated in table 9.4, there are eight transfer request signals: three from the multifunction timer pulse unit (mtu), which are compare match or input capture interrupts; the receive data full interrupts (rxi) and transmit data empty interrupts (txi) of the two se rial communication interf aces (sci); and the a/d conversion end interrupt (adi) of the a/d converter. when dma transfers are enabled (de = 1, dme = 1, te = 0, nmif = 0, ae = 0), a transfer is performed upon the input of a transfer request signal. the transfer request source need not be the data transfer source or transfer destination. however, when the transfer request is set by rxi (transfer request because sci's receive data is full), the transfer source must be the sci's receive data regi ster (rdr). when the transfer request is set by txi (transfer request because sci's transmit data is empty), the transfer de stination must be the sci's transmit data register (tdr). also, if the transfer request is set to the a/d converter, the data transfer destination must be the a/d converter register. table 9.4 selecting on-chip peripheral module request modes with the rs bits rs3 rs2 rs1 rs0 dmac transfer request source dma transfer request signal source destin- ation bus mode 0 1 1 0 mtu * 2 tgi0a any * 1 any * 1 burst/cycle steal 1 mtu * 2 tgi1a any * 1 any * 1 burst/cycle steal 1 0 0 0 mtu * 2 tgi2a any * 1 any * 1 burst/cycle steal 1 prohibited 1 0 prohibited 1 a/d adi addr * 4 any * 1 burst/cycle steal 1 0 0 sci0 * 3 transmit block txi0 any * 1 tdr0 burst/cycle steal 1 sci0 * 3 receive block rxi0 rdr0 any * 1 burst/cycle steal 1 0 sci1 * 3 transmit block txi1 any * 1 tdr1 burst/cycle steal 1 sci1 * 3 receive block rxi1 rdr1 any * 1 burst/cycle steal notes: 1. external memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding dmac, bsc). 2. mtu: multifunction timer pulse unit. 3. sci0, sci1: serial communications interface. 4. addr: a/d converter's a/d register. in order to output a transfer request from an on-chip peripheral module, set the relevant interrupt enable bit for each module, and output an interrupt signal. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 165 of 716 rej09b0398-0500 when an on-chip peripheral module's interrupt request signal is used as a dma transfer request signal, interrupts for the cpu are not generated. when a dma transfer is conducted corresponding with one of the transfer request signals in table 9.4, it is automatically discontinued. in cycle steal mode this occurs in the first transfer, and in burst mode with the last transfer. 9.3.3 channel priority when the dmac receives simultaneous transfer re quests on two or more channels, it selects a channel according to a predetermined priority order. the channel priority order is fixed at channel 0 > channel 1. 9.3.4 dma transfer types the dmac supports the transfers shown in table 9.5. it can operate in the single address mode, in which either the transfer source or destination is accessed using an acknowledge signal, or dual address mode, in which both the transfer source and destination addresses are output. the dmac has two bus modes: cycle-steal mode and burst mode. table 9.5 supported dma transfers destination source external device with dack external memory memory- mapped external device on-chip memory on-chip peripheral module external device with dack not available single single not available not available external memory single dual dual dual dual memory-mapped external device single dual dual dual dual on-chip memory not available dual dual dual dual on-chip peripheral module not available dual dual dual dual notes: 1. single: single address mode 2. dual: dual address mode 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 166 of 716 rej09b0398-0500 address modes single address mode: in the single address mode, both the transfer source and destination are external; one (selectable) is accessed by a dack signal while the other is accessed by an address. in this mode, the dmac performs the dma transfer in 1 bus cycle by simultaneously outputting a transfer request acknowledge dack signal to one external device to access it while outputting an address to the other end of the transfer. figure 9.3 shows an example of a transfer between an external memory and an external device with dac k in which the external device outputs data to the data bus while that data is written in external memory in the same bus cycle. dmac dack dreq external memory external device with dack this lsi external address bus : data flow external data bus figure 9.3 data flow in single address mode two types of transfers are possible in the singl e address mode: (a) transfers between external devices with dack and memory-mapped external devices, and (b) transfers between external devices with dack and external memory. the only transfer requests for either of these is the external request ( dreq ). figure 9.4 shows the dma transfer timing for the single address mode. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 167 of 716 rej09b0398-0500 ck a21 to a0 csn d15 to d0 dack wrh wrl address output to external memory space data that is output from the external device with dack dack si g nal to external devices with dack (active low) wr si g nal to external memory space a. external device with dack to external memory space ck a21 to a0 csn d15 to d0 rd address output to external memory space data that is output from external memory space rd si g nal to external memory space dack si g nal to external device with dack (active low) dack b. external memory space to external device with dack figure 9.4 example of dma transfer timing in the single address mode dual address mode: dual address mode is used for access of both the transfer source and destination by address. transfer source and des tination can be accessed either internally or externally. in dual address mode, data is read from the transfer source during the data read cycle, and written to the transfer destination during the write cycle, so transfer is conducted in two bus cycles. at this time, the transfer data is temporar ily stored in the dmac. with the kind of external memory transfer shown in figure 9.5, data is read from one of the memories by the dmac during a read cycle, then written to the other external memory during the subsequent write cycle. figure 9.6 shows the timing for this operation. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 168 of 716 rej09b0398-0500 data buffer address bus data bus address bus data bus memory transfer source module transfer destination module memory transfer source module transfer destination module sar dar data buffer sar dar the sar value is taken as the address, and data is read from the transfer source module and stored temporarily in the dmac. 1st bus cycle 2nd bus cycle the dar value is taken as the address, and data stored in the dmac's data buffer is written to the transfer destination module. dmac dmac figure 9.5 operation during dual address mode 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 169 of 716 rej09b0398-0500 data read cycle data write cycle transfer destination address transfer source address ck (1st cycle) (2nd cycle) a21 to a0 csn d15 to d0 rd w rh , wrl dack note: transfer between external memories with dack are output durin g read cycle. figure 9.6 example of transfer timing in dual address mode 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 170 of 716 rej09b0398-0500 bus modes select the appropriate bus mode in the tm b its of chcr0, chcr1. there are two bus modes: cycle steal and burst. cycle-steal mode: in the cycle steal mode, the bus right is given to another bus master after each one-transfer-unit (byte, word, or longword) dmac transfer. when the next transfer request occurs, the bus rights are obtained from the other bus master and a transfer is performed for one transfer unit. when that transfer ends, the bus right is passed to the other bus master. this is repeated until the transfer end conditions are satisfied. the cycle steal mode can be used with all categorie s of transfer destination, transfer source and transfer request. figure 9.7 shows an example of dma transfer timing in the cycle steal mode. transfer conditions are dual address mode and dreq level detection. cpu cpu cpu dmac dmac cpu dmac dmac cpu cpu dreq bus cycle bus control returned to cpu read write write read figure 9.7 dma transfer exam ple in the cycle-steal mode burst mode: once the bus right is obtained, the tran sfer is performed continuously until the transfer end condition is satisfied. in the external request mode with low level detection of the dreq pin, however, when the dreq pin is driven high, the bus passes to the other bus master after the bus cycle of the dmac that currently has an acknowledged request ends, even if the transfer end conditions have not been satisfied. figure 9.8 shows an example of dma transfer timing in the burst mode. transfer conditions are single address mode and dreq level detection. cpu cpu cpu dmac dmac dmac dmac dmac dreq bus cycle dmac cpu figure 9.8 dma transfer e xample in the burst mode 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 171 of 716 rej09b0398-0500 relationship between request modes and bus modes by dma transfer category table 9.6 shows the relationship between request modes and bus modes by dma transfer category. table 9.6 relationship of request modes and bus modes by dma transfer category address mode transfer category request mode bus * 5 mode transfer size (bits) usable channels single external device with dack and external memory external b/c 8/16/32 0,1 external device with dack and memory-mapped external device external b/c 8/16/32 0, 1 dual external memory and external memory any * 1 b/c 8/16/32 0, 1 external memory and memory-mapped external device any * 1 b/c 8/16/32 0, 1 memory-mapped external device and memory-mapped external device any * 1 b/c 8/16/32 0, 1 external memory and on-chip memory any * 1 b/c 8/16/32 0, 1 external memory and on-chip peripheral module any * 2 b/c * 3 8/16/32 * 4 0, 1 memory-mapped external device and on-chip memory any * 1 b/c 8/16/32 0, 1 memory-mapped external device and on-chip peripheral module any * 2 b/c * 3 8/16/32 * 4 0, 1 on-chip memory and on-chip memory any * 1 b/c 8/16/32 0, 1 on-chip memory and on-chip peripheral module any * 2 b/c * 3 8/16/32 * 4 0, 1 * 1 on-chip peripheral module and on- chip peripheral module any * 2 b/c * 3 8/16/32 * 4 0, 1 notes: 1. external request, auto-request or on-chip peripheral module request enabled. however, in the case of on-chip peripheral module request, it is not possible to specify the sci or a/d converter for the transfer request source. 2. external request, auto-request or on-chip peripheral module request possible. however, if transfer request source is also the sci or a/d converter, the transfer source or transfer destination must be the sci or a/d converter. 3. when the transfer request source is the sci, only cycle steal mode is possible. 4. access size permitted by register of on- chip peripheral module that is the transfer source or transfer destination. 5. b: burst, c: cycle steal 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 172 of 716 rej09b0398-0500 bus mode and channel priority order when a given channel is transferring in burst mode, and a transfer request is issued to channel 0, which has a higher priority ranking, transfer on channel 0 begins immediately. channel 1 transfer is continued after transfer on channel 0 are completely ended, whether the channel 0 setting is cycle steal mode or burst mode. 9.3.5 number of bus cycle states and dreq pin sample timing number of states in bus cycle: the number of states in the bus cycle when the dmac is the bus master is controlled by the bus state controlle r (bsc) just as it is when the cpu is the bus master. for details, see section 8, bus state controller. dreq pin sampling timing and drak signal: in external request mode, the dreq pin is sampled by either falling edge or low-level detection. when a dreq input is detected, a dmac bus cycle is issued and dma transfer effected, at the earliest, after three states. however, in burst mode when single address operation is specified, a du mmy cycle is inserted fo r the first bus cycle. in this case, the actual data transfer starts from the second bus cycle. data is transferred continuously from the second bus cycle. the dummy cycle is not counted in the number of transfer cycles, so there is no need to recognize the dummy cycle when setting the dmatcr. dreq sampling from the second time begins from the start of the transfer one bus cycle prior to the dmac transfer generated by the previous sampling. drak is output once for the first dreq sampling, irrespective of transfer mode or dreq detection method. in burst mode, using edge detection, dreq is sampled for the first cycle only, so drak is also output for the first cycle only. therefore, the dreq signal negate timing can be ascertained, and this facilitates handshake operations of transfer requests with the dmac. cycle steal mode operations: in cycle steal mode, dreq sampling timing is the same irrespective of dual or single address mode, or whether edge or low-level dreq detection is used. for example, dmac transfer begins (figure 9.9) , at the earliest, three cycles from the first sampling timing. the second sampling begins at the start of the transfer on e bus cycle prior to the start of the dmac transfer initiated by the first sampling (i.e., from the start of the cpu(3) transfer). at this point, if dreq detection has not occurred, sampling is executed every cycle thereafter. as in figure 9.10, whatever cycl e the cpu transfer cy cle is, the next sampling begins from the start of the transfer one bus cycle before the dmac transfer begins. figure 9.9 shows an example of output during dack read and figure 9.10 an example of output during dack write. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 173 of 716 rej09b0398-0500 ck dreq drak bus cycle dack cpu(3) cpu(4) cpu(5) cpu(2) cpu(1) 1st sampling 2nd sampling dmac(r) dmac(r) dmac(w) dmac(w) dmac(w) dmac(r) figure 9.9 cycle steal, dual address and level detection (fastest operation) 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 174 of 716 rej09b0398-0500 ck dreq drak bus cycle dack cpu cpu cpu cpu dmac(r) dmac (r) dmac(w) 1st samplin g 2nd samplin g note: with cycle-steal and dual address operation, samplin g timin g is the same whether dreq detection is by level or by ed g e. figure 9.10 cycle steal, dual addre ss and level detection (normal operation) 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 175 of 716 rej09b0398-0500 figures 9.11 and 9.12 show cycle steal mode and single address mode. in this case, transfer begins at earliest three cycles after the first dreq sampling. the second sampling begins from the start of the transfer one bus cycle before the start of the first dmac transfer. in single address mode, the dack signal is output during the dmac transfer period. ck dreq drak bus cycle dack cpu cpu cpu cpu cpu dmac dmac dmac figure 9.11 cycle steal, single address and level detection (fastest operation) 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 176 of 716 rej09b0398-0500 ck dreq drak bus cycle dack cpu cpu dmac cpu dmac cpu cpu note: with cycle-steal and sin g le address operation, samplin g timin g is the same whether dreq detection is by level or by ed g e. figure 9.12 cycle steal, single address and level detection (normal operation) 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 177 of 716 rej09b0398-0500 burst mode, dual address, and level detection: dreq sampling timing in burst mode with dual address and level detection is shown in figures 9.13 and 9.14. dreq sampling timing in burst mode with dual address and level detection is vi rtually the same as that of cycle steal mode. for example, dmac transfer begins (figure 9.13), at the earliest, three cycl es after the timing of the first sampling. the second sampling also begins from the start of the transfer one bus cycle before the start of the first dmac transfer. in burst mode, as long as transfer requests are issued, dmac transfer continues. therefore, the ?trans fer one bus cycle before the start of the dmac transfer? may be a dmac transfer. in burst mode, the dack output period is the same as that of cycle steal mode. figure 9.14 shows the normal operation of this burst mode. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 178 of 716 rej09b0398-0500 ck dreq drak bus cycle dack cpu cpu cpu cpu dmac(r) dmac(w) dmac(r) dmac(r) dmac(w) dmac(r) dmac(w) figure 9.13 burst mode, dual address and level detection (fastest operation) 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 179 of 716 rej09b0398-0500 ck dreq drak bus cycle dack cpu cpu dmac(r) dmac(r) dmac(r) cpu dmac(w) dmac(w) figure 9.14 burst mode, dual address and level detection (normal operation) 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 180 of 716 rej09b0398-0500 burst mode, single address, and level detection: dreq sampling timing in burst mode with single address and level detection is shown in figures 9.15 and 9.16. in burst mode with single address and level detection, a dummy cycle is inserted as one bus cycle, at the earliest, three cycles after timing of the first sampling. data during this period is undefined, and the dack signal is not output. nor is the number of dmac transfers counted. the actual dmac transfer begins after one dummy bus cycle output. the dummy cycle is not counted either at the start of the second sampling (transfer one bus cycle before the start of the first dmac transfer). therefore, the second sampling is not conducted from the bus cycle starting the dummy cycle, but fr om the start of the cpu(3) bus cycle. thereafter, as long the dreq is continuously sampled, no dummy cycle is inserted. dreq sampling timing during this period begins from the start of the transfer one bus cycle before the start of dmac transfer, in the sa me way as with cycle steal mode. as with the fourth sampling in figure 9.15, once dmac transfer is interrupted, a dummy cycle is again inserted at the start as so on as dmac transfer is resumed. the dack output period in burst mode is the same as in cycle steal mode. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 181 of 716 rej09b0398-0500 ck dreq drak bus cycle dack cpu(4) cpu(1) cpu(2) cpu(3) dummy dmac dummy 2nd sampling 1st sampling 3rd sampling 4th sampling dmac dmac figure 9.15 burst mode, single address and level detection (fastest operation) 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 182 of 716 rej09b0398-0500 ck dreq drak bus cycle dack cpu cpu dummy dmac cpu dmac dmac figure 9.16 burst mode, single address and level detection (normal operation) 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 183 of 716 rej09b0398-0500 burst mode, dual address, and edge detection: in burst mode with dual address and edge detection, dreq sampling is conducted only on the first cycle. in figure 9.17, dmac transfer begins, at the ear liest, three cycles after the timing of the first sampling. thereafter, dmac transfer continues until the end of the data transfer count set in the dmatcr. dreq sampling is not conducted during this period. therefore, drak is output on the first cycle only. when dmac transfer is resumed after being halted by a nmi or address error, be sure to reinput an edge request. the remaining transfer restarts after the first drak output. the dack output period in burst mode is the same as in cycle steal mode. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 184 of 716 rej09b0398-0500 ck dreq drak bus cycle dack cpu cpu cpu dmac(r) dmac(r) dmac(r) dmac(r) dmac(w) dmac(w) dmac(w) dmac(w) figure 9.17 burst mode, dual address and edge detection 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 185 of 716 rej09b0398-0500 burst mode, single address, and edge detection: in burst mode with single address and edge detection, dreq sampling is conducted only on the first cycle. in figure 9.18, a dummy cycle is inserted, at the earliest, three cycles after the timing for the first sampling. during this period, data is undefined, and dack is not output. nor is the number of dmac transfers counted. the actual dmac transfer begins after one dummy bus cycl e output. thereafter, dmac transfer continues until the data transfer count set in the dmatcr has ended. dreq sampling is not conducted during this period. therefore, drak is output on the first cycle only. when dmac transfer is resumed after being halted by a nmi or address error, be sure to reinput an edge request. drak is output once, and the re maining transfer restarts after output of one dummy cycle. the dack output period in burst mode is the same as in cycle steal mode. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 186 of 716 rej09b0398-0500 ck dreq drak bus cycle dack cpu dmac dmac dmac dmac cpu cpu dummy figure 9.18 burst mode, single address and edge detection 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 187 of 716 rej09b0398-0500 9.3.6 dma transfer ending conditions the dma transfer ending conditions vary for individual channels ending and for all channels ending together. individual channel ending conditions: there are two ending conditions. a transfer ends when the value of the channel's dma tran sfer count register (dmatcr) is 0, or when the de bit of the channel's chcr is cleared to 0. ? when dmatcr is 0: when the dmatcr value becomes 0 and the corresponding channel's dma transfer ends, the transfer end flag bit (te) is set in the chcr. if the ie (interrupt enable) bit has been set, a dmac interrupt (dei) is requested of the cpu. ? when de of chcr is 0: software can halt a dma transfer by clearin g the de bit in the channel's chcr. the te bit is not set when this happens. conditions for ending all channels simultaneously: transfers on all channels end when the nmif (nmi flag) bit or ae (address error flag) bit is set to 1 in the dmaor, or when the dme bit in the dmaor is cleared to 0. ? when the nmif or ae bit is set to 1 in dmaor: when an nmi interrupt or dmac address error occurs, the nmif or ae bit is set to 1 in the dmaor and all channels stop their transfers. the dmac obtains the bus rights, and if these flags are set to 1 during execution of a transfer, dmac halts operation when the transf er processing currently being executed ends, and transfers the bus right to the other bus master. consequently, even if the nmif or ae bits are set to 1 during a transfer, the dma source address register (sar), designation address register (dar), and dma transfer count register (dmatcr) are all updated. the te bit is not set. to resume the transfers after nmi in terrupt or address error processing, clear the appropriate flag bit to 0. to avoid restarting a tr ansfer on a particular channel, clear its de bit to 0. when the processing of a one unit transfer is complete. in a dual address mode direct address transfer, even if an address error occurs or the nmi flag is set during read processing, the transfer will not be halted until after completion of the following write processing. in such a case, sar, dar, and dmatcr values are updated. ? when dme is cleared to 0 in dmaor: clearing the dme bit to 0 in the dmaor aborts the transfers on all channels. the te bit is not set. 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 188 of 716 rej09b0398-0500 9.3.7 dmac access from cpu the space addressed by the dmac is 3-cycle space. therefore, when the cpu becomes the bus master and accesses the dmac, a minimum of thr ee basic clock (clk) cycles are required for one bus cycle. also, since the dmac is located in word space, while a word-size access to the dmac is completed in one bus cycle, a longwo rd-size access is automatically divided into two word accesses, requiring two bus cycles (six ba sic clock cycles). these two bus cycles are executed consecutively; a different bus cycle is never inserted between the two word accesses. this applies to both write accesses and read accesses. 9.4 examples of use 9.4.1 example of dma transfer between on-chip sci and external memory in this example, on-chip seri al communication interface channel 0 (sci0) received data is transferred to external memory using the dmac channel 1. table 9.7 indicates the transfer conditions and the setting values of each of the registers. table 9.7 transfer conditions and register se t values for transfer between on-chip sci and external memory transfer conditions register value transfer source: rdr0 of on-chip sci0 sar1 h'ffff81a5 transfer destination: external memory dar1 h'00400000 transfer count: 64 times dmatcr1 h'00000040 transfer source addre ss: fixed chcr1 h'00004d05 transfer destination address: incremented transfer request source: sci0 (rdr0) bus mode: cycle steal transfer unit: byte interrupt request generation at end of transfer channel priority ranking: 0 > 1 dmaor h'0001 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 189 of 716 rej09b0398-0500 9.4.2 example of dma transfer between external ram and external device with dack in this example, an external request, single addr ess mode transfer with external memory as the transfer source and an external device with dack as the transfer destin ation is executed using dmac channel 1. table 9.8 indicates the transfer conditions and the setting values of each of the registers. table 9.8 transfer conditions and register se t values for transfer between external ram and external device with dack transfer conditions register value transfer source: external ram sar1 h'00400000 transfer destination: external device with dack dar1 (access by dack) transfer count: 32 times dmatcr1 h'00000020 transfer source address: decremented chcr1 h'00002269 transfer destination address: (setting ineffective) transfer request source: external pin ( dreq1 ) edge detection bus mode: burst transfer unit: word no interrupt request generation at end of transfer channel priority ranking: 0 > 1 dmaor h'0001 9. direct memory access controller (dmac) rev.5.00 sep. 27, 2007 page 190 of 716 rej09b0398-0500 9.5 usage notes 1. other than the dma operation register (d maor) accessing in word (16 bit) units, access all registers in word (16 bit) or longword (32 bit) units. 2. when rewriting the rs0 to rs3 bits of chcr0, chcr1, first clear the de bit to 0 (set the de bit to 0 before doing rewrites with a chcr byte address). 3. when an nmi interrupt is input, the nmif bit of the dmaor is set even when the dmac is not operating. 4. set the dme bit of the dmaor to 0 and ma ke certain that any dmac received transfer request processing has been completed before entering standby mode. 5. do not access the dmac or bsc on-ch ip peripheral modules from the dmac. 6. when activating the dmac, do the chcr or dmaor setting as the final step. there are instances where abnormal operation will result if any other registers are established last. 7. after the dmatcr count becomes 0 and the dma transfer ends normally, always write a 0 to the dmatcr, even when execu ting the maximum number of transfers on the same channel. there are instances where abnormal ope ration will result if this is not done. 8. when detecting external requests by falling edge , maintain the external request pin at high level when performing the dmac establishment. 9. when operating in single address mode, establish an external address as the address. there are instances where abnormal operation will result if an internal address is established. 10. do not access dmac register empty addresses (h'ffff86b2 to h'ffff86bf, h'ffff86e4 to h'ffff86ff). operation cannot be guarant eed when empty addresses are accessed. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 191 of 716 rej09b0398-0500 section 10 multifunction timer pulse unit (mtu) 10.1 overview the superh microcomputer has an on-chip 16-bit multifunction timer pulse unit (mtu) with three channels of 16-bit timers. 10.1.1 features ? can process a maximum of eight different pulse outputs and inputs. ? has eight timer general registers (tgr): four fo r channel 0, and two each for channels 1 and 2 that can be set to function independently as output compare or input capture. the channel 0 tgrc and tgrd registers can be used as buffer registers. ? can select eight counter input clock sources for all channels ? all channels can be set for the following operating modes: ? compare match waveform output: 0 output/1 output/toggle output selectable. ? input capture function: select able rising edge, falling edge, or both rising and falling edge detection. ? counter clearing function: counters can be cleared by a compare-match or input capture. ? synchronizing mode: two or more timer counters (tcnt) can be written to simultaneously. two or more timer counters can be simultaneously cleared by a compare- match or input capture. counter synchronization functions enable synchronized register input/output. ? pwm mode: pwm output can be provided with any duty cycle. when combined with the counter synchronizing function, up to seven-phase pwm output is enabled (with channels 0 to 2 set to pwm mode 2 and channel 0 synchronized with the tgr0a register (channels 0 to 2 phase output: 3, 2, 2)). ? channels 0 can be set for buffer operation ? input capture register double buffer configuration possible ? output compare register au tomatic re-write possible ? channels 1, 2 can be independently set to the phase counting mode ? two-phase encoder pulse up/down count possible ? cascade connection operation ? can be operated as a 32-bit counter by using the channel 2 input clock for channel 1 overflow/underflow ? high speed access via internal 16-bit bus 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 192 of 716 rej09b0398-0500 ? thirteen interrupt sources ? channel 0 has four compare-match/input capture interrupts and one overflow interrupt which can be requested independently. ? channels 1 and 2 have two compare-match/input capture interrupts, one overflow interrupt, and one underflow interrupt which can be requested independently. ? automatic transfer of register data ? block transfer, 1-word data transfers and 1-byte data transfers are possible through dmac activation. ? a/d converter conversion start trigger can be generated ? channels 0 to 2 compare-match/input capture signals can be used as a/d converter conversion start triggers. table 10.1 summarizes the mtu functions. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 193 of 716 rej09b0398-0500 table 10.1 mtu functions item channel 0 channel 1 channel 2 counter clocks internal: / 1, /4, /16, /64, /256, /1024 external: eight to each channel from tclka, tclkb, tclkc, and tclkd general registers tgr0a tgr0b tgr1a tgr1b tgr2a tgr2b general registers/buffer registers tgr0c tgr0d no no input/output pins tioc0a tioc0b tioc0c tioc0d tioc1a tioc1b tioc2a tioc2b counter clear function tgr compare-match or input capture tgr compare-match or input capture tgr compare-match or input capture 0 yes yes yes compare match output 1 yes yes yes toggle yes yes yes input capture function yes yes yes synchronization yes yes yes buffer operation yes no no pwm mode 1 yes yes yes pwm mode 2 yes yes yes phase counting mode no yes yes dmac activation tgr0a compare match or input capture tgr1a compare match or input capture tgr2a compare match or input capture a/d conversion start trigger tgr0a com-pare match or input capture tgr1a com-pare match or input capture tgr2a com-pare match or input capture 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 194 of 716 rej09b0398-0500 item channel 0 channel 1 channel 2 interrupt sources compare match/input capture 0a compare match/input capture 1a compare match/input capture 2a compare match/input capture 0b compare match/input capture 1b compare match/input capture 2b compare match/input capture 0c overflow overflow compare match/input capture 0d underflow underflow overflow ? ? 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 195 of 716 rej09b0398-0500 10.1.2 block diagram figure 10.1 is the block diagram of the mtu. tcr channel 0 channel 1 channel 2 shared control lo g ic channels 0 to 2 control lo g ic tmdr tiorh tiorl tier tsr tcr tmdr tior tier tsr tcr tmdr tior tier tsr tstr tsyr tcnt bus i/f tgra tgrd tgrb tgrc tcnt tgra tgrb tcnt tgra tgrb (clock input) internal clock: /1 /4 /16 /64 /256 /1024 (i/o pins) channel 0: tioc0a tioc0b tioc0c tioc0d external clock: tclka tclkb tclkc tclkd channel 1: tioc1a tioc1b channel 2: tioc2a tioc2b internal data bus a/d conversion start request si g nal (interrupt request si g nal) channel 0: tgi0a tgi0b tgi0c tgi0d tgi0v channel 1: tgi1a tgi1b tgi1v tgi1u channel 2: tgi2a tgi2b tgi2v tgi2u module data bus figure 10.1 mtu block diagram 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 196 of 716 rej09b0398-0500 10.1.3 pin configuration table 10.2 summarizes the mtu pins. table 10.2 pin configuration channel name pin name i/o function shared clock input a tclka i clock a input pin (a-phase input pin in channel 1 phase counting mode) clock input b tclkb i clock b input pin (b-phase input pin in channel 1 phase counting mode) clock input c tclkc i clock c input pin (a-phase input pin in channel 2 phase counting mode) clock input d tclkd i clock d input pin (b-phase input pin in channel 2 phase counting mode) 0 input capture/output compare-match 0a tioc0a i/o tgr0a input capture input/output compare output/pwm output pin input capture/output compare-match 0b tioc0b i/o tgr0b input capture input/output compare output/pwm output pin input capture/output compare-match 0c tioc0c i/o tgr0c input capture input/output compare output/pwm output pin input capture/output compare-match 0d tioc0d i/o tgr0d input capture input/output compare output/pwm output pin 1 input capture/output compare-match 1a tioc1a i/o tgr1a input capture input/output compare output/pwm output pin input capture/output compare-match 1b tioc1b i/o tgr1b input capture input/output compare output/pwm output pin 2 input capture/output compare-match 2a tioc2a i/o tgr2a input capture input/output compare output/pwm output pin input capture/output compare-match 2b tioc2b i/o tgr2b input capture input/output compare output/pwm output pin note: the tioc pins output undefined values when they are set to input capture and timer output by the pin function controller (pfc). 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 197 of 716 rej09b0398-0500 10.1.4 register configuration table 10.3 summarizes the mtu register configuration. table 10.3 register configuration channel name abbrevi- ation r/w initial value address access size (bits) * 1 shared timer start register tstr r/w h'00 h'ffff8240 8, 16, 32 timer synchro register tsyr r/w h'00 h'ffff8241 0 timer control register 0 tcr0 r/w h'00 h'ffff8260 timer mode register 0 tmdr0 r/w h'c0 h'ffff8261 timer i/o control register 0h tior0h r/w h'00 h'ffff8262 timer i/o control register 0l tior0l r/w h'00 h'ffff8263 timer interrupt enable register 0 tier0 r/w h'40 h'ffff8264 timer status register 0 tsr0 r/(w) * 2 h'c0 h'ffff8265 timer counter 0 tcnt0 r/w h'0000 h'ffff8266 16, 32 general register 0a tgr0a r/w h'ffff h'ffff8268 general register 0b tgr0b r/w h'ffff h'ffff826a general register 0c tgr0c r/w h'ffff h'ffff826c general register 0d tgr0d r/w h'ffff h'ffff826e 1 timer control register 1 tcr1 r/w h'00 h'ffff8280 8, 16, 32 timer mode register 1 tmdr1 r/w h'c0 h'ffff8281 timer i/o control register 1 tior1 r/w h'00 h'ffff8282 timer interrupt enable register 1 tier1 r/w h'40 h'ffff8284 timer status register 1 tsr1 r/(w) * 2 h'c0 h'ffff8285 timer counter 1 tcnt1 r/w h'0000 h'ffff8286 16, 32 general register 1a tgr1a r/w h'ffff h'ffff8288 general register 1b tgr1b r/w h'ffff h'ffff828a 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 198 of 716 rej09b0398-0500 channel name abbrevi- ation r/w initial value address access size (bits) * 1 2 timer control register 2 tcr2 r/w h'00 h'ffff82a0 8, 16, 32 timer mode register 2 tmdr2 r/w h'c0 h'ffff82a1 timer i/o control register 2 tior2 r/w h'00 h'ffff82a2 timer interrupt enable register 2 tier2 r/w h'40 h'ffff82a4 timer status register 2 tsr2 r/(w) * 2 h'c0 h'ffff82a5 timer counter 2 tcnt2 r/w h'0000 h'ffff82a6 16, 32 general register 2a tgr2a r/w h'ffff h'ffff82a8 general register 2b tgr2b r/w h'ffff h'ffff82aa notes: do not access empty addresses. 1. 16-bit registers (tcnt, tgr) cannot be read or written in 8-bit units. 2. write 0 to clear flags. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 199 of 716 rej09b0398-0500 10.2 mtu register descriptions 10.2.1 timer control register (tcr) the tcr is an 8-bit read/write register for controlling the tcnt counter for each channel. the mtu has three tcr registers, one for each of the channels 0 to 2. tcr is initialized to h'00 by a power-on reset or the standby mode. channel 0: tcr0 bit: 7 6 5 4 3 2 1 0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w channels 1, 2: tcr1, tcr2 bit: 7 6 5 4 3 2 1 0 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 200 of 716 rej09b0398-0500 bits 7 to 5 ? counter clear 2 to 0 (cclr2 to cclr0): select the counter clear source for the tcnt counter. channels 0 bit 7 cclr2 bit 6 cclr1 bit 5 cclr0 description 0 0 0 tcnt clear disabled (initial value) 1 tcnt is cleared by tgra compare-match or input capture 1 0 tcnt is cleared by tgrb compare-match or input capture 1 synchronizing clear: tcnt is cleared in synchronization with clear of other channel counters operating in sync. * 1 1 0 0 tcnt clear disabled 1 tcnt is cleared by tgrc compare-match or input capture * 2 1 0 tcnt is cleared by tgrd compare-match or input capture * 2 1 synchronizing clear: tcnt is cleared in synchronization with clear of other channel counters operating in sync * 1 notes: 1. setting the sync bit of the tsyr to 1 sets the synchronization. 2. when tgrc or tgrd are functioning as buffer registers, tcnt is not cleared because the buffer registers have priority and co mpare-match/input captures do not occur. channels 1, 2 bit 7 reserved * 1 bit 6 cclr1 bit 5 cclr0 description 0 0 0 tcnt clear disabled (initial value) 1 tcnt is cleared by tgra compare-match or input capture 1 0 tcnt is cleared by tgrb compare-match or input capture 1 synchronizing clear: tcnt is cleared in synchronization with clear of other channel counters operating in sync * 2 notes: 1. the bit 7 of channels 1 and 2 is reserved. it always reads 0, and cannot be modified. 2. setting the sync bit of the tsyr to 1 sets the synchronization. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 201 of 716 rej09b0398-0500 bits 4 and 3 ? clock edge 1, 0 (ckeg1 and ckeg0): ckeg1 and ckeg0 select the input clock edges. when counting is done on both edges of the internal clock the input clock frequency becomes 1/2 (example: both edges of /4 = rising edge of /2 ). when phase count mode is used with channels 1, 2, these settings are ignored, as the phase count mode settings have priority. bit 4 ckeg1 bit 3 ckeg0 description 0 0 count on rising edges (initial value) 1 count on falling edges 1 x count on both rising and falling edges notes: 1. x: 0 or 1, don't care. 2. internal clock edge selection is effective when the input clock is /4 or slower. these settings are ignored when /1, or the overflow/underflow of another channel is selected for the input clock. bits 2 to 0 ? timer prescaler 2 to 0 (tpsc2 to tpsc0): tpsc2 to tpsc0 select the counter clock source for the tcnt. an inde pendent clock source can be se lected for each channel. table 10.4 shows the possible settings for each channel. table 10.4 mtu clock sources internal clock external clock channel /1 /4 / 16 / 64 / 256 / 1024 other channel overflow/ underflow tcl ka tcl kb tcl kc tcl kd 0 o o o o x x x o o o o 1 o o o o o x o o o x x 2 o o o o x o x o o o x note: symbols: o: setting possible x: setting impossible 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 202 of 716 rej09b0398-0500 channel 0 bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: count with /1 (initial value) 1 internal clock: count with /4 1 0 internal clock: count with /16 1 internal clock: count with /64 1 0 0 external clock: count with the tclka pin input 1 external clock: count with the tclkb pin input 1 0 external clock: count with the tclkc pin input 1 external clock: count with the tclkd pin input channel 1 bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: count with /1 (initial value) 1 internal clock: count with /4 1 0 internal clock: count with /16 1 internal clock: count with /64 1 0 0 external clock: count with the tclka pin input 1 external clock: count with the tclkb pin input 1 0 internal clock: count with /256 1 count with the tcnt2 overflow/underflow note: these settings are ineffective when channel 1 is in phase counting mode. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 203 of 716 rej09b0398-0500 channel 2 bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 internal clock: count with /1 (initial value) 1 internal clock: count with /4 1 0 internal clock: count with /16 1 internal clock: count with /64 1 0 0 external clock: count with the tclka pin input 1 external clock: count with the tclkb pin input 1 0 external clock: count with the tclkc pin input 1 internal clock: count with /1024 note: these settings are ineffective when channel 2 is in phase counting mode. 10.2.2 timer mode register (tmdr) the tmdr is an 8-bit r ead/write register that sets the operating mode for each channel. the mtu has three tmdr registers, one for each channel. tmdr is initialized to h'c0 by a power-on reset or the standby mode. channel 0: tmdr0 bit: 7 6 5 4 3 2 1 0 ? ? bfb bfa md3 md2 md1 md0 initial value: 1 1 0 0 0 0 0 0 r/w: r r r/w r/w r/w r/w r/w r/w channels 1, 2: tmdr1, tmdr2 bit: 7 6 5 4 3 2 1 0 ? ? ? ? md3 md2 md1 md0 initial value: 1 1 0 0 0 0 0 0 r/w: r r r r r/w r/w r/w r/w 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 204 of 716 rej09b0398-0500 bits 7 and 6 ? reserved: these bits always read as 1. the write value should always be 1. bit 5 ? buffer operation b (bfb): designates whether to use the tgrb register for normal operation, or buffer operation in combination with the tgrd register. when using tgrd as a buffer register, no tgrd register input capture/output compares are generated. this bit is reserved in channels 1 and 2, which have no tgrd registers. this bit always read as 0. the write value should always be 0. bit 5 bfb description 0 tgrb operates normally (initial value) 1 tgrb and tgrd buffer operation bit 4 ? buffer operation a (bfa): designates whether to use the tgra register for normal operation, or buffer operation in combination with the tgrc register. when using tgrc as a buffer register, no tgrc register input capture/output compares are generated. this bit is reserved in channels 1 and 2, which have no tgrc registers. this bit always read as 0. the write value should always be 0. bit 4 bfa description 0 tgra operates normally (initial value) 1 tgra and tgrc buffer operation 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 205 of 716 rej09b0398-0500 bits 3 to 0 ? modes 3 to 0 (md3 to md0): these bits set the timer operation mode. bit 3 md3 bit 2 md2 bit 1 md1 bit 0 md0 description 0 0 0 0 normal operation (initial value) 1 reserved (do not set) 1 0 pwm mode 1 1 pwm mode 2 1 0 0 phase counting mode 1 * 1 phase counting mode 2 * 1 0 phase counting mode 3 * 1 phase counting mode 4 * 1 0 0 0 reserved (do not set) 1 reserved (do not set) 1 0 reserved (do not set) 1 reserved (do not set) 1 0 0 reserved (do not set) 1 reserved (do not set) 1 0 reserved (do not set) 1 reserved (do not set) note: * phase measurement mode can not be set for channel 0. 10.2.3 timer i/o control register (tior) the tior is a register that controls the tgr. th e mtu has four tior registers, two for channels 0 and one each for channels 1 and 2. tior is in itialized to h'00 by a power-on reset or the standby mode. channel 0: tior0h channels 1, 2: tior1, tior2 bit: 7 6 5 4 3 2 1 0 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 206 of 716 rej09b0398-0500 bits 7 to 4 ? i/o control b3 to b0 (iob3 to iob0): these bits set the tgrb register function. bits 3 to 0 ? i/o control a3 to b0 (ioa3 to ioa0): these bits set the tgra register function. channel 0: tior0l bit: 7 6 5 4 3 2 1 0 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: when the tgrc or tgrd registers are set for buffer operation, these settings become ineffective and the operation is as a buffer register. bits 7 to 4 ? i/o control d3 to d0 (iod3 to iod0): these bits set the tgrd register function. bits 3 to 0 ? i/o control c3 to c0 (ioc3 to ioc0): these bits set the tgrc register function. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 207 of 716 rej09b0398-0500 channel 0 (tior0h register) bits 7 to 4 ? i/o control b3 to b0 (iob3 to iob0): these bits set the tgr0b register function. bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 description 0 0 0 0 output disabled (initial value ) 1 initial output is 0 output 0 on compare-match 1 0 output 1 on compare-match 1 tgr0b is an output compare register toggle output on compare-match 1 0 0 output disabled 1 initial output is 1 output 0 on compare-match 1 0 output 1 on compare-match 1 toggle output on compare-match 1 0 0 0 input capture on rising edge 1 input capture on falling edge 1 0 input capture on both edges 1 tgr0b is an input capture register capture input source is the tioc0b pin 1 0 0 1 input capture on tcnt1 count up/count down 1 0 capture input source is channel 1/ count clock 1 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 208 of 716 rej09b0398-0500 bits 3 to 0 ? i/o control a3 to a0 (ioa3 to ioa0): these bits set the tgr0a register function. bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 description 0 0 0 0 output disabled (initial value ) 1 initial output is 0 output 0 on compare-match 1 0 output 1 on compare-match 1 tgr0a is an output compare register toggle output on compare-match 1 0 0 output disabled 1 initial output is 1 output 0 on compare-match 1 0 output 1 on compare-match 1 toggle output on compare-match 1 0 0 0 input capture on rising edge 1 input capture on falling edge 1 0 input capture on both edges 1 tgr0a is an input capture register capture input source is the tioc0a pin 1 0 0 1 1 0 capture input source is channel 1/ count clock input capture on tcnt1 count up/count down 1 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 209 of 716 rej09b0398-0500 channel 0 (tior0l register) bits 7 to 4 ? i/o control d3 to d0 (iod3 to iod0): these bits set the tgr0d register function. bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 description 0 0 0 0 output disabled (initial value) 1 initial output is 0 output 0 on compare-match 1 0 output 1 on compare-match 1 tgr0d is an output compare register toggle output on compare-match 1 0 0 output disabled 1 initial output is 1 output 0 on compare-match 1 0 output 1 on compare-match 1 toggle output on compare-match 1 0 0 0 input capture on rising edge 1 capture input source is the tioc0d pin input capture on falling edge 1 0 input capture on both edges 1 tgr0d is an input capture register 1 0 0 1 input capture on tcnt1 count up/count down 1 0 capture input source is channel 1/ count clock 1 note: when the bfb bit of tmdr0 is set to 1 and tgr0d is being used as a buffer register, these settings become ineffective and input capture/output compares do not occur. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 210 of 716 rej09b0398-0500 bits 3 to 0 ? i/o control c3 to c0 (ioc3 to ioc0): these bits set the tgr0c register function. bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 description 0 0 0 0 output disabled (initial value ) 1 initial output is 0 output 0 on compare-match 1 0 output 1 on compare-match 1 tgr0c is an output compare register toggle output on compare-match 1 0 0 output disabled 1 initial output is 1 output 0 on compare-match 1 0 output 1 on compare-match 1 toggle output on compare-match 1 0 0 0 input capture on rising edge 1 capture input source is the tioc0c pin input capture on falling edge 1 0 input capture on both edges 1 tgr0c is an input capture register 1 0 0 1 1 0 capture input source is channel 1/ count clock input capture on tcnt1 count up/count down 1 note: when the bfa bit of tmdr0 is set to 1 and tgr0c is being used as a buffer register, these settings become ineffective and input capture/output compares do not occur. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 211 of 716 rej09b0398-0500 channel 1 (tior1 register) bits 7 to 4 ? i/o control b3 to b0 (iob3 to iob0): these bits set the tgr1b register function. bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 description 0 0 0 0 output disabled (initial value ) 1 initial output is 0 output 0 on compare-match 1 0 output 1 on compare-match 1 tgr1b is an output compare register toggle output on compare-match 1 0 0 output disabled 1 initial output is 1 output 0 on compare-match 1 0 output 1 on compare-match 1 toggle output on compare-match 1 0 0 0 input capture on rising edge 1 input capture on falling edge 1 0 capture input source is the tioc1b pin input capture on both edges 1 tgr1b is an input capture register 1 0 0 1 1 0 input capture on channel 0/tgr0c compare-match/input capture generation 1 capture input source tgr0c compare/match input capture 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 212 of 716 rej09b0398-0500 bits 3 to 0 ? i/o control a3 to a0 (ioa3 to ioa0): these bits set the tgr1a register function. bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 description 0 0 0 0 output disabled (initial value ) 1 initial output is 0 output 0 on compare-match 1 0 output 1 on compare-match 1 tgr1a is an output compare register toggle output on compare-match 1 0 0 output disabled 1 initial output is 1 output 0 on compare-match 1 0 output 1 on compare-match 1 toggle output on compare-match 1 0 0 0 input capture on rising edge 1 input capture on falling edge 1 0 capture input source is the tioc1a pin input capture on both edges 1 tgr1a is an input capture register 1 0 0 1 1 0 1 capture input source is tgr0a compare- match/input capture input capture on channel 0/tgr0a compare-match/input capture generation 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 213 of 716 rej09b0398-0500 channel 2 (tior2 register) bits 7 to 4 ? i/o control b3 to b0 (iob3 to iob0): these bits set the tgr2b register function. bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 description 0 0 0 0 output disabled (initial value ) 1 initial output is 0 output 0 on compare-match 1 0 output 1 on compare-match 1 tgr2b is an output compare register toggle output on compare-match 1 0 0 output disabled 1 initial output is 1 output 0 on compare-match 1 0 output 1 on compare-match 1 toggle output on compare-match 1 0 0 0 input capture on rising edge 1 input capture on falling edge 1 0 capture input source is the tioc2b pin input capture on both edges 1 tgr2b is an input capture register 1 0 0 input capture on rising edge 1 input capture on falling edge 1 0 input capture on both edges 1 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 214 of 716 rej09b0398-0500 bits 3 to 0 ? i/o control a3 to a0 (ioa3 to ioa0): these bits set the tgr2a register function. bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 description 0 0 0 0 output disabled (initial value ) 1 initial output is 0 output 0 on compare-match 1 0 output 1 on compare-match 1 tgr2a is an output compare register toggle output on compare-match 1 0 0 output disabled 1 initial output is 1 output 0 on compare-match 1 0 output 1 on compare-match 1 toggle output on compare-match 1 0 0 0 input capture on rising edge 1 input capture on falling edge 1 0 capture input source is the tioc2a pin input capture on both edges 1 tgr2a is an input capture register 1 0 0 input capture on rising edge 1 input capture on falling edge 1 0 input capture on both edges 1 10.2.4 timer interrupt enable register (tier) the tier is an 8-bit register that controls the enable/disable of interrupt requests for each channel. the mtu has three tier registers, one each for ch annel. tier is initialized to h'40 by a reset or by standby mode. channel 0: tier0 bit: 7 6 5 4 3 2 1 0 ttge ? ? tciev tgied tgiec tgieb tgiea initial value: 0 1 0 0 0 0 0 0 r/w: r/w r r r/w r/w r/w r/w r/w 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 215 of 716 rej09b0398-0500 channels 1, 2: tier1, tier2 bit: 7 6 5 4 3 2 1 0 ttge ? tcieu tciev ? ? tgieb tgiea initial value: 0 1 0 0 0 0 0 0 r/w: r/w r r/w r/w r r r/w r/w bit 7 ? a/d conversion start request enable (ttge): enables or disables generation of an a/d conversion start request by a tgra register input capture/compare-match. bit 7 ttge description 0 disable a/d conversion start requests (initial value) 1 enable a/d conversion start request generation bit 6 ? reserved: this bit always read as 1. the write value should always be 1. bit 5 ? underflow interrupt enable (tcieu): enables or disables interrupt requests when the underflow flag (tcfu) of the channel 1, 2 timer status register (tsr) is set to 1. this bit is reserved for channel 0. it always reads as 0. the write value should always be 0. bit 5 tcieu description 0 disable udf interrupt requests (tciu) (initial value) 1 enable udf interrupt requests (tciu) bit 4 ? overflow interrupt enable (tciev): enables or disables interrupt requests when the overflow flag tcfv of the timer status register (tsr) is set to 1. bit 4 tciev description 0 disable tcfv interrupt requests (tciv) (initial value) 1 enable tcfv interrupt requests (tciv) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 216 of 716 rej09b0398-0500 bit 3 ? tgr interrupt enable d (tgied): enables or disables interrupt tgfd requests when the tgfd bit of the channel 0 tsr register is set to 1. this bit is reserved for channels 1 and 2. it always reads as 0. the write value should always be 0. bit 3 tgied description 0 disable interrupt requests (tgid) due to the tgfd bit (initial value) 1 enable interrupt requests (tgid) due to the tgfd bit bit 2 ? tgr interrupt enable c (tgiec): enables or disables tgfc interrupt requests when the tgfc bit of the channel 0 tsr register is set to 1. this bit is reserved for channels 1 and 2. it always reads as 0. the write value should always be 0. bit 2 tgiec description 0 disable interrupt requests (tgic) due to the tgfc bit (initial value) 1 enable interrupt requests (tgic) due to the tgfc bit bit 1 ? tgr interrupt enable b (tgieb): enables or disables tgfb interrupt requests when the tgfb bit of the tsr register is set to 1. bit 1 tgieb description 0 disable interrupt requests (tgib) due to the tgfb bit (initial value) 1 enable interrupt requests (tgib) due to the tgfb bit bit 0 ? tgr interrupt enable a (tgiea): enables or disables tgfa interrupt requests when the tgfa bit of the tsr register is set to 1. bit 0 tgiea description 0 disable interrupt requests (tgia) due to the tgfa bit (initial value) 1 enable interrupt requests (tgia) due to the tgfa bit 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 217 of 716 rej09b0398-0500 10.2.5 timer status register (tsr) the timer status register (tsr) is an 8-bit regist er that indicates the status of each channel. the mtu has three tsr registers, one each for channel. tsr is initialized to h'c0 by a power-on reset or by standby mode. channel 0: tsr0 bit: 7 6 5 4 3 2 1 0 ? ? ? tcfv tgfd tgfc tgfb tgfa initial value: 1 1 0 0 0 0 0 0 r/w: r r r r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * only 0 writes to clear the flags are possible. channels 1, 2: tsr1, tsr2 bit: 7 6 5 4 3 2 1 0 tcfd ? tcfu tcfv ? ? tgfb tgfa initial value: 1 1 0 0 0 0 0 0 r/w: r r r/(w) * r/(w) * r r r/(w) * r/(w) * note: * only 0 writes to clear the flags are possible. bit 7 ? count direction flag (tcfd): this status flag indicates the count direction of the channel 1, 2 tcnt counters. this bit is reserved in channel 0. this bit always reads as 1. the write value should always be 1. bit 7 tcfd description 0 tcnt counts down 1 tcnt counts up (initial value) bit 6 ? reserved: this bit always reads as 1. the write value should always be 1. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 218 of 716 rej09b0398-0500 bit 5 ? underflow flag (tcfu): this status flag indicates th e occurrence of a channel 1, 2 tcnt counter underflow. this bit is reserved in channel 0. this bit always reads as 0. the write value should always be 0. bit 5 tcfu description 0 clear condition: with tcfu = 1, a 0 write to tcfu after reading it (initial value) 1 set condition: when the tcnt value underflows (h'0000 h'ffff) bit 4 ? overflow flag (tcfv): this status flag indicates th e occurrence of a tcnt counter overflow. bit 4 tcfv description 0 clear condition: with tcfv = 1, a 0 write to tcfv after reading it (initial value) 1 set condition: when the tcnt value overflows (h'ffff h'0000) bit 3 ? input capture/output compare flag d (tgfd): this status flag indicates the occurrence of a channel 0 tgrd register input capture or compare-match. this bit is reserved in channels 1 and 2. it always reads as 0. the write value should always be 0. bit 3 tgfd description 0 clear condition: with tgfd = 1, a 0 write to tgfd following a read (initial value) 1 set conditions: ? when tgrd is functioning as an output compare register (tcnt = tgrd) ? when tgrd is functioning as input capture (the tcnt value is sent to tgrd by the input capture signal) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 219 of 716 rej09b0398-0500 bit 2 ? input capture/output compare flag c (tgfc): this status flag indicates the occurrence of a channel 0 tgrc register input capture or compare-match. this bit is reserved for channels 1 and 2. it always reads as 0. the write value should always be 0. bit 2 tgfc description 0 clear condition: with tgfc = 1, a 0 write to tgfc following a read (initial value) 1 set conditions: ? when tgrc is functioning as an output compare register (tcnt = tgrc) ? when tgrc is functioning as input capture (the tcnt value is sent to tgrc by the input capture signal) bit 1 ? input capture/output compare flag b (tgfb): this status flag indicates the occurrence of a tgrb register input capture or compare-match. bit 1 tgfb description 0 clear condition: with tgfb = 1, a 0 write to tgfb following a read (initial value) 1 set conditions: ? when tgrb is functioning as an output compare register (tcnt = tgrb) ? when tgrb is functioning as input capture (the tcnt value is sent to tgrb by the input capture signal) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 220 of 716 rej09b0398-0500 bit 0 ? input capture/output compare flag a (tgfa): this status flag indicates the occurrence of a tgra register input capture or compare-match. bit 0 tgfa description 0 clear condition: with tgfa = 1, a 0 write to tgfa following a read (cleared by dmac transfer due to tgfa) (initial value) 1 set conditions: ? when tgra is functioning as an output compare register (tcnt = tgra) ? when tgra is functioning as input capture (the tcnt value is sent to tgra by the input capture signal) 10.2.6 timer counters (tcnt) the timer counters (tcnt) are 16-bit counters, w ith one for each channel, for a total of three. the tcnt are initialized to h'0000 by a power-on re set and when in standby mode. accessing the tcnt counters in 8-bit units is prohi bited. always access in 16-bit units. channel abbreviation function 0 tcnt0 increment counter 1 tcnt1 increment/decrement counter * 2 tcnt2 increment/decrement counter * note: * can only be used as an increment/decrement counter in phase counting mode, with other channel overflow/underflow counting. it becomes an increment counter in all other cases. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 221 of 716 rej09b0398-0500 10.2.7 timer general register (tgr) each timer general register (tgr) is a 16-bit regist er that can function as either an output compare register or an input capture register. there are a total of eight tgr, four for channel 0, and two each for channels 1 and 2. the tgrc and tgrd of channel 0 can be set to operate as buffer registers. the tgr register and buffer register combinations are tgra with tgrc, and tgrb with tgrd. the tgrs are initialized to h' ffff by a power-on reset or in standby mode. accessing of the tgrs in 8-bit units is disabled; th ey may only be accessed in 16-bit units. bit: 15 14 13 12 11 10 9 8 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 10.2.8 timer start register (tstr) the timer start register (tstr) is an 8-bit read/write register that starts and stops the timer counters (tcnt) of channels 0 to 2. tstr is initialized to h'00 upon power-on reset or standby mode. bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? cst2 cst1 cst0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 222 of 716 rej09b0398-0500 bits 2 to 0 ? counter start 4 to 0 (cst4 to cst0): select the start and stop of the timer counters (tcnt). the counter start to channel and bit to channel correspondence are indicated in the tables below. counter start channel cst2 channel 2 (tcnt2) cst1 channel 1 (tcnt1) cst0 channel 0 (tcnt0) bit n cstn description 0 tcntn count is halted (initial value) 1 tcntn counts note: n = 2 to 0. if 0 is written to the cst bit during operation with the tioc pin in output status, the counter stops, but the tioc pin output compare output level is maintained. if a write is done to the tior register while the cst bit is a 0, the pin output level is updated to the established initial output value. bits 7 to 3 ? reserved: these bits always read as 0. the write value should always be 0. 10.2.9 timer synchro register (tsyr) the timer synchro register (tsyr) is an 8-bit read/write register that selects independent or synchronous tcnt counter operation for channels 0 to 2. channels for which 1 is set in the corresponding bit will be synchronized. tsyr is initialized to h'00 upon power-on reset or standby mode. bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? sync2 sync1 sync0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 223 of 716 rej09b0398-0500 bits 2 to 0 ? timer synchronization 2 to 0 (sync2 to sync0): selects operation independent of, or synchronized to, other channels. synchron ous operation allows synchronous clears due to multiple tcnt synchronous presets and other channel counter clears. a minimum of two channels must have sync bits set to 1 for synchronous operation. for synchronization clearing, it is necessary to set the tcnt counter clear sources (the cclr2 to cclr0 bits of the tcr register), in addition to the sync bit. the counter start to channel and bit-to-channel correspondence are indicated in the tables below. counter start channel sync2 channel 2 (tcnt2) sync1 channel 1 (tcnt1) sync0 channel 0 (tcnt0) bit n syncn description 0 timer counter (tcntn) independent operation (initial value) (tcntn preset/clear unrelated to other channels) 1 timer counter synchronous operation * 1 tcntn synchronous preset/ synchronous clear * 2 possible notes: n = 2 to 0. 1. minimum of two channel sync bits must be set to 1 for synchronous operation. 2. tcnt counter clear sources (cclr2 to cclr0 bits of the tcr register) must be set in addition to the sync bit in order to have clear synchronization. bits 7 to 3 ? reserved: these bits always read as 0. the write value should always be 0. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 224 of 716 rej09b0398-0500 10.3 bus master interface 10.3.1 16-bit registers the timer counters (tcnt) and general registers (tgr) are 16-bit registers. a 16-bit data bus to the bus master enables 16-bit read /writes. 8-bit read/write is not possible. always access in 16-bit units. figure 10.2 shows an example of 16-bit register access operation. tcnth tcntl bus interface upper 8 bits lower 8 bits bus master internal data bus module data bus figure 10.2 16-bit register access operation (bus master ? tcnt (16 bit)) 10.3.2 8-bit registers all registers other than the tcnt and general registers (tgr) are 8-bit registers. these are connected to the cpu by a 16-bit data bus, so 16-bit read/writes and as 8-bit read/writes are both possible (figures 10.3 to 10.5). tcr bus interface upper 8 bits lower 8 bits bus master internal data bus module data bus figure 10.3 8-bit register access operation (bus master ? tcr (upper 8 bits)) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 225 of 716 rej09b0398-0500 tmdr bus interface upper 8 bits lower 8 bits bus master internal data bus module data bus figure 10.4 8-bit register access operation (bus master ? tmdr (lower 8 bits)) tcr tmdr bus interface upper 8 bits lower 8 bits bus master internal data bus module data bus figure 10.5 8-bit register access operation (bus master ? tcr, tmdr (16 bit)) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 226 of 716 rej09b0398-0500 10.4 operation 10.4.1 overview the operation modes are described below. ordinary operation: each channel has a timer counter (tcnt) and general register (tgr). the tcnt is an upcounter and can also operate as a free-running counter, periodic counter or external event counter. general registers (tgr) can be used as output compare registers or input capture registers. synchronized operation: the tcnt of a channel set for synchronized operation does a synchronized preset. when any tcnt of a channel operating in the synchronized mode is rewritten, the tcnts of other channels are simultaneously rewritten as well. the timer synchronization bits of the tsyr registers of mu ltiple channels set for synchronous operation can be set to clear the tcnts simultaneously. buffer operation: when tgr is an output compare regist er, the buffer register value of the corresponding channel is transferred to the tgr when a compare-match occurs. when tgr is an input capture register, the tcnt counter value is transferred to the tgr when an input capture occur simultaneously the value previously stored in the tgr is transferred to the buffer register. cascade connection operation : the channel 1 and channel 2 counters (tcnt1 and tcnt2) can be connected together to operate as a 32-bit counter. pwm mode: in pwm mode, a pwm waveform is output. the output level can be set by the tior register. each tgr can be set for pwm waveform output with a duty cycle between 0 % and 100 % . phase counting mode: in phase counting mode, the phase differential between two clocks input from the channel 1 and channel 2 external clock input pins is detected and the tcnt counter operates as an up/down counter. in phase counting mode, the corresponding tclk pins become clock inputs and tcnt functions as an up/down counter. it can be used as a two-phase encoder pulse input. 10.4.2 basic functions always select mtu external pin set function using the pin function controller (pfc). counter operation: when a start bit (cst0 to cst2) in the timer start register (tstr) is set to 1, the corresponding timer counter (tcnt) starts counting. there are two counting modes: a free- running mode and a periodic mode. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 227 of 716 rej09b0398-0500 to select the counting operation (figure 10.6): 1. set bits tpsc2 to tpsc0 in the tcr to select the counter clock. at the same time, set bits ckeg1 and ckeg0 in the tcr to select the desired edge of the input clock. 2. to operate as a periodic counter, set the cclr2 to cclr0 bits in the tcr to select tgr as a clearing source for the tcnt. 3. set the tgr selected in step 2 as an outpu t compare register using the timer i/o control register (tior). 4. write the desired cycle value in the tgr selected in step 2. 5. set the cst bit in the tstr to 1 to start counting. counting mode selection select counter clock periodic counter select counter clear source select output compare register set period start counting start counting free-running counter periodic counter free-running counter 5 5 4 3 2 1 figure 10.6 procedure for se lecting the counting operation free-running counter operation example: a reset of the mtu timer counters (tcnt) leaves them all in the free-running mode. when a bit in the tstr is set to 1, the corresponding timer counter operates as a free-running counter and begins to increment. when the count overflows from h'ffff to h'0000, the tcfv bit in the timer status register (tsr ) is set to 1. if the tciev bit in the timer's corresponding tim er interrupt enable register (t ier) is set to 1, the mtu will make an interrupt request to the interrupt controller. after the tcnt overflows, counting continues from h'0000. figure 10.7 shows an example of free-running counter operation. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 228 of 716 rej09b0398-0500 cst bit tcnt value time h'ffff h'0000 tcfv figure 10.7 free-running counter operation periodic counter op eration example: periodic counter operation is obtained for a given channel's tcnt by selecting compare-match as a tcnt clear source. set the tgr register for period setting to output compare register and select counter clear upon compare-match using the cclr2 to cclr0 bits of the timer control register (tcr). after these settings, the tcnt begins incrementing as a periodic counter when the corresponding bit of tstr is set to 1. when the count matches the tgr register value, the tgf bit in the tsr is set to 1 and the counter is cleared to h'0000. if the tgie bit of the corresponding tier is set to 1 at this point, the mtu will make an interrupt request to the interrupt controller. after the compare-match, tcnt continues counting from h'0000. figure 10.8 shows an example of periodic counting. cst bit tcnt value time counter cleared by tgr compare match tgr h'0000 tgf flag cleared by software or dmac activation figure 10.8 period ic counter operation 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 229 of 716 rej09b0398-0500 compare-match waveform output function: the mtu can output 0 level, 1 level, or toggle output from the corresponding output pins upon compare-matches. procedure for selecting the compare-match waveform output operation (figure 10.9): 1. set the tior to select 0 output or 1 output for the initial value, and 0 output, 1 output, or toggle output for compare-match output. the tioc pin will output the set initial value until the first compare-match occurs. 2. set a value in the tgr to select the compare-match timing. 3. set the cst bit in the tstr to 1 to start counting. output selection select waveform output mode select output timing start counting 1 2 3 figure 10.9 procedure for selecting compare match w aveform output operation 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 230 of 716 rej09b0398-0500 waveform output operation (0 output/1 output): figure 10.10 shows 0 output/1 output. in the example, tcnt is a free-running counter, 1 is output upon compare-match a and 0 is output upon compare-match b. when the pin level matches the set level, the pin level does not change. h'ffff h'0000 tioca tcnt value time tgra tgrb tiocb does not change does not change 1 output does not change does not change 0 output figure 10.10 example of 0 output/1 output waveform output operation (toggle output): figure 10.11 shows the toggle output. in the example, the tcnt operates as a periodic count er cleared by compare-match b, with toggle output at both compare-match a and compare-match b. h'ffff h'0000 tioca tcnt value counter cleared by tgrb compare match time tgrb tgra tiocb toggle output toggle output figure 10.11 example of toggle output 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 231 of 716 rej09b0398-0500 input capture function: in the input capture mode, the tcnt value is transferred into the tgr register when the input edge is detected at the input capture/output compare pin (tioc). detection can take place on the rising edge, falling edge, or both edges. channels 0 and 1 can use other channel counter input clocks or compare-match signals as input capture sources. the procedure for selecting the input capture operation (figure 10.12) is: 1. set the tior to select the input capture function of the tgr, then select the input capture source, and rising edge, falling edge, or both edges as the input edge. 2. set the cst bit in the tstr to 1 to start the tcnt counting. input selection select input-capture input start counting input capture operation 1 2 figure 10.12 procedure for se lecting input ca pture operation 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 232 of 716 rej09b0398-0500 input capture operation: figure 10.13 shows input capture. the falling edge of tiocb and both edges of tioca are selected as input capture input edges. in the example, tcnt is set to clear at the input capture of the tgrb register. counter cleared by tiocb input (falling edge) tcnt value h'0180 h'0160 h'0005 h'0010 h'0000 tiocb tioca tgra tgrb h'0005 h'0160 h'0010 h'0180 time figure 10.13 input capture operation 10.4.3 synchronous operation in the synchronizing mode, two or more timer counters can be rewritten simultaneously (synchronized preset). multiple timer counters can also be cleared simultaneously using tcr settings (synchronized clear). the synchronizing mode can increase the number of tgr registers for a single time base. all three channels can be set for synchronous operation. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 233 of 716 rej09b0398-0500 procedure for selecting the sync hronizing mode (figure 10.14): 1. set 1 in the sync bit of the timer synchro register (tsyr) to use the corresponding channel in the synchronizing mode. 2. when a value is written in the tcnt in any of the synchronized channels, the same value is simultaneously written in the tcnt in the other channels. 3. set the counter to clear with output compare/input capture using bits cclr2 to cclr0 in the tcr. 4. set the counter clear source to synchronized clear using the cclr2 to cclr0 bits of the tcr. 5. set the cst bits for the corresponding channels in the tstr to 1 to start counting in the tcnt. select counter clear source channel that generated clear source? no yes select synchronizing mode set synchronizing mode synchronized preset set tcnt start counting set counter synchronous clear start counting counter clear synchronized clear synchronized preset synchronized clear 1 2 3 5 4 5 figure 10.14 procedure for selecting synchronizing operation 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 234 of 716 rej09b0398-0500 synchronized operation: figure 10.15 shows an example of synchronized operation. channels 0, 1, and 2 are set to synchronized operation and pwm mode 1. channel 0 is set for a counter clear upon compare-match with tgr0b. channels 1 and 2 are set for synchronous counter clears by synchronous presets and tgr0b register compare-matches. accordingly, a three-phase pwm waveform with the data set in the tgr0b register as its pwm period is output from the tioc0a, tioc1a, and tioc2a pins. see section 10.4.6, pwm mode, for details on the pwm mode. tcnt0 to tcnt2 values time tioc0a synchronized clear on tgr0b compare match tgr0b tgr1b tgr0a tgr2b tgr1a tgr2a h'0000 tioc1a tioc2a figure 10.15 synchronized operation example 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 235 of 716 rej09b0398-0500 10.4.4 buffer operation buffer operation is a function of channels 0, 3, and 4. tgrc and tgrd can be used as buffer registers. table 10.5 shows the register combinations for buffer operation. table 10.5 register combinations channel general register buffer register 0 tgr0a tgr0c tgr0b tgr0d the buffer operation differs, depending on whether the tgr has been set as an input capture register or an output compare register. when tgr is an output compare register: when a compare-match occurs, the corresponding channel buffer register value is transferred to th e general register. figure 10.16 shows an example. compare match signal buffer register tcnt comparator general register figure 10.16 compare match buffer operation when tgr is an input capture register: when an input capture occurs, the timer counter (tcnt) value is transferred to the general register (tgr), and the value that had been held up to that time in the tgr is transferred to the buffer register (figure 10.17). input capture signal tcnt buffer register general register figure 10.17 input capture buffer operation 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 236 of 716 rej09b0398-0500 procedure for setting buffer mode (figure 10.18): 1. use the timer i/o control register (tior) to set the tgr as either an input capture or output compare register. 2. use the timer mode register (tmdr) bfa, and bfb bits to set the tgr for buffer mode. 3. set the cst bit in the tstr to 1 to start the count operation. 1 2 3 select tgr function buffer mode select buffer mode start counting buffer mode figure 10.18 buffer operation setting procedure buffer operation examples ? when tgr is an output compare register: figure 10.19 shows an example of channel 0 set to pwm mode 1, and the tgra and tgrc registers set for buffer operation. the tcnt counter is cleared by a compare-match b, and the output is a 1 upon compare-match a and 0 output upon compare-match b. because bu ffer mode is selected, a compare-match a changes the output, and the buffer register tgrc value is simultaneously transferred to the general register tgra. this operation is repeat ed with each occurrence of a compare-match a. see section 10.4.6, pwm mode, for details on the pwm mode. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 237 of 716 rej09b0398-0500 tgr0b tgr0a h'0000 tgr0c tgr0a tioc0a h'0450 h'0520 h'0200 h'0450 h'0520 h'0200 tcnt value time transfer h'0450 h'0200 figure 10.19 buffer operation e xample (output compare register) buffer operation examples ? when tgr is an input capture register: figure 10.20 shows an example of tgra set as an input capture register with the tgra and tgrc registers set for buffer operation. the tcnt counter is cleared by a tgra register input capture, and the tioca pin input capture input edge is selected as both rising and falling edge. because buffer mode is selected, an input capture a causes the tcnt counter value to be stored in the tgra register, and the value that was stored in the tgra up until that time is simultaneously transferred to the tgrc register. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 238 of 716 rej09b0398-0500 h'0f07 h'09fb h'0532 h'0000 tgra tgrc tioc0a h'0532 h'09fb h'0f07 tcnt value time h'0f07 h'0532 figure 10.20 buffer operation e xample (input capture register) 10.4.5 cascade connection mode cascade connection mode is a function that connects the 16-bit counters of two channels together to act as a 32-bit counter. this function operates by using the tpsc2 to tpsc0 bits of the tcr register to set the channel 1 counter clock to count by tcnt2 counter overflow/underflow. note: when channel 1 is set to phase counting mode, the counter clock settings become ineffective. table 10.6 shows the cascade connection combinations. table 10.6 cascade connection combinations combination upper 16 bits lower 16 bits channel 1, channel 2 tcnt1 tcnt2 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 239 of 716 rej09b0398-0500 procedure for setting cascade connection mode (figure 10.21): 1. set the tpsc2 to tpsc 0 bits of the channel 1 timer control register (tcr) to b'111 to select ?count by tcnt2 overflow/underflow.? 2. set the cst bits corresponding to the upper and lower 16 bits in the tstr to 1 to start the count operation. cascade connection operation select cascade connection start counting cascade connection operation 1 2 figure 10.21 procedure for se lecting cascade connection mode cascade connection operation examples ? phase counting mode: figure 10.22 shows an example of operation when the tcnt1 counter is set to count on tcnt2 overflow/underflow and channel 2 is set to phase counting mode. the tcnt1 counter increments with a tcnt2 counter overflow and decrements with a tcnt2 underflow. tclka tclkb tcnt2 fffd ffff ffff fffe 0000 0001 0001 0000 0002 tcnt1 0000 0000 0001 figure 10.22 cascade connection operation example (phase counting mode) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 240 of 716 rej09b0398-0500 10.4.6 pwm mode pwm mode outputs the various pwm waveforms from output pins. output levels of 0 output, 1 output, or toggle output can be selected as the output level for the compare-match of each tgr. a period can be set for a register by using the tg r compare-match as a counter clear source. all channels can be independently set to pwm m ode. synchronous operation is also possible. there are two pwm modes: ? pwm mode 1 generates pwm output using the tgra and tgrb registers, and tgrc and tgrd registers as pairs. the initial output values are those established in the tgra and tgrc registers. when the values set in tgr registers being used as a pair are equal, output values will not change even if a compare-match occurs. a maximum of four-phase pwm output is possible for pwm mode 1. ? pwm mode 2 generates pwm output using one tgr register as a period register and another as a duty cycle register. the output value of each pin upon a counter clear is the initial value established by the tior register. when the values set in the period register and duty register are equal, output values will not change even if a compare-match occurs. table 10.7 lists the combinations of pwm output pins and registers. table 10.7 combinations of pwm output pins and registers output pin channel register pwm mode 1 pwm mode 2 0 (ab pair) tgr0a tgr0b tioc0a tioc 0a tioc 0b 0 (cd pair) tgr0c tgr0d tioc0c tioc 0c tioc 0d 1 tgr1a tgr1b tioc1a tioc 1a tioc 1b 2 tgr2a tgr2b tioc2a tioc 2a tioc 2b note: pwm output of the period setting tgr is not possible in pwm mode 2. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 241 of 716 rej09b0398-0500 procedure for selecting th e pwm mode (figure 10.23): 1. set bits tpsc2 to tpsc0 in the tcr to select the counter clock source. at the same time, set bits ckeg1 and ckeg0 in the tcr to select the desired edge of the input clock. 2. set bits cclr2 to cclr0 in the tcr to select the tgr to be used as a counter clear source. 3. set the period in the tgr selected in step 2, and the duty cycle in another tgr. 4. using the timer i/o control register (tior), set the tgr selected in step 3 to act as an output compare register, and select the initial value and output value. 5. set the md3 to md 0 bits in tmdr to select the pwm mode. 6. set the cst bit in the tstr to 1 to let the tcnt start counting. 1 2 3 4 5 6 pwm mode select counter clock select waveform output level set tgr select pwm mode start counting pwm mode select counter clear source figure 10.23 procedure fo r selecting the pwm mode 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 242 of 716 rej09b0398-0500 pwm mode operation examples ? pwm mode 1 (figure 10.24): a tgra register compare- match is used as a tcnt counte r clear source, the tgra register initial output value and output compare output value are both 0, and the tgrb register output compare output value is a 1. in this example, the value established in the tg ra register becomes the period and the value established in the tgrb regist er becomes the duty cycle. counter cleared by tgra compare match tcnt value tgra tgrb h'0000 tioca time figure 10.24 pwm mode operation example (mode 1) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 243 of 716 rej09b0398-0500 pwm mode operation examples ? pwm mode 2 (figure 10.25): channels 0 and 1 are set for synchronous operation, tgr1b register compare-match is used as a tcnt counter clear source, the other tgr register initial output value is 0 and output compare output value is 1, and a 5-phase pwm waveform is output. in this example, the value established in the tgr1b register becomes the period and the value established in the other tgr register becomes the duty cycle. tgr0a tgr0b tgr0c tgr0d tgr1a tgr1b tcnt value time h'0000 tioc0a tioc0b tioc0c tioc0d tioc1a counter cleared on tgr1b compare match figure 10.25 pwm mode operation example (mode 2) 0 % duty cycle: figure 10.26 shows an example of a 0 % duty cycle pwm waveform output in pwm mode. tgra tcnt value tgrb rewrite tgrb tioca time 0 % duty cycle tgrb rewrite tgrb rewrite figure 10.26 pwm mode operation example (0 % duty cycle) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 244 of 716 rej09b0398-0500 100 % duty cycle: figure 10.27 shows an example of a 100 % duty cycle pwm waveform output in pwm mode. in pwm mode, when setting cycle = duty cycle the output waveform does not change, nor is there a change of waveform for the first pulse immediately after clearing the counter. tgra tcnt value tgrb rewrite tgrb tioca tioca time time 100 % duty cycle output does not change if period register and duty cycle register compare matches occur simultaneously output does not change if period register and duty cycle register compare matches occur simultaneously tgrb rewrite tgrb rewrite tgra tcnt value tgrb rewrite tgrb tgrb rewrite 100 % duty cycle 0 % duty cycle tgrb rewrite figure 10.27 pwm mode operation example (100 % duty cycle) 10.4.7 phase counting mode the phase counting mode detects the phase differential of two external clock inputs and counts the tcnt counter up or down. this mode can be set for channels 1 and 2. when set in the phase counting mode, an external clock is selected for the counter input clock, regardless of the settings of the tpsc2 to tpsc0 bits of tcr or the ckeg1 and ckeg0 bits. tcnt also becomes an up/down counter. since the tcr cclr1/cclr0 bits, tior, tier, and tgr functions are all enabled, input capture and compare-match functions and interrupt sources can be used. when the tcnt counter is incrementing, an overflow sets the tsr register tcfv (overflow flag). when it is decrementing, an underflow sets the tcfu (underflow flag). 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 245 of 716 rej09b0398-0500 the tsr register tcfd bit is a count direction flag. read the tcfd flag to confirm whether the tcnt is incrementing or decrementing. table 10.8 shows the correspondence between channels and external clock pins. table 10.8 phase counting mode clock input pins channel a phase input pin b phase input pin 1 tclka tclkb 2 tclkc tclkd procedure for selecting the phase counting mode (figure 10.28): 1. set the md3 to md0 bits of the timer mode register (tmdr) to select the phase counting mode. 2. set the cst bit of the timer start register (tstr) to 1 to start the count. phase counting mode select phase counting mode start counting phase counting mode 1 2 figure 10.28 procedure for se lecting the phase counting mode phase counting operation examples: the phase counting mode uses the phase difference between two external clocks to increment/decrement the tcnt counter. there are 4 modes, depending on the count conditions. phase counting mode 1: figure 10.29 shows an example of phase counting mode 1 operation. table 10.9 lists the up counting and down counting conditions for the tcnt. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 246 of 716 rej09b0398-0500 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) tcnt value time increment decrement figure 10.29 phase counting mode 1 operation table 10.9 phase count mode 1 up/down counting conditions tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation 1 (high level) rising edge increment 0 (low level) falling edge rising edge 0 (low level) falling edge 1 (high level) 1 (high level) falling edge decrement 0 (low level) rising edge rising edge 1 (high level) falling edge 0 (low level) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 247 of 716 rej09b0398-0500 phase count mode 2: figure 10.30 shows an example of phase counting mode 2 operation. table 10.10 lists the up counting and down counting conditions for the tcnt. tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) tcnt value increment decrement time figure 10.30 phase counting mode 2 operation table 10.10 phase count mode 2 up/down counting conditions tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation 1 (high level) rising edge does not count (don't care) 0 (low level) falling edge rising edge 0 (low level) falling edge 1 (high level) increment 1 (high level) falling edge does not count (don't care) 0 (low level) rising edge rising edge 1 (high level) falling edge 0 (low level) decrement 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 248 of 716 rej09b0398-0500 phase count mode 3: figure 10.31 shows an example of phase counting mode 3 operation. table 10.11 lists the up counting and down counting conditions for the tcnt. increment decrement tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) tcnt value time figure 10.31 phase counting mode 3 operation table 10.11 phase count mode 3 up/down counting conditions tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation 1 (high level) rising edge does not count (don't care) 0 (low level) falling edge rising edge 0 (low level) falling edge 1 (high level) increment 1 (high level) falling edge decrement 0 (low level) rising edge does not count (don't care) rising edge 1 (high level) falling edge 0 (low level) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 249 of 716 rej09b0398-0500 phase count mode 4: figure 10.32 shows an example of phase counting mode 4 operation. table 10.12 lists the up counting and down counting conditions for the tcnt. increment decrement tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) tcnt value time figure 10.32 phase counting mode 4 operation table 10.12 phase count mode 4 up/down counting conditions tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation 1 (high level) rising edge increment 0 (low level) falling edge rising edge 0 (low level) does not count (don't care) falling edge 1 (high level) 1 (high level) falling edge decrement 0 (low level) rising edge rising edge 1 (high level) does not count (don't care) falling edge 0 (low level) phase counting mode application example: figure 10.33 shows an example where channel 1 is set to phase counting mode and is teamed with channel 0 to input a two-phase encoder pulse for a servo motor to accurately detect position and speed. channel 1 is set to phase counting mode 1, and the encoder pulse a phase and b phase are input to the tclka and tclkb pins. channel 0 is set so that the tcnt counter is cleared on a tgr0c register compare-match, and the tgr0a and tgr0c registers are used with the compare-match function to establish the speed control and position control periods. the tgr0b register is used with the input capture function, 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 250 of 716 rej09b0398-0500 and the tgr0b and tgr0d registers are employed for buffer operation. the channel 1 counter input clock is used as the tgr0b register input capture source, and a pulse width of four times the 2-phase encoder pulse is detected. the channel 1 tgr1a and tgr1b registers are set for the input capture function, the channel 0 tgr0a and tgr0c register compare-match is used as an input capture source, and all of the control period increment and decrement values ar e stored. this procedur e enables the accurate detection of position and speed. tclka tclkb edge detection circuit tcnt1 tcnt0 tgr1a (speed period capture) tgr0a (speed control period) tgr0c (position control period) tgr0b (pulse width capture) tgr0d (buffer operation) tgr1b (position period capture) channel 0 channel 1 + ? + ? figure 10.33 phase count mode application example 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 251 of 716 rej09b0398-0500 10.5 interrupts 10.5.1 interrupt sources and priority ranking the mtu has three interrupt sources: tgr register compare-match/input captures, tcnt counter overflows and tcnt counter underflows. because each of these three types of interrupts are allocated its own dedicated status flag and enable/disable bit, the issuing of interrupt request signals to the interrupt controller can be independently enabled or disabled. when an interrupt source is generated, the correspo nding status flag in the timer status register (tsr) is set to 1. if the corresponding enable/disable bit in the timer input enable register (tier) is set to 1 at this time, the mtu makes an interrupt request of the interrupt controller. the interrupt request is canceled by clearing the status flag to 0. the channel priority order can be changed with the interrupt controller. the priority ranking within a channel is fixed. for more information, see section 6, interrupt controller. table 10.13 lists the mtu interrupt sources. input capture/compa re match interrupts: if the tgie bit of the timer input enable register (tier) is already set to 1 when the tgf flag in the timer status register (tsr) is set to 1 by a tgr register input capture/compare-match of any channel, an interrupt request is sent to the interrupt controller. the interrupt request is can celed by clearing the tgf flag to 0. the mtu has 8 input capture/compare-match interrupts; four fo r channel 0, and two each for channels 1 and 2. overflow interrupts: if the tciev bit of the tier is already set to 1 when the tcfv flag in the tsr is set to 1 by a tcnt counter overflow of any channel, an interrupt request is sent to the interrupt controller. the interrupt request is can celed by clearing the tcfv flag to 0. the mtu has three overflow interrupts, one for each channel. underflow interrupts: if the tcieu bit of the tier is already set to 1 when the tcfu flag in the tsr is set to 1 by a tcnt counter underflow of any channel, an interrupt request is sent to the interrupt controller. the interrupt request is can celed by clearing the tcfu flag to 0. the mtu has two underflow interrupts, one each for channels 1 and 2. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 252 of 716 rej09b0398-0500 table 10.13 mtu interrupt sources channel interrupt source description dmac activation priority * 0 tgi0a tgr0a input capture/compare-match yes high tgi0b tgr0b input capture/compare-match no tgi0c tgr0c input capture/compare-match no tgi0d tgr0d input capture/compare-match no tci0v tcnt0 overflow no 1 tgi1a tgr1a input capture/compare-match yes tgi1b tgr1b input capture/compare-match no tci1v tcnt1 overflow no tci1u tcnt1 underflow no 2 tgi2a tgr2a input capture/compare-match yes tgi2b tgr2b input capture/compare-match no tci2v tcnt2 overflow no tci2u tcnt2 underflow no low note: * indicates the initial status following reset. the ranking of channels can be altered using the interrupt controller. 10.5.2 dmac activation the tgra register input capture/compare-match interrupt of any channel can be used as a source to activate the on-chip dmac. for details, refer to section 9, direct memory access controller (dmac). the mtu has three tgra register input capture/compare-match interrupts, one for any channel, that can be used as dmac activation sources. 10.5.3 a/d converter activation the tgra register input capture/compare-match of any channel can be used to activate the on- chip a/d converter. if the ttge bit of the tier is already set to 1 when the tgfa flag in the tsr is set to 1 by a tgra register input capture/compare-match of any of the channels, an a/d conversion start request is sent to the a/d converter. if the mtu conversion start trigger is selected at such a time on the a/d converter side when this happens, the a/d conversion starts. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 253 of 716 rej09b0398-0500 the mtu has three tgra register input capture/compare-match interrupts, one for each channel, that can be used as a/d converter activation sources. 10.6 operation timing 10.6.1 input/output timing tcnt count timing: count timing for the tcnt counter with internal clock operation is shown in figure 10.34. count timing with external clock operation (normal mode) is shown in figure 10.35, and figure 10.36 shows count timing with external clock operation (phase counting mode). tcnt input clock internal clock tcnt falling edge falling edge rising edge n ? 1 n n + 1 n + 2 figure 10.34 tcnt count timing during internal clock operation tcnt input clock internal clock tcnt falling edge falling edge rising edge n ? 1 n n + 1 n + 2 figure 10.35 tcnt count timing during external clock operation (normal mode) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 254 of 716 rej09b0398-0500 tcnt input clock external clock tcnt falling edge falling edge rising edge n ? 1 n n + 1 figure 10.36 tcnt count timing during external clock operation (phase counting mode) output compare output timing: the compare-match signal is generated at the final state of tcnt and tgr matching. when a compare-match signal is issued, the output value set in tior is output to the output compare output pin (the tioc pin). after tcnt and tgr matching, a compare-match signal is not issued until imme diately before the tc nt input clock. output compare output timing (normal mode and pwm mode) is shown in figure 10.37. tcnt input clock tioc pin compare- match signal tcnt tgr n n n + 1 figure 10.37 output compare output timing (normal mode/pwm mode) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 255 of 716 rej09b0398-0500 input capture signal timing: figure 10.38 illustrates input capture timing. input capture input input capture signal tcnt tgr n n + 2 n n + 2 n + 1 rising edge falling edge figure 10.38 input capture input signal timing counter clearing timing due to compare-match/input capture: timing for count er clearing due to compare-match is shown in figure 10.39. figure 10.40 shows the timing for counter clearing due to input capture. compare- match signal counter clear signal tcnt tgr n n h'0000 figure 10.39 counter cleari ng timing (compare-match) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 256 of 716 rej09b0398-0500 input capture signal counter clear signal tcnt tgr n n h'0000 figure 10.40 counter clearing timing (input capture) buffer operation timing: compare-match buffer operation timing is shown in figure 10.41. figure 10.42 shows input capture buffer operation timing. tcnt compare- match buffer signal tgra, tgrb tgrc, tgrd n n + 1 nn n compare- match signal figure 10.41 buffer operati on timing (compare-match) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 257 of 716 rej09b0398-0500 tcnt input capture signal buffer tgra, tgrb tgrc, tgrd n n + 1 nn n n + 1 n input capture signal figure 10.42 buffer operation timing (input capture) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 258 of 716 rej09b0398-0500 10.6.2 interrupt signal timing setting tgf flag timing during compare-match: figure 10.43 shows timing for the tgf flag of the timer status register (tsr) due to compar e-match, as well as tgi interrupt request signal timing. compare- match signal tcnt tcnt input clock tgr tgf flag tgi interrupt n n + 1 n figure 10.43 tgi interrupt timing (compare match) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 259 of 716 rej09b0398-0500 setting tgf flag timing during input capture: figure 10.44 shows timing for the tgf flag of the timer status register (tsr) due to input capture, as well as tgi interrupt request signal timing. input capture signal tcnt tgr tgf flag tgi interrupt n n figure 10.44 tgi interrupt timing (input capture) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 260 of 716 rej09b0398-0500 setting timing for overflow flag (tcfv)/underflow flag (tcfu): figure 10.45 shows timing for the tcfv flag of the timer status re gister (tsr) due to overflow, as well as tciv interrupt request signal timing. figure 10.46 shows timing for the tcfu flag of the timer status register (tsr) due to underflow, as well as tciu interrupt request signal timing. overflow signal tcnt (underflow) tcnt input clock tcfv flag tciv interrupt h'ffff h'0000 figure 10.45 tciv interrupt setting timing underflow signal tcnt (underflow) tcnt input clock tcfu flag tciu interrupt h'0000 h'ffff figure 10.46 tciu interrupt setting timing 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 261 of 716 rej09b0398-0500 status flag clearing timing: the status flag is cleared when the cpu reads a 1 status followed by a 0 write. for dma controller activation, clearing can also be done automatically. figure 10.47 shows the timing for status flag clearing by the cpu. figure 10.48 shows timing for clearing due to the dma controller. status flag interrupt request signal address write signal t 1 t 2 tsr write cycle tsr address figure 10.47 timing of status flag clearing by the cpu status flag interrupt request signal address t 1 t 2 dmac read cycle dmac write cycle source address destination address t 1 t 2 figure 10.48 timing of status flag clearing by dmac activation 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 262 of 716 rej09b0398-0500 10.7 usage notes this section describes contention and other ma tters requiring special attention during mtu operations. 10.7.1 input clock limitations the input clock pulse width, in the case of single edge, must be 1.5 states or greater, and 2.5 states or greater for both edges. normal operation cannot be guaranteed with lesser pulse widths. in phase counting mode, the phase difference between the two input clocks and the overlap must be 1.5 states or greater for each, and the pulse width must be 2.5 states or greater. input clock conditions for phase counting mode are shown in figure 10.49. overlap phase difference overlap phase difference pulse width pulse width pulse width pulse width tclkb (tclkd) tclka (tclkc) notes: phase difference and overlap: 1.5 states or greater pulse width: 2.5 states or greater figure 10.49 phase differe nce, overlap, and pulse width in phase count mode 10.7.2 note on cycle setting when setting a counter clearing by compare-match, clearing is done in the final state when tcnt matches the tgr value (update timing for count value on tcnt match). the actual number of states set in the counter is given by the following equation: f = (n + 1) (f: counter frequency, : operating frequency, n: value set in the tgr) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 263 of 716 rej09b0398-0500 10.7.3 contention between tcnt write and clear if a counter clear signal is issued in the t 2 state during the tcnt write cycle, tcnt clearing has priority, and tcnt write is not conducted (figure 10.50). counter clear signal tcnt address write signal t 1 t 2 tcnt write cycle tcnt address n h'0000 figure 10.50 tcnt write and clear contention 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 264 of 716 rej09b0398-0500 10.7.4 contention between tcnt write and increment if a count-up signal is issued in the t 2 state during the tcnt write cycle, tcnt write has priority, and the counter is not incremented (figure 10.51). tcnt input clock tcnt address write signal t 1 t 2 tcnt write cycle tcnt write data tcnt address m n figure 10.51 tcnt writ e and increment contention 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 265 of 716 rej09b0398-0500 10.7.5 contention between buffer register write and compare match if a compare-match occurs in the t 2 state of the tgr write cycle, data is transferred by the buffer operation from the buffer register to the tgr. data to be transferred on channel 0 is that after write (figure 10.52). buffer register compare match signal compare match buffer signal address write signal tgr t 1 t 2 tgr write cycle buffer register address nm buffer register write data m figure 10.52 tgr write and compare-match contention (channel 0) 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 266 of 716 rej09b0398-0500 10.7.6 contention between tgr read and input capture if an input capture signal is issued in the t 1 state of the tgr read cycle, the read data is that after input capture transfer (figure 10.53). tgr input capture signal internal data bus address read signal t 1 t 2 tgr read cycle tgr address m xm figure 10.53 tgr read and input capture contention 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 267 of 716 rej09b0398-0500 10.7.7 contention between tgr write and input capture if an input capture signal is issued in the t 2 state of the tgr read cycle, input capture has priority, and tgr write does not occur (figure 10.54). tgr input capture signal tcnt address write signal t 1 t 2 tgr write cycle tgr address m m figure 10.54 tgr write and input capture contention 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 268 of 716 rej09b0398-0500 10.7.8 contention between buffer register write and input capture if an input capture signal is issued in the t 2 state of the buffer write cycle, write to the buffer register does not occur, and buffer operation takes priority (figure 10.55). tgr input capture signal tcnt address write signal buffer register t 1 t 2 buffer register write cycle buffer register address n mn m figure 10.55 buffer register wr ite and input capture contention 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 269 of 716 rej09b0398-0500 10.7.9 contention between tg r write and compare match if a compare-match occurs in the t 2 state of the tgr write cycle, data is written to the tgr and a compare-match signal is issued (figure 10.56). tgr compare match signal tcnt address write signal t 1 t 2 tgr write cycle tgr address nn + 1 m n tgr write data figure 10.56 tgr write a nd compare match contention 10.7.10 tcnt2 write and overflow/underf low contention in cascade connection with timer counters tcnt1 and tcnt2 in a cascade connection, when a contention occurs during tcnt1 count (during a tcnt2 overflow/underflow) in the t 2 state of the tcnt2 write cycle, the write to tcnt2 is conducted, and the tcnt1 count signal is prohibited. at this point, if there is match with tgr1a and the tcnt1 value, a compare signal is issued. furthermore, when the tcnt1 count clock is selected as the input capture source of channel 0, tgra0 to tgrd0 carry out the input capture operation. in additio n, when the compare match/input capture is selected as the input capture source of tgrb1, tgrb1 carries out input capture operation. the timing is shown in figure 10.57. for cascade connections, be sure to synchronize settings for channels 1 and 2 when setting tcnt clearing. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 270 of 716 rej09b0398-0500 t1 t1 h'fffe h'ffff n n + 1 h'ffff m m n p qp m disabled tcnt2 write data tcnt2 address tcnt write cycle address write si g nal tcnt2 tgr2a, tgr2b channel 2 compare- match si g nal a/b tcnt1 input clock tcnt1 tgr1a channel 1 compare- match si g nal a tgr1b channel 1 inputcapture si g nal b tcnt0 tgr0a to tgr0d channel 0 input capture si g nal a to d figure 10.57 tcnt2 write and overflow/und erflow contention with cascade connection 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 271 of 716 rej09b0398-0500 10.7.11 contention between overflo w/underflow and counter clearing if overflow/underflow and counter clearing occur simultaneously, the tcfv/tcfu flag in tsr is not set and tcnt clearing takes precedence. figure 10.58 shows the operation timing when a tgr compare-match is specified as the clearing source, and h'ffff is set in tgr. tcnt input clock tcnt counter clear signal tgf flag tcfv flag h'ffff h'0000 disabled figure 10.58 contention betw een overflow and counter clearing 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 272 of 716 rej09b0398-0500 10.7.12 contention between tcnt write and overf low/underflow if there is an up-count or down-count in the t2 state of a tcnt write cycle, and overflow/underflow occurs, the tcnt write takes precedence and the tcfv/t cfu flag in tsr is not set . figure 10.59 shows the operation timing in this case. address write signal tcnt input clock tcnt tcfv flag h'ffff n tcnt write data disabled tcnt write cycle t1 t2 tcnt address figure 10.59 contention be tween tcnt write and overflow 10.7.13 cautions on carrying out buffer operation of channel 0 in pwm mode 1 in pwm mode 1, the tgra and tgrb registers are used in pairs and pwm waveform is output to the tioca pin. in the same manner, the tgrc and tgrd registers are used in pairs and pwm waveform is output to the tiocc pin. if either the tgrc or tgrd register is operating as a buffer register, the tiocc pin cannot execute default output se tting or pwm waveform output with the i/o control register (tior). note that for channel 0, the tiocc pin allows both default output setting by tior and pwm output when setting buffer operation only for the tgrd register in pwm mode 1. when using channel 0 in pwm mode 1 and setting buffer operation, use both the tgrc and tgrd registers as buffer registers. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 273 of 716 rej09b0398-0500 10.8 mtu output pi n initialization 10.8.1 operating modes the mtu has the following four operating modes. waveform output is possible in all of these modes. ? normal mode (channels 0 to 2) ? pwm mode 1 (channels 0 to 2) ? pwm mode 2 (channels 0 to 2) ? phase counting modes 1 to 4 (channels 1 and 2) the mtu output pin initialization method for each of these modes is described in this section. 10.8.2 reset start operation the mtu output pins (tioc*) are initialized low by a reset and in standby mode. since mtu pin function selection is performed by the pin function controller (pfc), when the pfc is set, the mtu pin states at that point are output to the ports. when mtu output is selected by the pfc immediately after a reset, the mtu output initial level, low, is output directly at the port. when the active level is low, the syst em will operate at this point, a nd therefore the pfc setting should be made after initialization of the mtu output pins is completed. note: channel number and port notation are substituted for *. 10.8.3 operation in case of re-setting due to error during operation, etc. if an error occurs during mtu operation, mtu output should be cut by the system. cutoff is performed by switching the pin output to port output with the pfc and outputting the inverse of the active level. the pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. the mtu has four operating modes, as stat ed above. there are thus 16 mode transition combinations. possible mode transition combinations are shown in table 10.14. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 274 of 716 rej09b0398-0500 table 10.14 mode transition combinations after before normal pwm1 pwm2 pcm normal (1) (2) (3) (4) pwm1 (5) (6) (7) (8) pwm2 (9) (10) (11) (12) pcm (13) (14) (15) (16) legend: normal: normal mode pwm1: pwm mode 1 pwm2: pwm mode 2 pcm: phase counting modes 1 to 4 the above abbreviations are used in so me places in following descriptions. 10.8.4 overview of initialization procedures and mode transitions in case of error during operation, etc. ? when making a transition to a mode (normal, pwm1, pwm2, pcm) in which the pin output level is selected by the timer i/o control register (tior) setting, initialize the pins by means of a tior setting. ? in pwm mode 1, since a waveform is not output to the tioc*b (tioc*d) pin, setting tior will not initialize the pins. if initialization is required, carry it out in normal mode, then switch to pwm mode 1. ? in pwm mode 2, since a waveform is not output to the cycle register pin, setting tior will not initialize the pins. if initialization is required, carry it out in normal mode, then switch to pwm mode 2. ? in normal mode or pwm mode 2, if tgrc and tgrd operate as buffer registers, setting tior will not initialize the buffer register pins. if initialization is required, clear buffer mode, carry out initialization, then set buffer mode again. ? in pwm mode 1, if either tgrc or tgrd operates as a buffer register, setting tior will not initialize the tgrc pin. to initialize the tgrc pin, clear buffer mode, carry out initialization, then set buffer mode again. note: channel number is substituted for * indicated in this article. pin initialization procedures are described below for the numbered combinations in table 10.14. the active level is assumed to be low. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 275 of 716 rej09b0398-0500 (1) operation when error o ccurs during normal mode op eration, and operation is restarted in normal mode: figure 10.60 shows an explanator y diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (normal) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen note: n = 0 to 15 pen hi-z hi-z figure 10.60 error occurrence in norm al mode, recovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. after a reset, the tmdr setting is for normal mode. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. not necessary when restarting in normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 276 of 716 rej09b0398-0500 (2) operation when error o ccurs during normal mode op eration, and operation is restarted in pwm mode 1: figure 10.61 shows an explanator y diagram of the case where an error occurs in normal mode and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (normal) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z ? not initialized (tioc * b) note: n = 0 to 15 figure 10.61 error occurrence in no rmal mode, recovery in pwm mode 1 1 to 9 are the same as in figure 10.60. 10. set pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized. if initialization is required, initialize in normal mode, then switch to pwm mode 1.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 277 of 716 rej09b0398-0500 (3) operation when error o ccurs during normal mode op eration, and operation is restarted in pwm mode 2: figure 10.62 shows an explanator y diagram of the case where an error occurs in normal mode and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (normal) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z ? not initialized (cycle re g ister) note: n = 0 to 15 figure 10.62 error occurrence in no rmal mode, recovery in pwm mode 2 1 to 9 are the same as in figure 10.60. 10. set pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized. if initialization is required, initialize in normal mode, then switch to pwm mode 2.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 278 of 716 rej09b0398-0500 (4) operation when error occurs during normal mode operation, and operation is restarted in phase counting mode: figure 10.63 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re- setting. 1 reset 2 tmdr (normal) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pcm) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z note: n = 0 to 15 figure 10.63 error occurr ence in normal mode, recov ery in phase counting mode 1 to 9 are the same as in figure 10.60. 10. set phase counting mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 279 of 716 rej09b0398-0500 (5) operation when error occurs during pwm mode 1 op eration, and operation is restarted in normal mode: figure 10.64 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (pwm1) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z ? not initialized (tioc * b) note: n = 0 to 15 figure 10.64 error occu rrence in pwm mode 1, r ecovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. set pwm mode 1. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence. in pwm mode 1, the tioc*b side is not initialized.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. set normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 280 of 716 rej09b0398-0500 (6) operation when error o ccurs during pwm mode 1 op eration, and operation is restarted in pwm mode 1: figure 10.65 shows an explanator y diagram of the case where an error occurs in pwm mode 1 and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (pwm1) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z ? not initialized (tioc * b) ? not initialized (tioc * b) note: n = 0 to 15 figure 10.65 error occurrence in pw m mode 1, recovery in pwm mode 1 1 to 9 are the same as in figure 10.64. 10. not necessary when restarting in pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 281 of 716 rej09b0398-0500 (7) operation when error o ccurs during pwm mode 1 op eration, and operation is restarted in pwm mode 2: figure 10.66 shows an explanator y diagram of the case where an error occurs in pwm mode 1 and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (pwm1) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z ? not initialized (tioc * b) ? not initialized (cycle re g ister) note: n = 0 to 15 figure 10.66 error occurrence in pw m mode 1, recovery in pwm mode 2 1 to 9 are the same as in figure 10.64. 10. set pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 282 of 716 rej09b0398-0500 (8) operation when error occurs during pwm mode 1 op eration, and operation is restarted in phase counting mode: figure 10.67 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in phase counting mode after re- setting. 1 reset 2 tmdr (pwm1) 4 pfc (mtu) 3 tior (1 init 0 out) 5 tstr (1) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pcm) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z ? not initialized (tioc * b) note: n = 0 to 15 figure 10.67 error occurr ence in pwm mode 1, recov ery in phase counting mode 1 to 9 are the same as in figure 10.64. 10. set phase counting mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 283 of 716 rej09b0398-0500 (9) operation when error occurs during pwm mode 2 op eration, and operation is restarted in normal mode: figure 10.68 shows an explanatory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z ? not initialized (cycle re g ister) note: n = 0 to 15 figure 10.68 error occu rrence in pwm mode 2, r ecovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. set pwm mode 2. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence. in pwm mode 2, the cycle register pins are not initialized. in the example, tioc*a is the cycle register.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. set normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 284 of 716 rej09b0398-0500 (10) operation when error occurs during pwm mode 2 op eration, and operation is restarted in pwm mode 1: figure 10.69 shows an explanatory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z ? not initialized (tioc * b) ? not initialized (cycle re g ister) note: n = 0 to 15 figure 10.69 error occurrence in pw m mode 2, recovery in pwm mode 1 1 to 9 are the same as in figure 10.68. 10. set pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 285 of 716 rej09b0398-0500 (11) operation when error occurs during pwm mode 2 op eration, and operation is restarted in pwm mode 2: figure 10.70 shows an explanator y diagram of the case where an error occurs in pwm mode 2 and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z ? not initialized (cycle re g ister) ? not initialized (cycle re g ister) note: n = 0 to 15 figure 10.70 error occurrence in pw m mode 2, recovery in pwm mode 2 1 to 9 are the same as in figure 10.68. 10. not necessary when restarting in pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 286 of 716 rej09b0398-0500 (12) operation when error occurs during pwm mode 2 op eration, and operation is restarted in phase counting mode: figure 10.71 shows an explanatory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in phase counting mode after re- setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pcm) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z ? not initialized (cycle re g ister) note: n = 0 to 15 figure 10.71 error occurr ence in pwm mode 2, recov ery in phase counting mode 1 to 9 are the same as in figure 10.68. 10. set phase counting mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 287 of 716 rej09b0398-0500 (13) operation when error occurs during phase countin g mode operation, and operation is restarted in normal mode: figure 10.72 shows an explanator y diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (pcm) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z note: n = 0 to 15 figure 10.72 error occurr ence in phase counting mode, recovery in normal mode 1. after a reset, mtu output is low and ports are in the high-impedance state. 2. set phase counting mode. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. set in normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 288 of 716 rej09b0398-0500 (14) operation when error occurs during phase countin g mode operation, and operation is restarted in pwm mode 1: figure 10.73 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (pcm) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z ? not initialized (tioc * b) note: n = 0 to 15 figure 10.73 error occurr ence in phase counting mode, recovery in pwm mode 1 1 to 9 are the same as in figure 10.72. 10. set pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 289 of 716 rej09b0398-0500 (15) operation when error occurs during phase countin g mode operation, and operation is restarted in pwm mode 2: figure 10.74 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (pcm) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z ? not initialized (cycle re g ister) note: n = 0 to 15 figure 10.74 error occurr ence in phase counting mode, recovery in pwm mode 2 1 to 9 are the same as in figure 10.72. 10. set pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 10. multifunction timer pulse unit (mtu) rev.5.00 sep. 27, 2007 page 290 of 716 rej09b0398-0500 (16) operation when error occurs during phase countin g mode operation, and operation is restarted in phase counting mode: figure 10.75 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. 1 reset 2 tmdr (pcm) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pcm) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu output tioc * a tioc * b port output pen pen hi-z hi-z note: n = 0 to 15 figure 10.75 error occurrence in phase counting mode, recovery in phase counting mode 1 to 9 are the same as in figure 10.72. 10. not necessary when restarting in phase counting mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 291 of 716 rej09b0398-0500 section 11 watchdog timer (wdt) 11.1 overview the watchdog timer (wdt) is a 1-channel timer for monitoring system operations. if a system encounters a problem (crashes, for example) and the timer counter overflows without being rewritten correctly by the cpu, an overflow signal ( wdtovf ) is output externally. the wdt can simultaneously generate an internal reset signal for the entire chip. when the watchdog function is not needed, the wdt can be used as an interval timer. in the interval timer operation, an inte rval timer interrupt is genera ted at each counter overflow. the wdt is also used in recovering from the standby mode. 11.1.1 features the wdt has the following features: ? works in watchdog timer mode or interval timer mode. ? outputs wdtovf in the watchdog timer mode. when the counter overflows in the watchdog timer mode, overflow signal wdtovf is output externally. you can select whether to reset the chip internally when this happens. ? generates interrupts in the interval timer mode. when the counter overflows, it generates an interval timer interrupt. ? clears standby mode. ? works with eight counter input clocks. 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 292 of 716 rej09b0398-0500 11.1.2 block diagram figure 11.1 is the block diagram of the wdt. /2 /64 /128 /256 /512 /1024 /4096 /8192 internal clock sources clock overflow clock select interrupt control reset control rstcsr le g end: tcsr: tcnt: rstcsr: note: * the internal reset si g nal can be g enerated by settin g the re g ister. timer control/status re g ister timer counter reset control/status re g ister tcnt tcsr module bus bus interface internal data bus iti (interrupt si g nal) wdtovf internal reset si g nal * wdt figure 11.1 wdt block diagram 11.1.3 pin configuration table 11.1 shows the pin configuration. table 11.1 pin configuration pin abbreviation i/o function watchdog timer overflow wdtovf o outputs the counter overflow signal in the watchdog timer mode 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 293 of 716 rej09b0398-0500 11.1.4 register configuration table 11.2 summarizes the three wdt registers. th ey are used to select the clock, switch the wdt mode, and control the reset signal. table 11.2 wdt registers address name abbreviation r/w initial value write * 1 read * 2 timer control/status register tcsr r/(w) * 3 h'18 h'ffff8610 h'ffff8610 timer counter tcnt r/w h'00 h'ffff8611 reset control/status register rstcsr r/(w) * 3 h'1f h'ffff8612 h'ffff8613 notes: 1. write by word transfer. it cannot be written in byte or longword. 2. read by byte transfer. it cannot be read in word or longword. 3. only 0 can be written in bit 7 to clear the flag. 11.2 register descriptions 11.2.1 timer counter (tcnt) bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the tcnt is an 8-bit read/write upcounter. (the tcnt differs from other registers in that it is more difficult to write to. see section 11.2.4, register access, for details.) when the timer enable bit (tme) in the timer control/status register (tcsr) is set to 1, the watchdog timer counter starts counting pulses of an internal clock selected by clock select bits 2 to 0 (cks2 to cks0) in the tcsr. when the value of the tcnt overflows (changes from h'ff to h'00), a watchdog timer overflow signal ( wdtovf ) or interval timer interrupt (iti) is generated, depending on the mode selected in the wt/ it bit of the tcsr. the tcnt is initialized to h'00 by a power-on reset a nd when the tme bit is cleared to 0. it is not initialized in the standby mode. 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 294 of 716 rej09b0398-0500 11.2.2 timer control/sta tus register (tcsr) bit: 7 6 5 4 3 2 1 0 ovf wt/ it tme ? ? cks2 cks1 cks0 initial value: 0 0 0 1 1 0 0 0 r/w: r/(w) r/w r/w r r r/w r/w r/w the timer control/status register (tcsr) is an 8-bit read/write register. (the tcsr differs from other registers in that it is more difficult to write to. see section 11.2.4, register access, for details.) its functions include selecting the timer mode and clock source. bits 7 to 5 are initialized to 000 by a power-on rese t or in standby mode. bits 2 to 0 are initialized to 000 by a power-on reset, but retain their values in the standby mode. bit 7 ? overflow flag (ovf): indicates that the tcnt has overflowed from h'ff to h'00 in the interval timer mode. it is not set in the watchdog timer mode. bit 7 ovf description 0 no overflow of tcnt in interval timer mode (initial value) cleared by reading ovf, then writing 0 in ovf 1 tcnt overflow in the interval timer mode bit 6 ? timer mode select (wt/ it ): selects whether to use the wdt as a watchdog timer or interval timer. when the tcnt overflows, the wdt either generates an interval timer interrupt (iti) or generates a wdtovf signal, depending on the mode selected. bit 6 wt/ it description 0 interval timer mode: interval timer interrupt request to the cpu when tcnt overflows (initial value) 1 watchdog timer mode: wdtovf signal output externally when tcnt overflows. (section 11.2.3, reset control/status register (rstcsr), describes in detail what happens when tcnt overflows in the watchdog timer mode.) 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 295 of 716 rej09b0398-0500 bit 5 ? timer enable (tme): enables or disables the timer. bit 5 tme description 0 timer disabled: tcnt is initialized to h'00 and count-up stops (initial value) 1 timer enabled: tcnt starts counting. a wdtovf signal or interrupt is generated when tcnt overflows. bits 4 and 3 ? reserved: these bits always read as 1. the write value should always be 1. bits 2 to 0: clock select 2 to 0 (cks2 to cks0): these bits select one of eight internal clock sources for input to the tcnt. the clock signals are obtained by dividing the frequency of the system clock ( ). description bit 2 cks2 bit 1 cks1 bit 0 cks0 clock source overflow interval * ( = 28.7 mhz) 0 0 0 /2 (initial value) 17.9 s 0 0 1 /64 573.4 s 0 1 0 /128 1.1 ms 0 1 1 /256 2.3 ms 1 0 0 /512 4.6 ms 1 0 1 /1024 9.2 ms 1 1 0 /4096 36.7 ms 1 1 1 /8192 73.4 ms note: * the overflow interval listed is the time from when the tcnt begins counting at h'00 until an overflow occurs. 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 296 of 716 rej09b0398-0500 11.2.3 reset control/status register (rstcsr) bit: 7 6 5 4 3 2 1 0 wovf rste ? ? ? ? ? ? initial value: 0 0 0 1 1 1 1 1 r/w: r/(w) * r/w r r r r r r note: * only 0 can be written in bit 7 to clear the flag. the rstcsr is an 8-bit readable and writable register. (the rstcsr differs from other registers in that it is more difficult to write. see section 11. 2.4, register access, for details.) it controls output of the internal reset signal generated by timer counter (tcnt) overflow. rstcr is initialized to h'1f by input of a reset signal from the res pin, but is not initialized by the internal reset signal generated by the overflow of the wdt. it is initialized to h'1f in standby mode. bit 7 ? watchdog timer overflow flag (wovf): indicates that the tcnt has overflowed (h'ff to h'00) in the watchdog timer mode. it is not set in the interval timer mode. bit 7 wovf description 0 no tcnt overflow in watchdog timer mode (initial value) cleared when software reads wovf, then writes 0 in wovf 1 set by tcnt overflow in watchdog timer mode bit 6 ? reset enable (rste): selects whether to reset the chip internally if the tcnt overflows in the watchdog timer mode. bit 6 rste description 0 not reset when tcnt overflows (initial value) lsi not reset internally, but tcnt and tcsr reset within wdt. 1 reset when tcnt overflows bit 5 ? reserved: this bit always read as 0. the write value should always be 0. bits 4 to 0 ? reserved: these bits always read as 1. the write value should always be 1. 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 297 of 716 rej09b0398-0500 11.2.4 register access the watchdog timer's tcnt, tcsr, and rstcsr registers differ from other registers in that they are more difficult to write to. the procedures for writing and reading these registers are given below. writing to the tcnt and tcsr: these registers must be written by a word transfer instruction. they cannot be written by byte transfer instructions. the tcnt and tcsr both have the same write address. the write data must be contained in the lower byte of the written word. the upper byte must be h'5a (for the tcnt) or h'a5 (for the tcsr) (figure 11.2). this transfers the write data from the lower byte to the tcnt or tcsr. h'5a h'ffff8610 address: writing to the tcnt 15 8 7 0 write data h'a5 h'ffff8610 address: writing to the tcsr 15 8 7 0 write data figure 11.2 writing to the tcnt and tcsr writing to the rstcsr: the rstcsr must be written by a word access to address h'ffff8612. it cannot be written by byte transfer instructions. procedures for writing 0 in wovf (bit 7) and for writing to rste (bit 6) are different, as shown in figure 11.3. to write 0 in the wovf bit, the write data must be h'a5 in the upper byte and h'00 in the lower byte. this clears the wovf bit to 0. the rste bit is not affected. to write to the rste bit, the upper byte must be h'5a and the lower byte must be the write data. the values of bit 6 of the lower byte is transferred to the rste bit, respectively. the wovf bit is not affected. 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 298 of 716 rej09b0398-0500 h'a5 h'ffff8612 address: writing 0 to the wovf bit 15 8 7 0 h'00 h'5a h'ffff8612 address: writing to the rste bit 15 8 7 0 write data figure 11.3 writing to the rstcsr reading from the tcnt, tcsr, and rstcsr: tcnt, tcsr, and rstcsr are read like other registers. use byte transfer instructions. the read addresses are h'ffff8610 for the tcsr, h'ffff8611 for the tcnt, and h'ffff8613 for the rstcsr. 11.3 operation 11.3.1 watchdog timer mode to use the wdt as a watchdog timer, set the wt/ it and tme bits of the tcsr to 1. software must prevent tcnt overflow by rewriting the tcnt value (normally by writing h'00) before overflow occurs. no tcnt overflows will occur while the system is operating normally, but if the tcnt fails to be rewritten and overflows occur due to a system crash or the like, a wdtovf signal is output externally (figure 11.4). the wdtovf signal can be used to reset the system. the wdtovf signal is output for 128 clock cycles. if the rste bit in the rstcsr is set to 1, a signal to reset the chip will be generated internally simultaneous to the wdtovf signal when tcnt overflows. the internal reset signal is output for 512 clock cycles. when a watchdog overflow reset is generated simultaneously with a reset input at the res pin, the res reset takes priority, and the wovf bit is cleared to 0. the following are not initialized a wdt reset signal: ? pfc (pin function controller) function register ? i/o port register initializing is only possible by external power-on reset. 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 299 of 716 rej09b0398-0500 h'ff h'00 overflow wt/ it = 1 tme = 1 h'00 written in tcnt internal reset si g nal * wdtovf si g nal tcnt value wdtovf and internal reset g enerated wovf = 1 wt/ it = 1 tme = 1 le g end: wt/ it : tme: timer mode select bit timer enable bit h'00 written in tcnt time 512 clocks 128 clocks note: * internal reset si g nal occurs only when the rste bit is set to 1. figure 11.4 operation in the watchdog timer mode 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 300 of 716 rej09b0398-0500 11.3.2 interval timer mode to use the wdt as an in terval timer, clear wt/ it to 0 and set tme to 1. an interval timer interrupt (iti) is generated each time the timer counter overflows. this function can be used to generate interval timer interrupts at regular intervals (figure 11.5). h'ff tcnt value le g end: iti: interval timer interrupt request g eneration h'00 wt/ it = 0 tme = 1 iti iti iti iti time overflow overflow overflow overflow figure 11.5 operation in the interval timer mode 11.3.3 clearing the standby mode the watchdog timer has a special function to clear the standby mode with an nmi interrupt. when using the standby mode, set the wdt as described below. before transition to the standby mode: the tme bit in the tcsr mu st be cleared to 0 to stop the watchdog timer counter before it enters the standby mode. the chip cannot enter the standby mode while the tme bit is set to 1. set bits cks2 to cks0 so that the counter overflow interval is equal to or longer than the oscillation settling time. see section 20.3, ac characteristics, for the oscillation settling time. recovery from the standby mode: when an nmi request signal is received in standby mode, the clock oscillator starts running and the watchdog timer starts incrementing at the rate selected by bits cks2 to cks0 before the standby mode was entered. when the tcnt overflows (changes from h'ff to h'00), the clock is presumed to be stable and usable; clock signals are supplied to the entire chip and the standby mode ends. for details on the standby mode, see section 19, power down state. 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 301 of 716 rej09b0398-0500 11.3.4 timing of setting the overflow flag (ovf) in the interval timer mode, when the tcnt overflo ws, the ovf flag of the tcsr is set to 1 and an interval timer interrupt is simultaneously requested (figure 11.6). h'ff h'00 ck tcnt overflow signal (internal signal) ovf figure 11.6 timing of setting the ovf 11.3.5 timing of setting the watchdog timer overflow flag (wovf) when the tcnt overflows in the watchdog timer mode, the wovf bit of the rstcsr is set to 1 and a wdtovf signal is output. when the rste bit is set to 1, tcnt overflow enables an internal reset signal to be generated for the entire chip (figure 11.7). h'ff h'00 ck tcnt overflow signal (internal signal) wovf figure 11.7 timing of setting the wovf bit 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 302 of 716 rej09b0398-0500 11.4 usage notes 11.4.1 tcnt write and increment contention if a timer counter increment clock pulse is generated during the t 3 state of a write cycle to the tcnt, the write takes priority and the timer counter is not incremented (figure 11.8). ck address internal write signal tcnt input clock tcnt nm tcnt address counter write data t 1 t 2 t 3 tcnt write cycle figure 11.8 contention betw een tcnt write and increment 11.4.2 changing cks2 to cks0 bit values if the values of bits cks2 to cks0 are altered while the wdt is running, the count may increment incorrectly. always stop the watchdog timer (by clearing the tme bit to 0) before changing the values of bits cks2 to cks0. 11.4.3 changing between watchdog timer/interval timer modes to prevent incorrect operation, always stop the watchdog timer (by clearing the tme bit to 0) before switching between interval timer mode and watchdog timer mode. 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 303 of 716 rej09b0398-0500 11.4.4 system reset with wdtovf if a wdtovf signal is input to the res pin, the lsi cannot initialize correctly. avoid logical input of the wdtovf output signal to the res input pin. to reset the entire system with the wdtovf signal, use the circuit shown in figure 11.9. reset input reset si g nal to entire system sh7014/16/17 res wdtovf figure 11.9 example of a system reset circuit with a wdtovf signal 11.4.5 internal reset with the watchdog timer if the rste bit is cleared to 0 in the watchdog timer mode, the lsi will not reset internally when a tcnt overflow occurs, but the tcnt and tcsr in the wdt will reset. 11. watchdog timer (wdt) rev.5.00 sep. 27, 2007 page 304 of 716 rej09b0398-0500 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 305 of 716 rej09b0398-0500 section 12 serial communication interface (sci) 12.1 overview this lsi has a serial communication interface (s ci) with two independent channels, both of which possess the same functions. the sci supports both asynchronous and clock synchronous serial communication. it also has a multiprocessor communication function for serial communication among two or more processors. 12.1.1 features the sci has the following features: ? select asynchronous or clock synchronous as the serial communications mode. ? asynchronous mode: serial data communications are synched by start-stop in character units. the sci can communicate with a uni versal asynchronous receiver/transmitter (uart), an asynchronous communication interface adapter (acia), or any other chip that employs a standard asynchronous serial communication. it can also communicate with two or more other processors using the multiprocessor communication function. there are twelve selectable serial data communication formats. ? data length: seven or eight bits ? stop bit length: one or two bits ? parity: even, odd, or none ? multiprocessor bit: one or none ? receive error detection: parity , overrun, and framing errors ? break detection: by reading the rxd level directly when a framing error occurs ? clocked synchronous mode: serial data communication is synchronized with a clock signal. the sci can communicate with other chips having a clock synchronous communication function. there is one serial data communication format. ? data length: eight bits ? receive error detec tion: overrun errors ? full duplex communication: the transmitting and r eceiving sections are independent, so the sci can transmit and receive simultaneously . both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. ? on-chip baud rate generator with selectable bit rates. ? internal or external transmit/receive clock source: baud rate generator (internal) or sck pin (external). 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 306 of 716 rej09b0398-0500 ? four types of interrupts: transmit-data-empty , transmit-end, receive-data-full, and receive- error interrupts are requested independently. th e transmit-data-empty and receive-data-full interrupts can start the dir ect memory access controller (dmac) to transfer data. 12.1.2 block diagram figure 12.1 shows a block diagram of the sci. parity g eneration parity check transmit/ receive control baud rate g enerator clock external clock bus interface internal data bus rxd rdr tdr rsr tsr ssr scr smr brr /4 /16 /64 tei txi rxi eri sck : : : : rsr rdr tsr tdr receive shift re g ister receive data re g ister transmit shift re g ister transmit data re g ister : : : : smr scr ssr brr serial mode re g ister serial control re g ister serial status re g ister bit rate re g ister txd sci module data bus le g end: figure 12.1 sci block diagram 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 307 of 716 rej09b0398-0500 12.1.3 pin configuration table 12.1 summarizes the sci pins by channel. table 12.1 sci pins channel pin name abbreviation input/output function 0 serial clock pin sck0 input/output sci0 clock input/output receive data pin rxd0 input sci0 receive data input transmit data pin txd0 output sci0 transmit data output 1 serial clock pin sck1 input/output sci1 clock input/output receive data pin rxd1 input sci1 receive data input transmit data pin txd1 output sci1 transmit data output 12.1.4 register configuration table 12.2 summarizes the sci internal registers. these registers select the communication mode (asynchronous or clock synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. table 12.2 registers channel name abbreviation r/w initial value address * 2 access size 0 serial mode register smr0 r/w h'00 h'ffff81a0 8, 16 bit rate register brr0 r/w h'ff h'ffff81a1 8, 16 serial control register scr0 r/w h'00 h'ffff81a2 8, 16 transmit data register tdr0 r/w h'ff h'ffff81a3 8, 16 serial status register ssr0 r/(w) * 1 h'84 h'ffff81a4 8, 16 receive data register rdr0 r h'00 h'ffff81a5 8, 16 1 serial mode register smr1 r/w h'00 h'ffff81b0 8, 16 bit rate register brr1 r/w h'ff h'ffff81b1 8, 16 serial control register scr1 r/w h'00 h'ffff81b2 8, 16 transmit data register tdr1 r/w h'ff h'ffff81b3 8, 16 serial status register ssr1 r/(w) * 1 h'84 h'ffff81b4 8, 16 receive data register rdr1 r h'00 h'ffff81b5 8, 16 notes: 1. the only value that can be written is a 0 to clear the flags. 2. do not access empty addresses. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 308 of 716 rej09b0398-0500 12.2 register descriptions 12.2.1 receive shift register (rsr) bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? the receive shift register (rsr) receives serial data . data input at the rxd pin is loaded into the rsr in the order received, lsb (bit 0) first, co nverting the data to parallel form. when one byte has been received, it is automati cally transferred to the rdr. the cpu cannot read or write the rsr directly. 12.2.2 receive data register (rdr) bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r the receive data register (rdr) stores serial r eceive data. the sci comple tes the reception of one byte of serial data by moving the received data from the receive sh ift register (rsr) into the rdr for storage. the rsr is then ready to receive the next data. this double buffering allows the sci to receive data continuously. the cpu can read but not write the rdr. the rdr is initialized to h'00 by a power-on reset or in standby mode. 12.2.3 transmit shift register (tsr) bit: 7 6 5 4 3 2 1 0 r/w: ? ? ? ? ? ? ? ? the transmit shift register (tsr) transmits serial data. the sci loads transmit data from the transmit data register (tdr) into the tsr, then transmits the data serially from the txd pin, lsb (bit 0) first. after transmitting one data byte, the sci automatically loads the next transmit data 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 309 of 716 rej09b0398-0500 from the tdr into the tsr and starts transmitting again. if the tdre bit of the ssr is 1, however, the sci does not load the tdr contents into the tsr. the cpu cannot read or write the tsr directly. 12.2.4 transmit data register (tdr) bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the transmit data register (tdr) is an 8-bit register that stores data for serial transmission. when the sci detects that the transmit shift register (tsr) is empty, it moves transmit data written in the tdr into the tsr and starts serial transmission. continuous serial transmission is possible by writing the next transmit data in the tdr during serial transmission from the tsr. the cpu can always read and write the tdr. the tdr is initialized to h'ff by a power-on reset or in standby mode. 12.2.5 serial mode register (smr) bit: 7 6 5 4 3 2 1 0 c/ a chr pe o/ e stop mp cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the serial mode register (smr) is an 8-bit regi ster that specifies the sci serial communication format and selects the clock source for the baud rate generator. the cpu can always read and write the smr. the smr is initialized to h'00 by a power-on reset or in standby mode. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 310 of 716 rej09b0398-0500 bit 7 ? communication mode (c/ a ): selects whether the sci operates in the asynchronous or clock synchronous mode. bit 7 c/ a description 0 asynchronous mode (initial value) 1 clocked synchronous mode bit 6 ? character length (chr): selects 7-bit or 8-bit data in the asynchronous mode. in the clock synchronous mode, the data length is always eight bits, regardless of the chr setting. bit 6 chr description 0 eight-bit data (initial value) 1 seven-bit data * note: * when 7-bit data is selected, the msb (bit 7) of the transmit data register is not transmitted. bit 5 ? parity enable (pe): selects whether to add a parity bit to transmit data and to check the parity of receive data, in the asynchronous mode. in the clock synchronous mode, a parity bit is neither added nor checked, regardless of the pe setting. bit 5 pe description 0 parity bit not added or checked (initial value) 1 parity bit added and checked * note: * when pe is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (o/ e ) setting. receive data parity is checked according to the even/odd (o/ e ) mode setting. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 311 of 716 rej09b0398-0500 bit 4 ? parity mode (o/ e ): selects even or odd parity when parity bits are added and checked. the o/ e setting is used only in asynchronous mode and only when the parity enable bit (pe) is set to 1 to enable parity addition and check. the o/ e setting is ignored in the clock synchronous mode, or in the asynchronous mode when parity addition and check is disabled. bit 4 o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. if even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 2. if odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. bit 3 ? stop bit length (stop): selects one or two bits as the stop bit length in the asynchronous mode. this setting is used only in the asynchronous mode. it is ignored in the clock synchronous mode because no stop bits are added. bit 3 stop description 0 one stop bit * 1 (initial value) 1 two stop bits * 2 notes: 1. in transmitting, a single bit of 1 is added at the end of each transmitted character. 2. in transmitting, two bits of 1 are added at the end of each transmitted character. in receiving, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 312 of 716 rej09b0398-0500 bit 2 ? multiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, settings of the parity enable (pe) and parity mode (o/ e ) bits are ignored. the mp bit setting is used only in the asynchronous mode; it is ignored in the clock synchronous mode. for the multiprocessor communication function, see section 12.3.3, multiprocessor communication. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bits 1 and 0 ? clock select 1 and 0 (cks1 and cks0): these bits select the internal clock source of the on-chip baud rate generator. four clock sources are available; , /4, /16, or /64. for further information on the clock source, bit rate register settings, and baud rate, see section 12.2.8, bit rate register. bit 1 cks1 bit 0 cks0 description 0 0 (initial value) 1 /4 1 0 /16 1 /64 12.2.6 serial control register (scr) bit: 7 6 5 4 3 2 1 0 tie rie te re mpie teie cke1 cke0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the serial control register (scr) operates the sc i transmitter/receiver, selects the serial clock output in the asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. the cpu can always read and write the scr. the scr is initialized to h'00 by a power-on reset or in standby mode. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 313 of 716 rej09b0398-0500 bit 7 ? transmit interrupt enable (tie): enables or disables the transmit-data-empty interrupt (txi) requested when the transmit data register empty bit (tdre) in the serial status register (ssr) is set to 1 by transfer of serial transmit data from the tdr to the tsr. bit 7 tie description 0 transmit-data-empty interrupt request (txi) is disabled * (initial value) 1 transmit-data-empty interrupt request (txi) is enabled note: * the txi interrupt request can be cleared by reading tdre after it has been set to 1, then clearing tdre to 0, or by clearing tie to 0. bit 6 ? receive interrupt enable (rie): enables or disables the r eceive-data-full interrupt (rxi) requested when the receive data register full bit (rdr f) in the serial status register (ssr) is set to 1 by transfer of serial receive data from the rsr to the rdr. it also enables or disables receive- error interrupt (eri) requests. bit 6 rie description 0 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are disabled * (initial value) 1 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are enabled note: * rxi and eri interrupt requests can be cleared by reading the rdrf flag or error flag (fer, per, or orer) after it has been set to 1, then clearing the flag to 0, or by clearing rie to 0. bit 5 ? transmit enable (te): enables or disables the sci serial transmitter. bit 5 te description 0 transmitter disabled * 1 (initial value) 1 transmitter enabled * 2 notes: 1. the transmit data register empty bit (tdre) in the serial status register (ssr) is locked at 1. 2. serial transmission starts when the transmit data register empty (tdre) bit in the serial status register (ssr) is cleared to 0 after writing of transmit data into the tdr. select the transmit format in the smr before setting te to 1. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 314 of 716 rej09b0398-0500 bit 4 ? receive enable (re): enables or disables the sci serial receiver. bit 4 re description 0 receiver disabled * 1 (initial value) 1 receiver enabled * 2 notes: 1. clearing re to 0 does not affect the receive flags (rdrf, fer, per, orer). these flags retain their previous values. 2. serial reception starts when a start bit is detected in the asynchronous mode, or synchronous clock input is detected in the clock synchronous mode. select the receive format in the smr before setting re to 1. bit 3 ? multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie setting is used only in the asynchronous mode, and only if the multiprocessor mode bit (mp) in the serial mode register (smr) is set to 1 during reception. the mpie setting is ignored in the clock synchronous mode or when the mp bit is cleared to 0. bit 3 mpie description 0 multiprocessor interrupts are disabled (normal receive operation) (initial value) mpie is cleared when the mpie bit is cleared to 0, or the multiprocessor bit (mpb) is set to 1 in receive data. 1 multiprocessor interrupts are enabled * receive-data-full interrupt requests (rxi), receive-error interrupt requests (eri), and setting of the rdrf, fer, and orer status flags in the serial status register (ssr) are disabled until data with the multiprocessor bit set to 1 is received. note: * the sci does not transfer receive data from the rsr to the rdr, does not detect receive errors, and does not set the rdrf, fer, and orer flags in the serial status register (ssr). when it receives data that includes mpb = 1, mpb is set to 1, and the sci automatically clears mpie to 0, generates rxi and eri interrupts (if the tie and rie bits in the scr are set to 1), and allows the fer and orer bits to be set. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 315 of 716 rej09b0398-0500 bit 2 ? transmit-end interrupt enable (teie): enables or disables the transmit-end interrupt (tei) requested if tdr does not contain valid transmit data when the msb is transmitted. bit 2 teie description 0 transmit-end interrupt (tei) requests are disabled * (initial value) 1 transmit-end interrupt (tei) requests are enabled. * note: * the tei request can be cleared by reading the tdre bit in the serial status register (ssr) after it has been set to 1, then clearing tdre to 0 and clearing the transmit end (tend) bit to 0; or by clearing the teie bit to 0. bits 1 and 0 ? clock enable 1 and 0 (cke1 and cke0): these bits select the sci clock source and enable or disable clock output from the sck pin. depending on the combination of cke1 and cke0, the sck pin can be used for serial clock output, or serial clock input. select the sck pin function by using the pin function controller (pfc). the cke0 setting is valid only in the asynchronous mode, and only when the sci is internally clocked (cke1 = 0). the cke0 setting is ignored in the clock synchronous mode, or when an external clock source is selected (cke1 = 1). se lect the sci operating mode in the serial mode register (smr) before setting cke1 and cke0. for further details on selection of the sci clock source, see table 12.9 in section 12.3, operation. bit 1 cke1 bit 0 cke0 description * 1 0 0 asynchronous mode internal clock, sck pin used for input pin (input signal is ignored) or output pin (output level is undefined) * 2 clock synchronous mode internal clock, sck pin used for synchronous clock output * 2 0 1 asynchronous mode internal clock, sck pin used for clock output * 3 clock synchronous mode internal clock, sck pin used for synchronous clock output 1 0 asynchronous mode external clock, sck pin used for clock input * 4 clock synchronous mode external clock, sck pin used for synchronous clock input 1 1 asynchronous mode external clock, sck pin used for clock input * 4 clock synchronous mode external clock, sck pin used for synchronous clock input notes: 1. the sck pin is multiplexed with other functions. use the pin function controller (pfc) to select the sck function for this pin, as well as the i/o direction. 2. initial value. 3. the output clock frequency is the same as the bit rate. 4. the input clock frequency is 16 times the bit rate. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 316 of 716 rej09b0398-0500 12.2.7 serial status register (ssr) the serial status register (ssr) is an 8-bit register containing multiprocessor bit values, and status flags that indicate sci operating status. the cpu can always read and write the ssr, but cannot write 1 in the status flags (tdre, rdrf, orer, per, and fer). these flags can be cleared to 0 only if they have first been read (after being set to 1). bits 2 (tend) and 1 (mpb) are r ead-only bits that cannot be written. the ssr is initialized to h'84 by a power-on reset or in standby mode. bit: 7 6 5 4 3 2 1 0 tdre rdrf orer fer per tend mpb mpbt initial value: 1 0 0 0 0 1 0 0 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * the only value that can be written is a 0 to clear the flag. bit 7 ? transmit data register empty (tdre): indicates that the sci has loaded transmit data from the tdr into the tsr and new serial transmit data can be written in the tdr. bit 7 tdre description 0 tdr contains valid transmit data [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when dmac writes data in tdr 1 tdr does not contain valid transmit data (initial value) [setting conditions] ? power-on reset or standby mode ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 317 of 716 rej09b0398-0500 bit 6 ? receive data register full (rdrf): indicates that rdr c ontains received data. bit 6 rdrf description 0 rdr does not contain valid re ceived data (initial value) [clearing conditions] ? power-on reset or standby mode ? when 0 is written to rdrf after reading rdrf = 1 ? when dmac reads data from rdr 1 rdr contains valid received data [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr note: the rdr and rdrf are not affected by detection of receive errors or by clearing of the re bit to 0 in the serial control register. they retain their previous contents. if rdrf is still set to 1 when reception of the next data ends, an overrun error (orer) occurs and the received data is lost. bit 5 ? overrun error (orer): indicates that data reception ended abnormally due to an overrun error. bit 5 orer description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] ? power-on reset or standby mode ? when 0 is written to orer after reading orer = 1 1 a receive overrun error occurred [setting condition] when the next serial reception is completed while rdrf = 1 * 2 notes: 1. the orer flag is not affected and retains their previous values when the re bit in scr is cleared to 0. 2. rdr continues to hold the data received before the overrun error, so subsequent receive data is lost. serial receiving cannot continue while orer is set to 1. in the clock synchronous mode, serial transmitting is disabled. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 318 of 716 rej09b0398-0500 bit 4 ? framing error (fer): indicates that data reception e nded abnormally due to a framing error in the asynchronous mode. bit 4 fer description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] ? power-on reset or standby mode ? when 0 is written to fer after reading fer = 1 1 a receive framing error occurred * 2 [setting condition] when at the end of an sci receive operation the final stop bit of the receive data is checked and its value * 2 is 0 notes: 1. the fer flag is not affected and retains their previous values when the re bit in scr is cleared to 0. 2. when the stop bit length is two bits, only the first bit is checked to see if it is a 1. the second stop bit is not checked. when a framing error occurs, the sci transfers the receive data into the rdr but does not set rdrf. serial receiving cannot continue while fer is set to 1. in the clock synchronous mode, serial transmitting is also disabled. in addition, serial transmission cannot continue in clock synchronous mode. bit 3 ? parity error (per): indicates that data reception (with parity) ended abnormally due to a parity error in the asynchronous mode. bit 3 per description 0 receiving is in progress or has ended normally * 1 (initial value) [clearing conditions] ? power-on reset or standby mode ? when 0 is written to per after reading per = 1 1 a receive parity error occurred * 2 [setting condition] per is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (o/ e ) in the serial mode register (smr) notes: 1. the per flag is not affected and retains their previous values when the re bit in scr is cleared to 0. 2. when a parity error occurs, the sci transfers the receive data into the rdr but does not set rdrf. serial receiving cannot continue while per is set to 1. in the clock synchronous mode, serial transmitting is also disabled. in addition, serial transmission cannot continue in clock synchronous mode. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 319 of 716 rej09b0398-0500 bit 2 ? transmit end (tend): indicates that when the last bit of a serial character was transmitted, the tdr did not contain valid data, so transmission has ended. tend is a read-only bit and cannot be written. bit 2 tend description 0 transmission is in progress [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when dmac writes data in tdr 1 end of transmission (initial value) [setting conditions] ? power-on reset or standby mode ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character bit 1 ? multiprocessor bit (mpb): stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for r eceiving in the asynchronous mode. the mpb is a read-only bit and cannot be written. bit 1 mpb description 0 multiprocessor bit value in receive data is 0 * (initial value) 1 multiprocessor bit value in receive data is 1 note: * if re is cleared to 0 when a multiprocessor format is selected, the mpb retains its previous value. bit 0 ? multiprocessor bit transfer (mpbt): stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode. the mpbt setting is ignored in the clock synchr onous mode, when a multiprocessor format is not selected, or when the sci is not transmitting. bit 0 mpbt description 0 multiprocessor bit value in transmit data is 0 (initial value) 1 multiprocessor bit value in transmit data is 1 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 320 of 716 rej09b0398-0500 12.2.8 bit rate register (brr) the bit rate register (brr) is an 8-bit register that, together with the baud rate generator clock source selected by the cks1 and cks0 bits in th e serial mode register (smr), determines the serial transmit/receive bit rate. the cpu can always read and write the brr. the brr is initialized to h'ff by a power-on reset or in standby mode. each channel has independent ba ud rate generator control, so different values can be set in the two channels. bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 12.3 lists examples of brr settings in the asynchronous mode; table 12.4 lists examples of bbr settings in the clock synchronous mode. table 12.3 bit rates and brr settings in asynchronous mode (mhz) 4 4.9152 6 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 70 0.03 2 86 0.31 2 106 ? 0.44 150 1 207 0.16 1 255 0.00 2 77 0.16 300 1 103 0.16 1 127 0.00 1 155 0.16 600 0 207 0.16 0 255 0.00 1 77 0.16 1200 0 103 0.16 0 127 0.00 0 155 0.16 2400 0 51 0.16 0 63 0.00 0 77 0.16 4800 0 25 0.16 0 31 0.00 0 38 0.16 9600 0 12 0.16 0 15 0.00 0 19 ? 2.34 14400 0 8 ? 3.55 0 10 ? 3.03 0 12 0.16 19200 0 6 ? 6.99 0 7 0.00 0 9 ? 2.34 28800 0 3 8.51 0 4 6.67 0 6 ? 6.99 31250 0 3 0.00 0 4 ? 1.70 0 5 0.00 38400 0 2 8.51 0 3 0.00 0 4 ? 2.34 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 321 of 716 rej09b0398-0500 (mhz) 7.3728 8 9.8304 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 130 ? 0.07 2 141 0.03 2 174 ? 0.26 150 2 95 0.00 2 103 0.16 2 127 0.00 300 1 191 0.00 1 207 0.16 1 255 0.00 600 1 95 0.00 1 103 0.16 1 127 0.00 1200 0 191 0.00 0 207 0.16 0 255 0.00 2400 0 95 0.00 0 103 0.16 0 127 0.00 4800 0 47 0.00 0 51 0.16 0 63 0.00 9600 0 23 0.00 0 25 0.16 0 31 0.00 14400 0 15 0.00 0 16 2.12 0 20 1.59 19200 0 11 0.00 0 12 0.16 0 15 0.00 28800 0 7 0.00 0 8 ? 3.55 0 10 ? 3.03 31250 0 6 5.33 0 7 0.00 0 9 ? 1.70 38400 0 5 0.00 0 6 ? 6.99 0 7 0.00 (mhz) 10 11.0592 12 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 177 ? 0.25 2 195 0.19 2 212 0.03 150 2 129 0.16 2 143 0.00 2 155 0.16 300 2 64 0.16 2 71 0.00 2 77 0.16 600 1 129 0.16 1 143 0.00 1 155 0.16 1200 1 64 0.16 1 71 0.00 1 77 0.16 2400 0 129 0.16 0 143 0.00 0 155 0.16 4800 0 64 0.16 0 71 0.00 0 77 0.16 9600 0 32 ? 1.36 0 35 0.00 0 38 0.16 14400 0 21 ? 1.36 0 23 0.00 0 25 0.16 19200 0 15 1.73 0 17 0.00 0 19 ? 2.34 28800 0 10 ? 1.36 0 11 0.00 0 12 0.16 31250 0 9 0.00 0 10 0.54 0 11 0.00 38400 0 7 1.73 0 8 0.00 0 9 ? 2.34 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 322 of 716 rej09b0398-0500 (mhz) 12.288 14 14.7456 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 217 0.08 2 248 ? 0.17 3 64 0.70 150 2 159 0.00 2 181 0.16 2 191 0.00 300 2 79 0.00 2 90 0.16 2 95 0.00 600 1 159 0.00 1 181 0.16 1 191 0.00 1200 1 79 0.00 1 90 0.16 1 95 0.00 2400 0 159 0.00 0 181 0.16 0 191 0.00 4800 0 79 0.00 0 90 0.16 0 95 0.00 9600 0 39 0.00 0 45 ? 0.93 0 47 0.00 14400 0 26 ? 1.23 0 29 1.27 0 31 0.00 19200 0 19 0.00 0 22 ? 0.93 0 23 0.00 28800 0 12 2.56 0 14 1.27 0 15 0.00 31250 0 11 2.40 0 13 0.00 0 14 ? 1.70 38400 0 9 0.00 0 10 3.57 0 11 0.00 (mhz) 16 17.2032 18 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 70 0.03 3 75 0.48 3 79 ? 0.12 150 2 207 0.16 2 223 0.00 2 233 0.16 300 2 103 0.16 2 111 0.00 2 116 0.16 600 1 207 0.16 1 223 0.00 1 233 0.16 1200 1 103 0.16 1 111 0.00 1 116 0.16 2400 0 207 0.16 0 223 0.00 0 233 0.16 4800 0 103 0.16 0 111 0.00 0 116 0.16 9600 0 51 0.16 0 55 0.00 0 58 ? 0.69 14400 0 34 ? 0.79 0 36 0.90 0 38 0.16 19200 0 25 0.16 0 27 0.00 0 28 1.02 28800 0 16 2.12 0 18 ? 1.75 0 19 ? 2.34 31250 0 15 0.00 0 16 1.20 0 17 0.00 38400 0 12 0.16 0 13 0.00 0 14 ? 2.34 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 323 of 716 rej09b0398-0500 (mhz) 18.432 19.6608 20 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 81 ? 0.22 3 86 0.31 3 88 ? 0.25 150 2 239 0.00 2 255 0.00 3 64 0.16 300 2 119 0.00 2 127 0.00 2 129 0.16 600 1 239 0.00 1 255 0.00 2 64 0.16 1200 1 119 0.00 1 127 0.00 1 129 0.16 2400 0 239 0.00 0 255 0.00 1 64 0.16 4800 0 119 0.00 0 127 0.00 0 129 0.16 9600 0 59 0.00 0 63 0.00 0 64 0.16 14400 0 39 0.00 0 42 ? 0.78 0 42 0.94 19200 0 29 0.00 0 31 0.00 0 32 ? 1.36 28800 0 19 0.00 0 20 1.59 0 21 ? 1.36 31250 0 17 2.40 0 19 ? 1.70 0 19 0.00 38400 0 14 0.00 0 15 0.00 0 15 1.73 (mhz) 22 22.1184 24 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 97 ? 0.35 3 97 0.19 3 106 ? 0.44 150 3 71 ? 0.54 3 71 0.00 3 77 0.16 300 2 142 0.16 2 143 0.00 2 155 0.16 600 2 71 ? 0.54 2 71 0.00 2 77 0.16 1200 1 142 0.16 1 143 0.00 1 155 0.16 2400 1 71 ? 0.54 1 71 0.00 1 77 0.16 4800 0 142 0.16 0 143 0.00 0 155 0.16 9600 0 71 ? 0.54 0 71 0.00 0 77 0.16 14400 0 47 ? 0.54 0 47 0.00 0 51 0.16 19200 0 35 ? 0.54 0 35 0.00 0 38 0.16 28800 0 23 ? 0.54 0 23 0.00 0 25 0.16 31250 0 21 0.00 0 21 0.54 0 23 0.00 38400 0 17 ? 0.54 0 17 0.00 0 19 ? 2.34 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 324 of 716 rej09b0398-0500 (mhz) 24.576 25.8048 26 bit rate (bits/s) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 108 0.08 3 114 ? 0.40 3 114 0.36 150 3 79 0.00 3 83 0.00 3 84 ? 0.43 300 2 159 0.00 2 167 0.00 2 168 0.16 600 2 79 0.00 2 83 0.00 2 84 ? 0.43 1200 1 159 0.00 1 167 0.00 1 168 0.16 2400 1 79 0.00 1 83 0.00 1 84 ? 0.43 4800 0 159 0.00 0 167 0.00 0 168 0.16 9600 0 79 0.00 0 83 0.00 0 84 ? 0.43 14400 0 52 0.63 0 55 0.00 0 55 0.76 19200 0 39 0.00 0 41 0.00 0 41 0.76 28800 0 26 ? 1.23 0 27 0.00 0 27 0.76 31250 0 24 ? 1.70 0 25 ? 0.75 0 25 0.00 38400 0 19 0.00 0 20 0.00 0 20 0.76 (mhz) 27.0336 28 bit rate (bits/s) n n error ( % ) n n error ( % ) 110 3 119 0.00 3 123 0.23 150 3 87 0.00 3 90 0.16 300 2 175 0.00 2 181 0.16 600 2 87 0.00 2 90 0.16 1200 1 175 0.00 1 181 0.16 2400 1 87 0.00 1 90 0.16 4800 0 175 0.00 0 181 0.16 9600 0 87 0.00 0 90 0.16 14400 0 58 ? 0.56 0 60 ? 0.39 19200 0 43 0.00 0 45 ? 0.93 28800 0 28 1.15 0 29 1.27 31250 0 26 0.12 0 27 0.00 38400 0 21 0.00 0 22 ? 0.93 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 325 of 716 rej09b0398-0500 table 12.4 bit rates and brr settings in clocked synchronous mode (mhz) 4 8 10 12 bit rate (bits/s) n n n n n n n n 110 3 141 250 2 249 3 124 3 155 3 187 500 2 124 2 249 3 77 3 93 1k 1 249 2 124 2 155 2 187 2.5k 1 99 1 199 1 249 2 74 5k 0 199 1 99 1 124 1 149 10k 0 99 0 199 0 249 1 74 25k 0 39 0 79 0 99 0 119 50k 0 19 0 39 0 49 0 59 100k 0 9 0 19 0 24 0 29 250k 0 3 0 7 0 9 0 11 500k 0 1 0 3 0 4 0 5 1m 0 0 * 0 1 ? ? 0 2 2.5m 0 0 * 0 0 * 5m 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 326 of 716 rej09b0398-0500 (mhz) 16 20 24 28 bit rate (bits/s) n n n n n n n n 110 250 3 249 500 3 124 3 155 3 187 3 218 1k 2 249 3 77 3 93 3 108 2.5k 2 99 2 124 2 149 2 174 5k 1 199 1 249 2 74 2 87 10k 1 99 1 124 1 149 1 174 25k 0 159 0 199 0 239 1 69 50k 0 79 0 99 0 119 0 139 100k 0 39 0 49 0 59 0 69 250k 0 15 0 19 0 23 0 27 500k 0 7 0 9 0 11 0 13 1m 0 3 0 4 0 5 0 6 2.5m ? ? 0 1 ? ? 0 2 5m 0 0 * ? ? 0 1 7m ? ? 0 0 * legend: blank: no setting available ? : setting possible, but error occurs notes: settings with an error of 1 % or less are recommended. * continuous transmission/reception is not possible. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 327 of 716 rej09b0398-0500 the brr setting is calculated as follows: asynchronous mode: n = 10 6 ? 1 64 2 2n ? 1 b synchronous mode: n = 10 6 ? 1 64 2 2n ? 1 b legend: b: bit rate (bit/s) n: baud rate generator brr setting (0 n 255) : operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the following table for the clock sources and value of n.) smr settings n clock source cks1 cks2 0 0 0 1 /4 0 1 2 /16 1 0 3 /64 1 1 the bit rate error in asynchronous mode is calculated as follows: error ( % ) = ? 1 100 (n + 1) b 64 2 2n ? 1 10 6 ? ? ? ? ? ? table 12.5 indicates the maximum bit rates in the asynchronous mode when the baud rate generator is being used for various frequencies. tables 12.6 and 12.7 show the maximum rates for external clock input. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 328 of 716 rej09b0398-0500 table 12.5 maximum bit rates for various frequencies with baud rate generator (asynchronous mode) settings (mhz) maximum bit rate (bits/s) n n 4 125000 0 0 4.9152 153600 0 0 6 187500 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 11.0592 345600 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 18.432 576000 0 0 19.6608 614400 0 0 20 625000 0 0 22 687500 0 0 22.1184 691200 0 0 24 750000 0 0 24.576 768000 0 0 25.8048 806400 0 0 26 812500 0 0 27.0336 844800 0 0 28 875000 0 0 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 329 of 716 rej09b0398-0500 table 12.6 maximum bit rates during external clock input (asynchronous mode) (mhz) external input clock (m hz) maximum bit rate (bits/s) 4 1.0000 62500 4.9152 1.2288 76800 6 1.5000 93750 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 11.0592 2.7648 172800 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 18.432 4.6080 288000 19.6608 4.9152 307200 20 5.0000 312500 22 5.5000 343750 22.1184 5.5296 345600 24 6.0000 375000 24.576 6.1440 384000 25.8048 6.4512 403200 26 6.5000 406250 27.0336 6.7584 422400 28 7.0000 437500 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 330 of 716 rej09b0398-0500 table 12.7 maximum bit rates during external clock input (clock synchronous mode) (mhz) external input clock (m hz) maximum bit rate (bits/s) 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 22 3.6667 3666666.7 24 4.0000 4000000.0 26 4.3333 4333333.3 28 4.6667 4666666.7 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 331 of 716 rej09b0398-0500 12.3 operation 12.3.1 overview for serial communication, the sci has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. asynchronous/clock synchronous mode and the transmission format are selected in the seri al mode register (smr), as shown in table 12.8. the sci clock source is selected by the c/ a bit in the serial mode register (smr) and the cke1 and cke0 bits in the serial control register (scr), as shown in table 12.9. asynchronous mode: ? data length is selectable: seven or eight bits. ? parity and multiprocessor bits are selectable, as well as the stop bit length (one or two bits). these selections determine the transm it/receive format and character length. ? in receiving, it is possible to de tect framing errors (fer), parity errors (per), overrun errors (orer), and the break state. ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator clock, and can output a clock with a frequency matching the bit rate. ? when an external clock is sel ected, the external clock input must have a frequency 16 times the bit rate. (the on-chip baud rate generator is not used.) clock synchronous mode: ? the communication format has a fixed 8-bit data length. ? in receiving, it is possible to detect overrun errors (orer). ? an internal or external clock can be selected as the sci clock source. ? when an internal clock is selected, the sci operates using the on-chip baud rate generator clock, and outputs a synchronous clock signal to external devices. ? when an external clock is selected, the sci operates on the input synchronous clock. the on-chip baud rate generator is not used. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 332 of 716 rej09b0398-0500 table 12.8 smr settings and sci communication formats smr settings sci communication format mode bit 7 c/ a bit 6 chr bit 5 pe bit 2 mp bit 3 stop data length parity bit multipro- cessor bit stop bit length asynchronous 0 0 0 0 0 8-bit not set not set 1 bit 1 2 bits 1 0 set 1 bit 1 2 bits 1 0 0 7-bit not set 1 bit 1 2 bits 1 0 set 1 bit 1 2 bits 0 * 1 0 8-bit not set set 1 bit * 1 2 bits 1 * 0 7-bit 1 bit asynchronous (multiprocessor format) * 1 2 bits clock synchronous 1 * * * * 8-bit not set none note: asterisks ( * ) in the table indicate don't-care bits. table 12.9 smr and scr settings and sci clock so urce selection smr scr settings sci transmit/receive clock mode bit 7 c/ a bit 1 cke1 bit 0 cke0 clock source sck pin function * asynchronous 0 0 0 internal sci does not use the sck pin 1 outputs a clock with frequency matching the bit rate 1 0 external 1 inputs a clock with frequency 16 times the bit rate 1 0 0 internal outputs the synchronous clock clock synchronous 1 1 0 external inputs the synchronous clock 1 note: * select the function in combination with the pin function controller (pfc). 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 333 of 716 rej09b0398-0500 12.3.2 operation in asynchronous mode in the asynchronous mode, each transmitted or recei ved character begins with a start bit and ends with a stop bit. serial communication is synchronized one character at a time. the transmitting and receiving sections of the sci are independent, so full duplex communication is possible. the transmitter and receiver are both do uble buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. figure 12.2 shows the general format of asynchronous serial communication. in asynchronous serial communication, the communica tion line is normally held in the marking (high) state. the sci monitors the line and starts serial communication when th e line goes to the space (low) state, indicating a start bit. one serial character consists of a start bit (low), data (lsb first), parity bit (high or low), and stop bit (high), in that order. when receiving in the asynchronous mode, the sci synchronizes on the falling edge of the start bit. the sci samples each data bit on the eighth pul se of a clock with a frequency 16 times the bit rate. receive data is latched at the center of each bit. 0 d0d1d2d3d4d5d6d7 1 1 0/1 1 1 (lsb) (msb) serial data start bit 1 bit transmit/receive data 7 or 8 bits one unit of communication data (characters or frames) idling (marking state) parity bit stop bit 1 or no bit 1 or 2 bits figure 12.2 data format in asynchronous communication (example: 8-bit data with parity and two stop bits) 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 334 of 716 rej09b0398-0500 transmit/receive formats: table 12.10 shows the 12 communication formats that can be selected in the asynchronous mode. the format is selected by settings in the serial mode register (smr). table 12.10 serial communication formats (asynchronous mode) smr bits serial transmit/receive format and frame length chr pe mp stop 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 0 start 8-bit data stop 0 0 0 1 start 8-bit data stop stop 0 1 0 0 start 8-bit data p stop 0 1 0 1 start 8-bit data p stop stop 1 0 0 0 start 7-bit data stop 1 0 0 1 start 7-bit data stop stop 1 1 0 0 start 7-bit data p stop 1 1 0 1 start 7-bit data p stop stop 0 ? 1 0 start 8-bit data mpb stop 0 ? 1 1 start 8-bit data mpb stop stop 1 ? 1 0 start 7-bit data mpb stop 1 ? 1 1 start 7-bit data mpb stop stop legend: start: start bit stop: stop bit p: parity bit mpb: multiprocessor bit ? : don't care clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the sci tran smit/receive clock. the clock source is selected by the c/ a bit in the serial mode register (smr) and bits cke1 and cke0 in the serial control register (scr) (table 12.9). 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 335 of 716 rej09b0398-0500 when an external clock is input at the sck pin, it must have a frequency equal to 16 times the desired bit rate. when the sci operates on an internal clock, it can output a clock signal at the sck pin. the frequency of this output clock is equal to the bit rate. the phase is aligned as in figure 12.3 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 d0d1d2d3d4d5d6d70/1 1 1 1 frame figure 12.3 output clock and communication data phase relationship (asynchronous mode) data transmit/receive operations sci initialization (asynchronous mode): before transmitting or receiving, clear the te and re bits to 0 in the serial control register (scr), then initialize the sci as follows. when changing the operation mode or communicati on format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets tdre to 1 and initializes the transmit shift register (tsr). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags and receive data register (r dr), which retain their previous contents. when an external clock is used, the clock should not be stopped during initia lization or subsequent operation. sci operation becomes unreliable if the clock is stopped. figure 12.4 is a sample flowchart for initializing th e sci. the procedure is as follows (the steps correspond to the numbers in the flowchart): 1. select the clock source in th e serial control register (scr). leave rie, tie, teie, mpie, te and re cleared to 0. if clock output is selected in asynchronous mode, clock output starts immediately after the setting is made to scr. 2. select the communication format in the serial mode register (smr). 3. write the value corresponding to the bit rate in the bit rate register (brr) unless an external clock is used. 4. wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scr) to 1. also set rie, tie, teie and mpie as necessary. setting te or re enables the sci to use the txd or rxd pin. the initial states are the marking transmit state, and the idle receive state (waiting for a start bit). 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 336 of 716 rej09b0398-0500 initialize clear te and re bits to 0 in scr set cke1 and cke0 bits in scr (te and re bits are 0) select transmit/receive format in smr set value to brr wait set te or re to 1 in scr; set rie, tie, teie, and mpie as necessary 1-bit interval elapsed? end 1 2 3 4 no yes figure 12.4 sample flowchart for sci initialization transmitting serial data (asynchronous mode): figure 12.5 shows a sample flowchart for transmitting serial data. the procedure is as follows (the steps correspond to the numbers in the flowchart): 1. sci initialization: set the txd pin using the pfc. 2. sci status check and transmit data write: read th e serial status register (ssr), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr) and clear tdre to 0. 3. continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in tdr, then clear tdre to 0. when the dmac or the dtc is started by a transmit-data-empty interrupt request (txi) in order to write data in tdr, the tdre bit is checked a nd cleared automatically. 4. to output a break at the end of serial transmission, first clear the port data register (dr) to 0, then clear the te to 0 in scr and use the pfc to establish the txd pin as an output port. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 337 of 716 rej09b0398-0500 start transmitting initialize read tdre bit in ssr read tend bit in ssr clear te bit in scr to 0; select thetxd pin as an output port with the pfc tend = 1? end transmission 1 2 3 no yes tdre = 1? write transmission data to tdr and clear tdre bit in ssr to 0 all data transmitted? no yes output break signal? no yes set dr = 0 4 yes no figure 12.5 sample flowchart for transmitting serial data 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 338 of 716 rej09b0398-0500 in transmitting serial data, the sci operates as follows: 1. the sci monitors the tdre bit in the ssr. wh en tdre is cleared to 0, the sci recognizes that the transmit data register (tdr) contains new data, and loads this data from the tdr into the transmit shift register (tsr). 2. after loading the data from the tdr into the tsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) is set to 1 in the scr, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits of data are output, lsb first. c. parity bit or multiprocessor bit: one parity bit (even or odd parity) or one multiprocessor bit is output. formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. stop bit: one or two 1 bits (stop bits) are output. e. marking: output of 1 bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci loads new data from the tdr into the tsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit to 1 in the ssr, outputs the stop bit, then continues output of 1 bits (marking). if the transmit-end interrupt enable bit (teie) in the scr is set to 1, a transmit-end interrupt (tei) is requested. figure 12.6 shows an example of sci transmit operation in the asynchronous mode. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 339 of 716 rej09b0398-0500 01 1 1 0/1 0 1 tdre tend parity bit parity bit serial data start bit data stop bit start bit data stop bit idle (markin g state) txi interrupt request txi interrupt handler writes data in tdr and clears tdre to 0 txi request tei interrupt request 1 frame d0 d1 d7 d0 d1 d7 0/1 example: 8-bit data with parity and one stop bit figure 12.6 sci transmit operation in asynchronous mode receiving serial data (asynchronous mode): figures 12.7 (1) and (2) show a sample flowchart for receiving serial data. the procedure is as follo ws (the steps correspond to the numbers in the flowchart). 1. sci initialization: set the rxd pin using the pfc. 2. receive error handling and break detection: if a receive error occurs, read the orer, per, and fer bits of the ssr to identify the error. after executing the necessary error handling, clear orer, per, and fer all to 0. receiving cannot resume if orer, per or fer remain set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. 3. sci status check and receive-dat a read: read the serial status re gister (ssr), check that rdrf is set to 1, then read receive data from the receive data register (rdr) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. 4. continue receiving serial data: read the rd r and rdrf bit and clear rdrf to 0 before the stop bit of the current frame is received. if th e dmac is started by a receive-data-full interrupt (rxi) to read rdr, the rdrf bit is cleared automatically so this step is unnecessary. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 340 of 716 rej09b0398-0500 start reception initialization read orer, per, and fer bits in ssr read reception data of rdr and clear rdrf bit in ssr to 0 end reception 1 4 no no yes yes read the rdrf bit in ssr rdrf = 1? per, fer, orer = 1? clear the re bit of scr to 0 yes no 3 error handling 2 all data received? figure 12.7 sample flowchart for receiving serial data (1) 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 341 of 716 rej09b0398-0500 start of error handling orer = 1? overrun error handling fer = 1? yes break? no framing error handling per = 1? yes parity error handling clear orer, per, and fer to 0 in ssr end clear re bit in scr to 0 no no no yes yes figure 12.7 sample flowchart for receiving serial data (2) 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 342 of 716 rej09b0398-0500 in receiving, the sci operates as follows: 1. the sci monitors the communication line. when it detects a start bit (0), the sci synchronizes internally and starts receiving. 2. receive data is shifted into the rsr in order from the lsb to the msb. 3. the parity bit and stop bit are received. af ter receiving these bits, the sci makes the following checks: a. parity check. the number of 1s in the receive data must match the even or odd parity setting of the o/e bit in the smr. b. stop bit check. the stop bit value must be 1. if there are two stop bits, only the first stop bit is checked. c. status check. rdrf must be 0 so that recei ve data can be loaded from the rsr into the rdr. if the data passes these checks, the sci sets rd rf to 1 and stores the received data in the rdr. if one of the checks fails (receive error), the sci operates as indicated in table 12.11. note: when a receive error occurs, further r eceiving is disabled. while receiving, the rdrf bit is not set to 1, so be sure to clear the error flags. 4. after setting rdrf to 1, if the receive-data-fu ll interrupt enable bit (r ie) is set to 1 in the scr, the sci requests a receive-data-full interrup t (rxi). if one of the error flags (orer, per, or fer) is set to 1 and the receive-data-fu ll interrupt enable bit (rie) in the scr is also set to 1, the sci requests a receive-error interrupt (eri). figure 12.8 shows an example of sci recei ve operation in the asynchronous mode. table 12.11 receive error co nditions and sci operation receive error abbreviation condition data transfer overrun error orer receiving of next data ends while rdrf is still set to 1 in ssr receive data not loaded from rsr into rdr framing error fer stop bit is 0 receive data loaded from rsr into rdr parity error per parity of receive data differs from even/odd parity setting in smr receive data loaded from rsr into rdr 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 343 of 716 rej09b0398-0500 tdrf fer framin g error g enerates eri interrupt request. 1 frame rxi interrupt handler reads data in rdr and clears rdrf to 0. 01 1 1 0/1 0 1 parity bit parity bit serial data start bit data stop bit start bit data stop bit idle (markin g state) d0 d1 d7 d0 d1 d7 0/1 rxi interrupt request example: 8-bit data with parity and one stop bit. figure 12.8 sci receive operation 12.3.3 multiprocessor communication the multiprocessor communication function enables several processors to share a single serial communication line for sending and receiving data. the processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). in multiprocessor communication, each receiving processor is addressed by a unique id. a serial communication cycle consists of an id-sending cycl e that identifies the receiving processor, and a data-sending cycle. the multiprocessor bit disti nguishes id-sending cycl es from data-sending cycles. the transmitting processor starts by sending the id of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. when they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their ids. the receiving processor with a matching id conti nues to receive further incoming data. processors with id s not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. multiple processors can send and receive data in this way. figure 12.9 shows the example of communication among processors using the multiprocessor format. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 344 of 716 rej09b0398-0500 communication formats: four formats are available. parity -bit settings are ignored when the multiprocessor format is selected. for details see table 12.8. clock: see the description in the asynchronous mode section. receiving processor a (id = 01) (id = 02) (id = 03) (id = 04) receiving processor b receiving processor c serial communication line h'01 h'aa (mpb = 0) (mpb = 1) id-transmit cycle: receiving processor address serial data mpb: example: multiprocessor bit sending data h'aa to receiving processor a transmitting processor receiving processor d data-transmit cycle: data sent to receiving processor specified by id figure 12.9 communication among processors using multiprocessor format transmitting multipro cessor serial data: figure 12.10 shows a sample flowchart for transmitting multiprocessor serial data. the procedure is as follows (the steps correspond to the numbers in the flowchart): 1. sci initialization: set the txd pin using the pfc. 2. sci status check and transmit data write: read th e serial status register (ssr), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr). also set mpbt (multiprocessor bit transfer) to 0 or 1 in ssr. finally, clear tdre to 0. 3. continue transmitting serial data: read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in tdr, then clear tdre to 0. when the dmac is started by a transmit-data-empty interrupt request (txi) to write data in tdr, the tdre bit is checked and cleared automatically. 4. output a break at the end of serial transmission: set the data register (dr) of the port to 0, then clear te to 0 in scr and set the txd pin function as output port with the pfc. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 345 of 716 rej09b0398-0500 tdre = 1? write transmit data in tdr and set mpbt in ssr all data transmitted? yes tend = 1? read tend bit in ssr output break signal? yes set dr = 0 clear te bit in scr to 0; select thetxd pin function as an output port with the pfc end transmission yes read tdre bit in ssr clear tdre bit to 0 initialization no no yes no no 1 2 3 4 start transmission figure 12.10 sample flowchart for tr ansmitting multiprocessor serial data 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 346 of 716 rej09b0398-0500 in transmitting serial data, the sci operates as follows: 1. the sci monitors the tdre bit in the ssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (tdr) contains new data, and loads this data from the tdr into the transmit shift register (tsr). 2. after loading the data from the tdr into the tsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) in the scr is set to 1, the sci requests a transmit-data-empty interrupt (txi) at this time. serial transmit data is transmitted in the following order from the txd pin: a. start bit: one 0 bit is output. b. transmit data: seven or eight bits are output, lsb first. c. multiprocessor bit: one multiprocessor bit (mpbt value) is output. d. stop bit: one or two 1 bits (stop bits) are output. e. marking: output of 1 bits continues until the start bit of the next transmit data. 3. the sci checks the tdre bit when it outputs the stop bit. if tdre is 0, the sci loads data from the tdr into the tsr, outputs the stop bit, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit in the ssr to 1, outputs the stop bit, then continues output of 1 bits in the marking state. if the transmit-end interrupt enable bit (teie) in the scr is set to 1, a transmit-end interrupt (tei) is requested at this time. figure 12.11 shows an example of sci receive operation in the multiprocessor format. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 347 of 716 rej09b0398-0500 tdre tend txi interrupt handler writes data in tdr and clears tdre to 0 txi interrupt request tei interrupt request 1 frame 01 1 1 0/1 0 1 multiprocessor bit multiprocessor bit serial data start bit data stop bit start bit data stop bit idle (markin g state) d0 d1 d7 d0 d1 d7 0/1 example: 8-bit data with multiprocessor bit and one stop bit txi interrupt request figure 12.11 sci multipro cessor transmit operation receiving multiprocessor serial data: figures 12.12 (1) and (2) show a sample flowchart for receiving multiprocessor serial data. the procedure for receiving multiprocessor serial data is listed below. 1. sci initialization: set the rxd pin using the pfc. 2. id receive cycle: set the mpie bit in the serial control register (scr) to 1. 3. sci status check and compare to id reception: r ead the serial status regi ster (ssr), check that rdrf is set to 1, then read data from the receive data register (rdr) and compare with the processor's own id. if the id does not match the receive data, set mpie to 1 again and clear rdrf to 0. if the id matches the receive data, clear rdrf to 0. 4. receive error handling and break detection: if a receive error occurs, read the orer and fer bits in ssr to identify the error. after execu ting the necessary error processing, clear both orer and fer to 0. receiving cannot resume if orer or fer remain set to 1. when a framing error occurs, the rxd pin can be read to detect the break state. 5. sci status check and data receiving: read ssr, check that rdrf is set to 1, then read data from the receive data register (rdr). 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 348 of 716 rej09b0398-0500 rdrf = 1 ? fer = 1 ? or orer =1 ? rdrf = 1 ? all data received ? no end reception yes set mpie bit in scr to 1 read rdrf bit of ssr initialization clear re bit in scr to 0 yes no 1 2 3 read orer and fer bits of ssr fer = 1 ? or orer =1 ? read rdrf bit in ssr read receive data from rdr is id the station's id no read orer and fer bits in ssr read receive data from rdr no error processin g no yes 5 4 yes yes no yes start reception figure 12.12 sample flow chart for receiving multip rocessor serial data (1) 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 349 of 716 rej09b0398-0500 orer = 1? break? yes framing error handling yes start error handling overrun error handling yes fer = 1? clear orer and fer bits in ssr to 0 end no no no clear re bit in scr to 0 figure 12.12 sample flow chart for receiving multip rocessor serial data (2) 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 350 of 716 rej09b0398-0500 figures 12.13 (1) and (2) show examples of sc i receive operation using a multiprocessor format. rdrf mpie rdr value id1 rxi interrupt request (multiprocessor interrupt), mpie = 0 rxi interrupt handler reads data in rdr and clears rdrf to 0 not station's id, so mpie is set to 1 a g ain no rxi interrupt, rdr maintains state 01 1 1 10 1 serial data start bit stop bit start bit stop bit idlin g (markin g ) d0 d1 d7 d0 d1 d7 0 mpb mpb mpb data (id1) data (data 1) figure 12.13 sci receive opera tion (id does not match) (1) 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 351 of 716 rej09b0398-0500 rdrf mpie rdr value id1 id2 01 1 1 10 1 mpb mpb serial data start bit data (id2) data (data 2) stop bit start bit stop bit idlin g (markin g ) d0 d1 d7 d0 d1 d7 0 rxi interrupt request (multiprocessor interrupt), mpie = 0 rxi interrupt handler reads data in rdr and clears rdrf to 0 station's id, so receivin g continues, with data received by the rxi interrupt processin g routine mpie bit is a g ain set to 1 mpb data2 example: own id matches data, 8-bit data with multiprocessor bit and one stop bit figure 12.13 example of sci r eceive operation (id matches) (2) 12.3.4 clock synchronous operation in the clock synchronous mode, the sci transmits and receives data in s ynchronization with clock pulses. this mode is suitable for high-speed serial communication. the sci transmitter and receiver are independent, so full duplex communication is possible while sharing the same clock. the transmitter and r eceiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. figure 12.14 shows the general format in clock synchronous serial communication. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 352 of 716 rej09b0398-0500 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 lsb msb synchroni- zation clock serial data * * transfer direction one unit (character or frame) of communication data note: * hi g h except in continuous transmittin g or receivin g . figure 12.14 data format in clock synchronous communication in clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. data are guaranteed valid at the rising edge of the serial clock. in each character, the serial data bits are transmitted in order from the lsb (first) to the msb (last). after output of the msb, the communication line remains in the state of the msb. in the clock synchronous mode, the sci tr ansmits or receives data by synchronizing with the falling edge of the synchronization clock. communication format: the data length is fixed at eight bits. no parity bit or multiprocessor bit can be added. clock: an internal clock generated by the on-chip baud rate generator or an external clock input from the sck pin can be selected as the sci tran smit/receive clock. the clock source is selected by the c/ a bit in the serial mode register (smr) and bits cke1 and cke0 in the serial control register (scr). see table 12.9. when the sci operates on an internal clock, it outputs the clock signal at the sck pin. eight clock pulses are output per transmitted or received ch aracter. when the sci is not transmitting or receiving, the clock signal re mains in the high state. note: an overrun error occurs only during the r eceive operation, and the sync clock is output until the re bit is cl eared to 0. when you want to perform a receive operation in one- character units, select external clock for the clock source. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 353 of 716 rej09b0398-0500 transmit/receive operations sci initialization (clock synchronous mode): before transmitting or receiving, software must clear the te and re bits to 0 in the serial contro l register (scr), then initialize the sci as follows. when changing the mode or communication format, always clear the te and re bits to 0 before following the procedure given below. clearing te to 0 sets tdre to 1 and initializes the transmit shift register (tsr). clearing re to 0, however, does not initialize the rdrf, per, fer, and orer flags and receive data register (rdr ), which retain their previous contents. figure 12.15 is a sample flowchart for initializing the sci. 1. select the clock source in th e serial control register (scr). leave rie, tie, teie, mpie, te, and re cleared to 0. 2. select the communication format in the serial mode register (smr). 3. write the value corresponding to the bit rate in the bit rate register (brr) unless an external clock is used. 4. wait for at least the interval required to transmit or receive one bit, then set te or re in the serial control register (scr) to 1. also set rie, tie, teie, and mpie. the txd, rxd pins becomes usable in response to the pfc corre sponding bits and the te, re bit settings. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 354 of 716 rej09b0398-0500 start of initialization clear te and re bits to 0 in scr 1-bit interval elapsed? set te and re to 1 in scr; set rie, tie, teie, and mpie bits yes no 1 set rie, tie, teie, mpie, cke1, and cke0 bits in scr (te and re are 0) end wait select transmit/receive format in smr set value in brr 2 3 4 figure 12.15 sample flowchart for sci initialization transmitting serial data (synchronous mode): figure 12.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. 1. sci initialization: set the txd pin function with the pfc. 2. sci status check and transmit data write: read ssr, check that the tdre flag is 1, then write transmit data in tdr and clear the tdre flag to 0. 3. to continue transmitting serial data: after checking that the tdre flag is 1, indicating that data can be written, write data in tdr, then clear the tdre flag to 0. when the dmac or dtc is activated by a transmit-data-empty interrupt request (txi) to write data in tdr, the tdre flag is checked an d cleared automatically. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 355 of 716 rej09b0398-0500 start transmitting read tdre flag in ssr tdre = 1? write transmit data in tdr and clear tdre flag to 0 in ssr all data transmitted? read tend flag in ssr yes no no no yes tend = 1? yes end clear te bit to 0 in scr initialize 2 3 1 figure 12.16 sample flowchart for serial transmitting 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 356 of 716 rej09b0398-0500 figure 12.17 shows an example of sci transmit operation. bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 synchroni- zation clock serial data transmit direction bit 7 txi interrupt handler writes data in tdr and clears tdre to 0 1 frame txi request txi request tdre tend lsb msb tei request figure 12.17 example of sci transmit operation sci serial transmission operates as follows. 1. the sci monitors the tdre bit in the ssr. when tdre is cleared to 0 the sci recognizes that the transmit data register (tdr) contains new data and loads this data from the tdr into the transmit shift register (tsr). 2. after loading the data from the tdr into the tsr, the sci sets the tdre bit to 1 and starts transmitting. if the transmit-data-empty interrupt enable bit (tie) in the scr is set to 1, the sci requests a transmit-data-empty interrupt (txi) at this time. if clock output mode is selected, the sci outputs eight synchronous clock pulses. if an external clock source is selected, the sci outputs data in synchronization with the input clock. data are output from the txd pin in order from the lsb (bit 0) to the msb (bit 7). 3. the sci checks the tdre bit when it outputs the msb (bit 7). if tdre is 0, the sci loads data from the tdr into the tsr, then begins serial transmission of the next frame. if tdre is 1, the sci sets the tend bit in the ssr to 1, transmits the msb, then holds the transmit data pin (txd) in the msb state. if the transmit-end interrupt enable bit (teie) in the scr is set to 1, a transmit-end interrupt (tei) is requested at this time. 4. after the end of serial transmission, the sck pin is held in the high state. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 357 of 716 rej09b0398-0500 receiving serial data (c lock synchronous mode): figures 12.18 (1) and (2) show a sample flowchart for receiving serial data. when switc hing from the asynchronous mode to the clock synchronous mode, make sure that orer, per, and fer are cleared to 0. if per or fer is set to 1, the rdrf bit will not be set and both transmitting and receiving will be disabled. the procedure for receiving se rial data is listed below: 1. sci initialization: set the rxd pin using the pfc. 2. receive error handling: if a receive error occurs, read the or er bit in ssr to identify the error. after executing the necessary error handling, clear orer to 0. transmitting/receiving cannot resume if orer remains set to 1. 3. sci status check and receive data read: read th e serial status register (ssr), check that rdrf is set to 1, then read receive data from the receive data register (rdr) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. 4. continue receiving serial data: read rdr, a nd clear rdrf to 0 before the frame msb (bit 7) of the current frame is received. if the dmac is started by a receive-data-full interrupt (rxi) to read rdr, the rdrf bit is cleared automatically so this step is unnecessary. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 358 of 716 rej09b0398-0500 start reception initialization read the orer bit of ssr all data received? end reception 1 no yes orer = 1? read receive data from rdr and clear rdrf bit of ssr to 0 rdrf = 1? yes yes no clear re bit of scr to 0 no read rdrf bit of ssr error processing 3 4 2 figure 12.18 sample flowch art for serial receiving (1) 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 359 of 716 rej09b0398-0500 error handling end clear orer bit of ssr to 0 overrun error processing figure 12.18 sample flowch art for serial receiving (2) figure 12.19 shows an example of the sci receive operation. bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 synchroni- zation clock serial data transfer direction bit 7 read data with rxi interrupt processin g routine and clear rdrf bit to 0 1 frame rxi request rxi request eri interrupt request g enerated by overrun error rdrf orer figure 12.19 example of sci receive operation 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 360 of 716 rej09b0398-0500 in receiving, the sci operates as follows: 1. the sci synchronizes with serial clock input or output and initializes internally. 2. receive data is shifted into the rsr in or der from the lsb to the msb. after receiving the data, the sci checks that rdrf is 0 so that r eceive data can be loaded from the rsr into the rdr. if this check passes, the sci sets rdrf to 1 and stores the received data in the rdr. if the check does not pass (receive error), the sci operates as indicated in table 12.11 and no further transmission or reception is possible. if the error flag is set to 1, the rdrf bit is not set to 1 during reception, even if the rdrf bit is 0 cleared. when restarting reception, be sure to clear the error flag. 3. after setting rdrf to 1, if the receive-data-fu ll interrupt enable bit (r ie) is set to 1 in the scr, the sci requests a receive-data-full interrupt (rxi). if the orer bit is set to 1 and the receive-data-full interrupt enable bit (rie) in the scr is also set to 1, the sci requests a receive-error interrupt (eri). transmitting and receiving serial data simultaneously (clock synchronous mode): figure 12.20 shows a sample flowchart for transmitting and receiving serial data simultaneously. the procedure is as follows (the steps correspond to the numbers in the flowchart): 1. sci initialization: set the txd and rxd pins using the pfc. 2. sci status check and transmit data write: read th e serial status register (ssr), check that the tdre bit is 1, then write transmit data in the transmit data register (tdr) and clear tdre to 0. the txi interrupt can also be used to determine if the tdre bit has changed from 0 to 1. 3. receive error handling: if a receive error occurs, read the or er bit in ssr to identify the error. after executing the necessary error processing, clear orer to 0. transmitting/receiving cannot resume if orer remains set to 1. 4. sci status check and receive data read: read th e serial status register (ssr), check that rdrf is set to 1, then read receive data from the receive data register (rdr) and clear rdrf to 0. the rxi interrupt can also be used to determine if the rdrf bit has changed from 0 to 1. 5. continue transmitting and receiving serial data: read the rdrf bit and rdr, and clear rdrf to 0 before the frame msb (bit 7) of the current frame is received. also read the tdre bit to check whether it is safe to write (if it reads 1); if so, write data in tdr, then clear tdre to 0 before the msb (bit 7) of the current frame is transmitted. when the dmac is started by a transmit-data-empty interrupt request (txi) to write data in tdr, the tdre bit is checked and cleared automatically. when the dmac is started by a receive-dat a-full interrupt (rxi) to read rdr, the rdrf bit is cleared automatically. note: in switching from transmitting or receivi ng to simultaneous transmitting and receiving, simultaneously clear the te bit and re bit to 0, then simultaneously set the te bit and re bit to 1. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 361 of 716 rej09b0398-0500 start transmitting/receive initialization read tdre bit in ssr all data transmitted/and received end transmission/reception 1 2 no yes tdre = 1? write transmission data in tdr and clear tdre bit of ssr to 0 rdrf = 1? yes no clear te and re bits of scr to 0 yes no read orer bit of ssr error handling 3 orer = 1? yes read receive data of rdr, and clear rdrf bit of ssr to 0 read rdrf bit of ssr 4 5 no figure 12.20 sample flowchart for serial transmission 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 362 of 716 rej09b0398-0500 12.4 sci interrupt sources and the dmac the sci has four interrupt sources: transmit-end (tei), receive-error (eri), receive-data-full (rxi), and transmit-data-empty (txi). table 12.12 lists the interrupt sources and indicates their priority. these interrupts can be enabled and disabled by the tie, rie, and teie bits in the serial control register (scr). each interrupt request is sent separately to the interrupt controller. txi is requested when the tdre b it in the ssr is set to 1. txi can start the direct memory access controller (dmac) to transfer data. tdre is automatically cleared to 0 when the dmac writes data in the transmit data register (tdr). rxi is requested when the rdrf bit in the ssr is set to 1. rxi can start the dmac to transfer data. rdrf is automatically clear ed to 0 when the dmac reads th e receive data register (rdr). eri is requested when the orer, per, or fer bit in the ssr is set to 1. eri cannot start the dmac. tei is requested when the tend bit in the ssr is set to 1. tei cannot st art the dmac. where the txi interrupt indicates that transmit data writing is enabled, the tei interrupt indicates that the transmit operation is complete. table 12.12 sci interrupt sources interrupt source description dmac activation priority eri receive error (orer, per, or fer) no high rxi receive data full (rdrf) yes txi transmit data empty (tdre) yes tei transmit end (tend) no low 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 363 of 716 rej09b0398-0500 12.5 usage notes sections 12.5.1 through 12.5.9 provide information for using the sci. 12.5.1 tdr write and tdre flags the tdre bit in the serial status register (ssr) is a status flag indicating loading of transmit data from tdr into tsr. the sci sets tdre to 1 when it transfers data from tdr to tsr. data can be written to tdr regardless of the tdre bit status. if new data is written in tdr when tdre is 0, however, the old data stored in tdr will be lost because the data has not yet been transferred to the tsr. before writing transmit data to the tdr, be sure to check that tdre is set to 1. 12.5.2 simultaneous multiple receive errors table 12.13 indicates the state of the ssr stat us flags when multiple receive errors occur simultaneously. when an overrun error occurs, the rsr contents cannot be transferred to the rdr, so receive data is lost. table 12.13 ssr status flags and transfer of receive data ssr status flags receive error status rdrf orer fer per receive data transfer rsr rdr overrun error 1 1 0 0 x framing error 0 0 1 0 o parity error 0 0 0 1 o overrun error + framing error 1 1 1 0 x overrun error + parity error 1 1 0 1 x framing error + parity error 0 0 1 1 o overrun error + framing error + parity error 1 1 1 1 x note: o = receive data is transferred from rsr to rdr. x = receive data is not transferred from rsr to rdr. 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 364 of 716 rej09b0398-0500 12.5.3 break detectio n and processing break signals can be detected by reading the rx d pin directly when a framing error (fer) is detected. in the break state, the input from the rxd pin consists of all 0s, so fer is set and the parity error flag (per) may also be set. in the br eak state, the sci receiver continues to operate, so if the fer bit is cleared to 0, it will be set to 1 again. 12.5.4 sending a break signal the txd pin becomes a general i/o pin with the i/o direction and level determined by the i/o port data register (dr) and pin function controller (pfc) control register (cr). these conditions allow break signals to be sent. the dr value is substitu ted for the marking status until the pfc is set. consequently, the output port is set to initially output a 1. to send a break in serial transmission, first clear the dr to 0, then establish the txd pin as an output port using the pfc. when te is cleared to 0, the transmission section is initialized regardless of the present transmission status. 12.5.5 receive error flags and transmitter operation (clock sync hronous mode only) when a receive error flag (orer, per, or fer) is set to 1, the sci will not start transmitting even if tdre is set to 1. be su re to clear the receive error flags to 0 before starting to transmit. note that clearing re to 0 does not clear the receive error flags. 12.5.6 receive data sampling timing and receive margin in the asynchronous mode in the asynchronous mode, the sci operates on a base clock of 16 times the bit rate frequency. in receiving, the sci synchronizes internally with the falling edge of the start bit, which it samples on the base clock. receive data is latched on the ri sing edge of the eighth base clock pulse (figure 12.21). 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 365 of 716 rej09b0398-0500 078150781505 internal base clock receive data (rxd) synchronization sampling timing data sampling timing 8 clocks 16 clocks start bit ? 7.5 clocks +7.5 clocks d0 d1 figure 12.21 receive data samplin g timing in asynchronous mode the receive margin in the asynchronous mode can therefore be expressed as: m = 0.5 ? 1 2n d ? 0.5 n ? (l ? 0.5)f ? (1 + f) 100 % legend: m : receive margin ( % ) n : ratio of clock frequency to bit rate (n = 16) d : clock duty cycle (d = 0 ? 1.0) l : frame length (l = 9 ? 12) f : absolute deviation of clock frequency from the equation above, if f = 0 and d = 0.5 the receive margin is 46.875 % : d = 0.5, f = 0 m = (0.5 ? 1/(2 16)) 100 % = 46.875 % this is a theoretical value. a reasonable marg in to allow in system designs is 20 to 30 % . 12. serial communication interface (sci) rev.5.00 sep. 27, 2007 page 366 of 716 rej09b0398-0500 12.5.7 constraints on dmac use ? when using an external clock source for the synchronization clock, update the tdr with the dmac, and then after five system clocks or mo re elapse, input a transmit clock. if a transmit clock is input in the first four system clocks after the tdr is written, an error may occur (figure 12.22). ? before reading the receive data register (rdr ) with the dmac, select the receive-data-full interrupt (rxi) of the sci as a start-up source. d0 d1 d2 d3 d4 d5 d6 d7 sck tdre t note: during external clock operation, an error may occur if t is 4 or less. figure 12.22 example of clock synchronous transmission with dmac 12.5.8 cautions for clock synchronous external clock mode ? set te = re = 1 only when the external clock sck is 1. ? do not set te = re = 1 until at least four clocks after the external clock sck has changed from 0 to 1. ? when receiving, rdrf is 1 when re is set to zero 2.5 to 3.5 clocks after the rising edge of the rxd d7 bit sck input, but it cannot be copied to rdr. 12.5.9 caution for clock synchronous internal clock mode when receiving, rdrf is 1 when re is set to zer o 1.5 clocks after the rising edge of the rxd d7 bit sck output, but it cannot be copied to rdr. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 367 of 716 rej09b0398-0500 section 13 high speed a/d converter ? sh7014 ? 13.1 overview the high speed a/d converter has 10-bit resolution, and can select from a maximum of eight channels of analog inputs. 13.1.1 features the high speed a/d converter has the following features: ? 10-bit resolution ? eight input channels ? high-speed conversion ? minimum conversion time: 2.9 s per channel (for 28-mhz operation) 1.4 s per channel during continuous conversion ? multiple conversion modes ? select mode/group mode ? single mode/scan mode ? buffered operation possible ? 2 channel simultaneous sampling possible ? two types of conversion start ? software, or timer conversion start trigger (mtu) can be selected. ? eight data registers ? conversion results stored in 16-bit data registers corresponding to each channel. ? sample and hold function ? a/d conversion end interrupt generation ? an a/d conversion end interrupt (adi) request can be generated on completion of a/d conversions 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 368 of 716 rej09b0398-0500 13.1.2 block diagram figure 13.1 is the block diagram of the high speed a/d converter. + ? av cc av ss an0 an1 an2 an3 an4 an5 an6 an7 d/a conversion circuit s&h a s&h b addra addrb addrc addrd addre addrf addrg addrh adcr adcsr internal data bus bus i/f interrupt signal adi mtu conversion start trigger cmp module internal data bus control logic multiplexer legend: adcr: adcsr: addra: addrb: addrc: addrd: a/d control register a/d control status register a/d data register a a/d data register b a/d data register c a/d data register d cmp: s&h: addre: addrf: addrg: addrh: comparator array sample and hold circuit a/d data register e a/d data register f a/d data register g a/d data register h figure 13.1 high speed a/d converter block diagram 13.1.3 pin configuration table 13.1 shows the input pins used by the high speed a/d converter. the av cc and av ss pins are for the high speed a/d conve rter internal analog section power supply. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 369 of 716 rej09b0398-0500 table 13.1 pin configuration pin abbreviation i/o function analog supply av cc i analog section power supply analog ground av ss i analog section ground and a/d conversion reference voltage analog input 0 an0 i analog input channel 0 analog input 1 an1 i analog input channel 1 analog input 2 an2 i analog input channel 2 analog input 3 an3 i analog input channel 3 analog input 4 an4 i analog input channel 4 analog input 5 an5 i analog input channel 5 analog input 6 an6 i analog input channel 6 analog input 7 an7 i analog input channel 7 13.1.4 register configuration table 13.2 shows the configuration of the high speed a/d converter registers. table 13.2 register configuration name abbreviation r/w initial value address access size a/d data register a addra r h'0000 h'ffff83f0 8,16 a/d data register b addrb r h'0000 h'ffff83f2 a/d data register c addrc r h'0000 h'ffff83f4 a/d data register d addrd r h'0000 h'ffff83f6 a/d data register e addre r h'0000 h'ffff83f8 a/d data register f addrf r h'0000 h'ffff83fa a/d data register g addrg r h'0000 h'ffff83fc a/d data register h addrh r h'0000 h'ffff83fe a/d control/status register adcsr r/(w) * h'00 h'ffff83e0 a/d control register adcr r/w h'00 h'ffff83e1 note: * only 0 can be written to bit 7 to clear the flag. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 370 of 716 rej09b0398-0500 13.2 register descriptions 13.2.1 a/d data registers a to h (addra to addrh) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ad9 ad8 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ad7 ad6 ad5 ad 4 ad3 ad2 ad1 ad0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r the addr are 16-bit read only registers for storing a/d conversion results. there are eight of these registers, addra through addrh. the a/d converted data is 10-bit data which is sent to the addr for the corresponding converted channel for storage. the lower 8 b its of the a/d converted data are transferred to and stored in the lower byte (bits 7 to 0) of the addr, and the upper 2 bits are stored into the upper byte (bits 9, 8). bits 15 to 10 always read as 0. data reads can be either byte or word. the upper 8 bits of the converted data are transferred upon byte data read s. additionally, buffered operation is possible by combining addra to addrd. table 13.3 shows the correspondence between the analog input channels and the addr. the addr are initialized to h'0000 by power-on reset or in standby mode. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 371 of 716 rej09b0398-0500 table 13.3 analog input channel and addr correspondence analog input channel a/d data register an0 addra * an1 addrb * an2 addrc * an3 addrd * an4 addre an5 addrf an6 addrg an7 addrh note: * except during buffer operation 13.2.2 a/d control/status register (adcsr) bit: 7 6 5 4 3 2 1 0 adf adie adst cks grp ch2 ch1 ch0 initial value: 0 0 0 0 0 0 0 0 r/w: r/(w) * r/w r/w r/w r/w r/w r/w r/w note: * only 0 can be written to bit 7 to clear the flag. the adcsr is an 8-bit read/wr ite register used for a/d conversion operation control and to indicate status. the adcsr is initialized to h'00 by power-on reset or in standby mode. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 372 of 716 rej09b0398-0500 bit 7 ? a/d end flag (adf): this status flag indicates that a/d conversion has ended. bit 7 adf description 0 [clear conditions] (initial value) ? with adf = 1, by reading the adf flag then writing 0 in adf ? when the dmac is activated by an adi interrupt 1 [set conditions] ? single mode: when a/d conversion ends after conversion for all designated channels (during buffer operation, this is not set until operation of the specified buffer has ended) ? scan mode: after one round of a/d conversion for all specified channels bit 6 ? a/d interrupt enable (adie): enables or disables interrupt requests (adi) after a/d conversion ends. set the adie bit while conversion is suspended. bit 6 adie description 0 disables interrupt requests (adi) after a/d conversion ends (initial value) 1 enables interrupt requests (adi) after a/d conversion ends bit 5 ? a/d start (adst) : selects start or stop for a/d conversion. a 1 is maintained during a/d conversions. the adst bit can be set to 1 by software, or timer conversion start triggers. bit 5 adst description 0 a/d conversion halted (initial value) 1 ? single mode: start a/d conversion. automatically cleared to 0 after conversion for the designated channel ends. ? scan mode: start a/d conversion. continuous conversion until 0 cleared by software. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 373 of 716 rej09b0398-0500 bit 4 ? clock select (cks): sets the a/d conversion time. set so that the conversion time is 2 s or greater in proportion to the operating frequency. make conversion time changes only while conversion is halted. bit 4 cks description 0 conversion time = 40 states (high speed a/d converter standard clock = /2) (initial value) 1 conversion time = 80 states (when /4 is selected) bit 3 ? group mode (grp): designates either select mode or group mode for the a/d conversion channel selection. set the grp bit only while conversion is halted. bit 3 grp description 0 select mode (initial value) 1 group mode bits 2 to 0 ? channel select 2 to 0 (ch2 to ch0): these bits, along with the grp bit, select the analog input channel. set the input channel only while conversion is halted. description bit 2 ch2 bit 1 ch1 bit 0 ch0 select mode (grp = 0) group mode (grp = 1) 0 0 0 an0 (initial value) an0 1 an1 an0 to an1 1 0 an2 an0 to an2 1 an3 an0 to an3 1 0 0 an4 an0 to an4 1 an5 an0 to an5 1 0 an6 an0 to an6 1 an7 an0 to an7 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 374 of 716 rej09b0398-0500 13.2.3 a/d control register (adcr) bit: 7 6 5 4 3 2 1 0 ? pwr trgs1 trgs0 scan dsmp bufe1 bufe0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w the adcr is an 8-bit read/write register used for a/d conversion operation control. the adcr is initialized to h'00 by power-on reset or in standby mode. bit 7 ? reserved: this bit always reads as 0. the write value should always be 0. bit 6 ? power (pwr): designates the conversion start mode for the high speed a/d converter. setting the pwr bit to 1 sets high speed start mode, and a 0 sets to low power conversion mode. see section 13.4.7, conversion start modes fo r details on the conversion start operation. set the pwr bit only while conversion is halted. bit 6 pwr description 0 low power conversion mode (initial value) 1 high speed start mode bits 5 and 4 ? timer trigger select 1, 0 (trgs1, trgs0): these bits enable or prohibit a/d conversion starts by trigger signals. set the trgs1, trgs0 bits only while conversion is halted. bit 5 trgs1 bit 4 trgs0 description 0 0 enable a/d conversion start by software (initial value) 1 enables a/d conversion start by mtu conversion start trigger 1 0 reserved 1 reserved 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 375 of 716 rej09b0398-0500 bit 3 ? scan mode (scan): selects either single mode or scan mode for the a/d conversion operation mode. see section 13.4, operation, for de tails on single mode and scan mode operation. set the scan bit only while conversion is halted. bit 3 scan description 0 single mode (initial value) 1 scan mode bit 2 ? simultaneous sampling (dsmp): enables or disables the simultaneous sampling of two channels. see section 13.4.6, simultaneous sa mpling operation, for details on simultaneous sampling. set the dsmp bit only while conversion is halted. bit 2 dsmp description 0 normal sampling operation (initial value) 1 simultaneous sampling operation bits 1 and 0 ? buffer enable 1, 0 (bufe1, bufe0): these bits select whether to use the addrb to addrd as buffer registers. set the bufe1 and bufe0 bits only while conversion is halted. bit 1 bufe1 bit 0 bufe0 description 0 0 normal operation (initial value) 1 addra and addrb buffer operation: conversion result addra addrb (addrb is the buffer register) 1 0 addra and addrc, also addrb and addrd buffer operation: conversion result 1 addra addrc, conversion result 2 addrb addrd (addrc and addrd are buffer registers) 1 addra to addrd buffer operation: conversion result addra addrb addrc addrd (addrb to addrd are buffer registers) 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 376 of 716 rej09b0398-0500 13.3 bus master interface the addra to addrh are 16-bit registers with a 16-bit width data bus to the bus master. the bus master can read from addra to addrh in either word or byte units. when an addr is read in word units, the addr cont ents are transferred to the bus master 16 bits at a time. in byte unit reads, the contents of the most significant eight bits (ad9 to ad2) of the converted data (ad9 to ad0) are transferred to the bus master. figures 13.2 (1) and (2) show an example of the addr read operation. 0 0 0 0 0 0 ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 ad 1 ad 0 upper 8 bits internal data bus bus i/f data register word data read lower 8 bits figure 13.2 addr read operation (1) 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 377 of 716 rej09b0398-0500 0 0 0 0 0 0 ad 9 ad 8 ad 7 ad 6 ad 5 ad 4 ad 3 ad 2 ad 1 ad 0 upper 8 bits internal data bus bus i/f byte data read data register figure 13.2 addr read operation (2) 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 378 of 716 rej09b0398-0500 13.4 operation ? the high speed a/d converter has 10-bit resolution. ? in addition to the four operating modes of select or group, and single or scan can be set in combination with buffer operation. ? select mode uses one channel and group mode selects multiple channels. ? one start in the single mode performs conversions on all selected channels, and one start in the scan mode performs repeated c onversions until stopped by software. ? in buffer operation, the previous conversion result is saved in a buffer register at the end of a conversion for the relevant channel. ? in simultaneous sampling operation, the analog input voltages of two channels are sampled simultaneously then converted in order. ? software, a timer conversion start trigger (mtu) can be selected as the conversion start condition. ? high speed start mode or low power conversion mode can be selected for a/d conversion using the pwr bit setting. ? when changing the operation mode or input channel, rewrite the adcsr, adcr while the adst bit is cleared to 0. af ter rewriting the adcsr, adcr, a/d conversion will be restarted when the adst bit is set to 1. operation mode or input channel changes can be made simultaneously with adst bit setting. when stopping an a/d conversion before completion, 0 clear the adst bit. 13.4.1 select-single mode choose select-single mode when doing a/d conversions for one channel only. when the adst bit is set to 1, a/d conversion is started according to the designated conversion start conditions. the adst bit is held to 1 during the a/d conversion and is automatically cleared to 0 upon completion. the adf flag is also set to 1 at the end of conversion. if the adie bit is set to 1 at this time, an adi interrupt request is generated. the adf flag is cleared by reading the adcsr, then writing a 0. figure 13.3 shows an example of operation in th e select-single mode when an1 is selected. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 379 of 716 rej09b0398-0500 addrb addra channel 3 channel 2 channel 1 channel 0 adst adf addrc addrd automatic clear sampling 1 conversion standby conversion standby conversion standby conversion standby conversion standby a/d conversion 1 conversion result 1 set to 1 by software figure 13.3 high speed a/d converter operation exam ple (select-single mode) 13.4.2 select-scan mode choose select-scan mode when doing repeated a/d conversions for one channel. this is useful when doing continuous monitoring of the analog input of one channel. when the adst bit is set to 1, a/d conversion is started according to the designated conversion start conditions. the adst bit is held to 1 until 0 cleared by software. a/d conversion for the selected input channel is repeated during that interval. the adf flag is set to 1 at the end of the first conversion. at this point, if the adie bit is set, an adi interrupt request is issued, and the high speed a/d converter is halted. with the high speed a/d converter in stop mode due to an adi interrupt request, conversion is restarted when the adf flag is cleared to 0. the adf flag is cleared by readin g the adcsr then writing a 0. figure 13.4 shows an example of operation in the select-scan mode wh en an1 is selected. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 380 of 716 rej09b0398-0500 addrb addra channel 3 channel 2 channel 1 channel 0 adst adf addrc addrd sampling 3 sampling 6 a/d conversion 5 sampling 1 a/d conver- sion 1 a/d conver- sion 3 conver- sion standby a/d conver- sion 2 sampling 2 sampling 4 sampling 5 a/d conver- sion 4 conversion standby conversion standby set to 1 by software cleared to 0 by software conversion standby conversion standby conversion stopped conver- sion result 1 conver- sion result 2 conver- sion result 3 conver- sion result 4 figure 13.4 high speed a/d converter operation ex ample (select-scan mode) 13.4.3 group-single mode choose group-single mode when doing a/ d conversions for multiple channels. when the adst bit is set to 1, a/d conversion is started according to the designated conversion start conditions. the adst bit is held to 1 during a/d conversion and is automatically cleared to 0 when all conversions for the designated input channels are completed. the adf flag is set to 1 when all conversions for the designated input channels are completed. if the adie bit is set to 1 at this time, an adi interr upt request is generated. the adf flag is cleared by reading the adcsr then writing a 0. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 381 of 716 rej09b0398-0500 figure 13.5 shows an example of operation in the group-single mode when an0 to an2 are selected. addrb addra channel 3 channel 2 channel 1 channel 0 adst adf addrc addrd sampling 1 sampling 2 sampling 3 a/d conversion 1 a/d conversion 2 a/d conversion 3 conversion standby conversion standby conversion standby conversion standby conversion standby conversion standby conversion standby automatic clear set to 1 by software conversion result 1 conversion result 2 conversion result 3 figure 13.5 high speed a/d converter operation exam ple (group-single mode) 13.4.4 group-scan mode choose group-scan mode when doing repeated a/ d conversions for multiple channels. this is useful when doing continuous monitoring of the analog inputs of multiple channels. when the adst bit is set to 1, a/d conversion is started according to the designated conversion start conditions. the adst bit is held to 1 until 0 cleared by software. a/d conversion for the selected input channels is repeated during that interval. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 382 of 716 rej09b0398-0500 the adf flag is set to 1 at the completion of the first conversions of all the designated input channels. at this point, if the adie bit is set to 1, an adi interrupt request is issued, and the high speed a/d converter is temporarily halted. with the high speed a/d converter in stop mode due to an adi interrupt request, conversion is restarted wh en the adf flag is clear ed to 0. the adf flag is cleared by reading the adcsr, then writing a 0. figure 13.6 shows an example of operation in the group-scan mode when an0 to an2 are selected. addrb addra channel 3 channel 2 channel 1 channel 0 adst adf addrc addrd sam- plin g 1 sam- plin g 4 sam- plin g 2 conver- sion standby conversion standby sam- plin g 5 sam- plin g 3 sam- plin g 6 a/d conver- sion 1 a/d conver- sion 4 a/d conver- sion 2 a/d conver- sion 5 a/d conver- sion 3 conversion standby conversion standby conversion standby conver- sion standby conver- sion standby cleared to 0 by software set to 1 by software conversion result 1 conversion result 4 conversion result 5 conversion result 2 conversion result 3 conver- sion stopped figure 13.6 high speed a/d converter operation ex ample (group-scan mode) 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 383 of 716 rej09b0398-0500 13.4.5 buffer operation when conversion ends on the relevant channel, the conversion result is stored in the addr, and simultaneously, the previously stored result is tr ansferred to another addr. buffer operation can be selected from the following: ? an0 addra addrb (two-stage, one-group operation) ? an0 addra addrc, an1 addrb addrd (two-stage, two-group operation) ? an0 addra addrb addrc addrd (four-stage, one-group operation) to use in combination with simultaneous sampling, set grp = 1, bufe1, bufe0 = b'10 and ch2 = 0. buffer operation timing is shown in figure 13.7. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 384 of 716 rej09b0398-0500 addrb addra channel 1 channel 0 adst adf addrd addrc channel 2 channel 3 sampling 1 sampling 3 sampling 2 sampling 4 sampling 5 a/d conver- sion 1 a/d conver- sion 3 a/d conver- sion 2 a/d conver- sion 4 conversion standby conversion standby conversion standby conversion standby conver- sion standby cleared to 0 by software set to 1 by software conver- sion result 1 conver- sion result 2 conver- sion result 3 conver- sion result 4 conver- sion result 1 conver- sion result 2 conver- sion result 3 figure 13.7 buffer operation example (select scan mode: two-stage one-group operation, when ch2 to ch0 = b'001) buffer-only operation: when performing conversion only on the analog input channels specified by the bufe1 and bufe0 bits, select group mode, and you can select the adf flag setting conditions with the ch2 to ch0 bits. table 13.4 shows conversion during buffer operation and adf flag setting conditions. the adf flag is set at the point in the table when the final conversion has ended. in single mode, conversion is halted after the adf flag is set to 1. in scan mode, conversion continues, and the converted data is stored in sequence in the buffer registers specified by the bufe1 and bufe0 bits. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 385 of 716 rej09b0398-0500 when the adf flag is set to 1, if the adie bit is also set to 1, an adi interrupt is issued. after the adcsr is read, the adf flag is cleared by a 0 write. with select single mode, the high speed a/d converter goes into standby mode at the end of every conversion cycle. the high speed a/d converter is restarted by software, or a timer trigger. when the number of conversion cycles shown in table 13.4 have ended, the adf flag is set to 1. table 13.4 conversion channel and adf flag setting/clearing conditions during buffer operation 1 channel setting sampling channel ch2 ch1 ch0 bufe1, bufe0 = b'01 bufe1, bufe0 = b'10 bufe1, bufe0 = b'11 0 0 0 an0 1 time (addra) an0, an1 1 time (addrb) an0 1 time (addra) 1 an0 2 times (addrb) an0 2 times (addrb) 1 0 * an0, an1 2 times (addrd) an0 3 times (addrc) 1 * an0 4 times (addrd) 1 ? ? * * * note: * see table 13.5. combined group mode and buffer operation: continuous conversion is possible on analog input channels (an0 and an1) specified by bits bufe1 and bufe0 as well as an4 to an7 due to setting of bits ch2 to ch0. table 13.5 shows conversion during buffer operation and adf flag setting conditions. the adf flag is set at the point in the table when the fina l conversion has ended. in this case, conversion is performed on the analog input corresponding with the addr specified in the buffer register. for example, when bufe1 and bufe0 = b'11 and ch2 to ch0 = b'110, conversion results are stored in addra and addre to addrg. also, contents of addra to addrc before the start of conversion are transferred to addrb to addrd. in single mode, conversion is halted after the adf flag has been set to 1. conversion continues in scan mode. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 386 of 716 rej09b0398-0500 table 13.5 conversion channel and adf flag setting/clearing conditions during buffer operation 2 channel setting sampling channel ch2 ch1 ch0 bufe1, bufe0 = b'01 bufe1, bufe0 = b'10 bufe1, bufe0 = b'11 0 0 ? * * * 1 0 an0, an2 (addrc) 1 an0, an2, an3 (addrd) 1 0 0 an0, an2 to an4 (addre) an0, an1, an4 (addre) an0, an4 (addre) 1 an0, an2 to an5 (addrf) an0, an1, an4, an5 (addrf) an0, an4, an5 (addrf) 1 0 an0, an2 to an6 (addrg) an0, an1, an4 to an6 (addrg) an0, an4 to an6 (addrg) 1 an0, an2 to an7 (addrh) an0, an1, an4 to an7 (addrh) an0, an4 to an7 (addrh) note: * see table 13.4. adf flag clearing: when the dmac is started up due to an a/d conversion end interrupt, the adf flag is cleared when the addr specified in table 13.4 or 13.5 has been read. resetting the number of buffer operations: clear the bufe1 and bufe0 bits to b'00 in conversion standby mode or when the converter has been halted. the number of buffer operations is cleared to 0. updating buffer operations: clear the bufe1 and bufe0 bits to b'00 in conversion standby mode or when the converter has been halted. thereafter, set bufe1 and bufe0, and the buffer operations shown in table 13.4 and 13.5 are performed when conversion is resumed. 13.4.6 simultaneous sampling operation with simultaneous sampling, continuous conversion is conducted with sampling of the input voltages on two channels at the same time. simultaneous sampling is valid in group mode. channels for sampling are determined by the ch2 and ch1 bits of the rdscr. the combinations are shown in table 13.6. for example, if grp = 1 when ch2 and ch1 = b'11, sampling occurs in order in the following pairs: an0, an1 an2, an3 an4, an5 an6, an7. sampling timing is shown in figure 13.9. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 387 of 716 rej09b0398-0500 table 13.6 simultaneous sampling channels channel setting ch2 ch1 sampling channels, grp 1 0 0 an0, an1 1 an0, an1 an2, an3 1 0 an0, an1 an2, an3 an4, an5 1 an0, an1 an2, an3 an4, an5 an6, an7 addrb addra adst adf addrd addrc automatically cleared channel 0 channel 1 channel 2 channel 3 sampling 1 a/d conver- sion 1 a/d conver- sion 2 conver- sion standby conversion standby conversion standby conversion standby conver- sion standby sampling 2 conver- sion standby conver- sion standby set to 1 by software conversion result 1 conversion result 2 figure 13.8 simultaneous sampling operation (group single mode) 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 388 of 716 rej09b0398-0500 13.4.7 conversion start modes the conversion start mode of the high speed a/d converter is set by the pwr bit of the adcsr. when the pwr bit is cleared to 0, low-power conversion mode is set and the internal analog circuit becomes inactive. high-speed start mode is set by setting the pwr bit to 1, and the analog circuit becomes active. in the low-power conversion mode, power is applied to the analog circuitry simultaneous to the conversion start (adst set). when 200 cycles of the reference clock have elapsed, conversion becomes possible for the analog circuit and the first a/d conversion begins. when performing consecutive conversions, the second and later conversions are executed in 20 cycles. select the basic clock with the cks bit of the adcsr. when the a/d conversion ends, adst is cleared to 0 and the analog circuit power supply is automati cally cut off. because th e analog circuit is only active during the a/d conversion operation period in this mode, current consumption can be reduced. in high-speed start mode, adst is cleared to 0 when a/d conversion ends. power continues to be supplied to the analog circuitry, and conversion-ready status is maintained. conversion is restarted immediately by resetting adst to 1. however, the first conversion after power-on begins 200 cycles after setting adst. clear the pwr bit to 0 to switch off the analog power supply. when performing consecutive conversions, the second and later conversions are executed in 20 cycles. because the analog circuit is alwa ys active in this mode, a/d c onversion can be executed at high speed. when a/d conversion is forcibly halted by clearing the adst bit to 0 during conversion in high- speed start mode (when adst = 1), the first conversion following a restart may not be performed normally. the second and subsequent conversions are performed normally. figures 13.9 and 13.10 show the timing of the conversion start operation. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 389 of 716 rej09b0398-0500 figures 13.9 and 13.10 show examples of conversion start operation timing. addrb addra channel 0 channel 1 channel 2 channel 3 adst adf addrd addrc set to 1 by software analog circuit power supply 200 cycles set clear sam- pling 1 sam- pling 2 sam- pling 3 a/d conver- sion 1 a/d conver- sion 2 a/d conver- sion 3 conver- sion standby conver- sion standby conver- sion standby conver- sion standby cleared to 0 by software conversion result 1 conversion result 2 conversion result 3 figure 13.9 conversion start opera tion (low-power conversion mode) 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 390 of 716 rej09b0398-0500 addrb addra channel 1 channel 0 adst adf addrd addrc set to 1 by software analog circuit power supply switched off by software channel 2 channel 3 set to 1 by software sam- pling 1 sam- pling 2 a/d conver- sion 1 a/d conver- sion 2 conversion result 1 conversion result 2 conversion standby conversion standby conversion standby conversion standby 200 cycles switched on by software (pwr set to 1) (pwr set to 0) figure 13.10 conversion start operation (high-speed start mode) 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 391 of 716 rej09b0398-0500 13.4.8 a/d conversion time the high speed a/d converter has an on-chip sample and hold circuit. the high speed a/d converter samples the input at time t d after the adst bit is set to 1, and then starts the conversion. the a/d conversion time t conv is the sum of the conversion start delay time t d , the input sampling time t spl , and the operating time t cp . this conversion time is not a set value, but is decided by the t d adcsr write timing, or the timer conversion start trigger generation timing. figure 13.11 shows an example of a/d conversion timing. table 13.7 lists a/d conversion times. address write si g nal adst samplin g timin g adf t d t conv t spl t cp le g end: t d : t spl : t conv : t cp : a/d conversion start delay time input samplin g time a/d conversion time operation time figure 13.11 a/d conversion timing 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 392 of 716 rej09b0398-0500 table 13.7 a/d conversion times cks = 0 cks = 1 time symbol min typ max min typ max a/d conversion start delay time t d 1.5 1.5 1.5 1.5 1.5 1.5 input sampling time t spl 20 20 20 40 40 40 a/d conversion time t conv 42.5 42.5 42.5 82.5 82.5 82.5 notes: 1. unit: states 2. table entries are for when pwr = 1. if 200 states have not elapsed since the adst bit has been set, no conversions are done until after those 200 states have occurred. when pwr = 0, add 200 states to the first a/d conversion start delay time. when two or more conversions are performed in succession, tcp is 20 cycles when cks = 0, and 40 cycles when cks = 1. the cks bit of the adcsr is the operation time t conv , but set so that this is 2 s or greater. table 13.8 shows the operating frequency and cks bit settings. table 13.8 operating frequency and cks bit settings minimum conversion time ( s) cks conversion time (states) 28 mhz 20 mhz 16 mhz 10 mhz 8 mhz 0 42.5 ? 2.1 2.6 4.3 5.3 1 82.5 2.9 4.2 5.0 8.3 10.3 note: the indication " ? " means the setting is not available. 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 393 of 716 rej09b0398-0500 13.5 interrupts the high speed a/d converter generates an a/d conversion end interrupt (adi) upon completion of a/d conversions. the adi interrupt request can be enabled or disabled by the adie bit of the adcsr. the dmac can be activated by adi interrupts. when converted data is read by the dmac upon an adi interrupt, consecutive conversions can be done without software responsibility. table 13.9 lists the high speed a/d converter interrupt sources. during scan mode, if the adie bit is set to 1, a/d conversion is temporarily suspended immediately when the adf flag is set to 1. a/d conversion is restarted when the adf flag is cleared to 0. when the dmac is activated by an adi interrupt, the adf flag is cleared to 0 when the final specified data register is read. table 13.9 high speed a/d converter interrupt sources interrupt source description dmac activation adi interrupt caused by conversion end possible 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 394 of 716 rej09b0398-0500 13.6 usage notes note the following points concerning the high speed a/d converter. 13.6.1 analog input voltage range during a/d conversions, see that the voltage applied to the analog input pins an0 to an7 is within the range of av ss an0 to an7 av cc . 13.6.2 av cc , av ss input voltages the av cc , av ss input voltages should be av cc = v cc 10 % , and av ss = v ss . when not using the high speed a/d converter, make av cc = v cc and av ss = v ss . when in standby mode, make v ram av cc 5.5 v, and av ss = v ss . v ram is the ram standby voltage. 13.6.3 input ports make the time constant of circuitry connected to an input port shorter than the high speed a/d converter sampling time. if the time constant of th e circuit is longer, there will be occasions where the input voltage is not adequately sampled. 13.6.4 conversion start modes current consumption will be different for the a/d conversion operation in high speed start mode and low-power conversion mode according to the pwr bit setting. 13.6.5 a/d conversion termination (hd6417014r only) if conversion is terminated while in progress (when adst = 1) in high-speed start mode (pwr = 1) by clearing the adst bit, there may be a larg e degree of error in the first conversion following the restart (on channel 1 in normal mode, or channel 2 in simultaneous sampling mode). subsequent conversions will be performed normally if a/d conversion is terminated while in progress, use one of the following methods to solve this problem: (a) ignore the first data following a restart after termination. (b) if the first data after a restart is used, perfo rm a single dummy conversion in single mode after the termination, terminate a/d conversion, then restart. (c) after termination, write 0 to the pwr bit before restarting. (in this case, the first conversion after the restart will begin after the elapse of 200 a/d reference clock cycles.) 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 395 of 716 rej09b0398-0500 13.6.6 handling of analog input pins to prevent damage from surges and other abnormal voltages at the analog input pins (an0 to an7), connect a protection circuit such as that shown in figure 13.12. this circuit also includes a cr filter function that suppresses error due to noise. the circuit shown here is only a design example; circuit constants must be decided on the basis of the actual operating conditions. figure 13.13 shows an equivalent circuit for the analog input pins, and table 13.10 summarizes the analog input pin specifications. 100 0.1 f avcc an0 to an7 avss sh7014 10 f 0.01 f note: * * figure 13.12 example of analog input pin protection circuit analo g multiplexer an0 to an7 1.0 k 20 pf 1 m hi g h speed a/d converter note: numeric values are reference values. figure 13.13 analog input pin equivalent circuit 13. high speed a/d converter ? sh7014 ? rev.5.00 sep. 27, 2007 page 396 of 716 rej09b0398-0500 table 13.10 analog input pin specifications item min max unit analog input capacitance ? 20 pf permissible signal source impedance ? 1 k 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 397 of 716 rej09b0398-0500 section 14 mid-speed a/d converter ? sh7016, sh7017 ? 14.1 overview the mid-speed a/d converter has 10 bit resolution, and can select from a maximum of eight channels of analog input. 14.1.1 features the mid-speed a/d converter has the following features: ? 10-bit resolution ? eight input channels ? conversion time ? minimum conversion time: per channel: 6.7 s (20mhz) ? multiple conversion modes: single mode/scan mode ? single mode: 1 channel a/d conversion ? 1 to 4 channel simultaneous conversion ? four 16-bit data registers ? the results of a/d conversion are transferred to and held in the data register for the relevant channel. ? sample and hold function ? a/d conversion end interrupt generation ? an a/d conversion end interrupt (adi) can be generated on completion of a/d conversion. ? a/d conversion can be started by mtu trigger input. 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 398 of 716 rej09b0398-0500 14.1.2 block diagram figure 14.1 is the block diagram of the mid-speed a/d converter. adcr adcsr addrd addrc addrb addra + ? av cc av ss an0 an1 an2 an3 an4 an5 an6 an7 le g end: adcr: adcsr: addra: addrb: addrc: addrd: a/d control re g ister a/d control status re g ister a/d data re g ister a a/d data re g ister b a/d data re g ister c a/d data re g ister d interrupt si g nal adi /16 /8 mtu tri gg er module data bus internal data bus 10-bit d/a continuous comparison re g ister bus interface analo g multiplexer sample & hold circuit conparator control circuit a/d converter figure 14.1 mid-speed a/ d converter block diagram 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 399 of 716 rej09b0398-0500 14.1.3 pin configuration table 14.1 shows the input pins used with the mid-speed a/d converter. the eight analog input pins are divided into two groups, with analog input pins 0 to 3 (an0 to an3) comprising group 0, and analog input pins 4 to 7 (an4 to an7) comprising group 1. the av cc and av ss pins are for the mid-speed a/d conv erter internal analog section power supply. table 14.1 pin configuration pin abbreviation i/o function analog supply av cc i analog section power supply analog ground av ss i analog section ground and a/d conversion standard voltage analog input 0 an0 i analog input group 0 analog input 1 an1 i analog input 2 an2 i analog input 3 an3 i analog input 4 an4 i analog input group 1 analog input 5 an5 i analog input 6 an6 i analog input 7 an7 i 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 400 of 716 rej09b0398-0500 14.1.4 register configuration table 14.2 shows the register configuration of the mid-speed a/d converter. table 14.2 register configuration name abbreviation r/w initial value address access size a/d data register ah addrah r h'00 h'ffff8420 8, 16 a/d data register al addral r h'00 h'ffff8421 8 a/d data register bh addrbh r h'00 h'ffff8422 8, 16 a/d data register bl addrbl r h'00 h'ffff8423 8 a/d data register ch addrch r h'00 h'ffff8424 8, 16 a/d data register cl addrcl r h'00 h'ffff8425 8 a/d data register dh addrdh r h'00 h'ffff8426 8, 16 a/d data register dl addrdl r h'00 h'ffff8427 8 a/d control/status register adcsr r/(w) * h'00 h'ffff8428 8, 16 a/d control register adcr r/w h'7f h'ffff8429 8, 16 note: * only 0 can be written to bit 7 to clear the flag. 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 401 of 716 rej09b0398-0500 14.2 register descriptions 14.2.1 a/d data register a to d (addra to addrd) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ?????? 0000000000000000 r addrn : r/w : r r r r r r r r r r r r r r r note: n = a to d initial value : bit : a/d registers are special registers that read stored results of a/d conversion in 16 bits. there are four registers: addra to addrd. the a/d converted data is 10 bit data which is to the addr of the corresponding converted channel for storage. the upper 8 bits of the a/d converted data correspond to the upper byte of the addr and the lower 2 bits correspond to the lower byte. bits 5 to 0 of the lower byte of addr are reserved and always read 0. analog input ch annels and correspondence to addr are shown in table 14.3. addr can always be read from the cpu. the upper byte may be read directly. the lower byte is transferred through the temporary register (temp) . for details, see section 14.3, interface with cpu. addr is initialized to h'0000 during power-on reset. table 14.3 analog input channel and addra to addrd correspondence analog input channel group group 1 a/d data register an0 an4 addra an1 an5 addrb an2 an6 addrc an3 an7 addrd 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 402 of 716 rej09b0398-0500 14.2.2 a/d control/status register (adcsr) adie adf adst scan cks ch2 ch1 ch0 76543210 00000010 r/w : r/(w) * r/w r/w r/w r/w r/w r/w r/w bit : initial value : note: * only 0 can be written to clear the fla g . the a/d control/status register (adcsr) is register that can read/write in 8 bits and control mid- speed a/d converter operations such as mode selection. the adcsr is initialized to h'00 during power-on reset. bit 7 ? a/d end flag (adf): status flag that indicates end of a/d conversion. bit 7 adf description 0 [clear conditions] (initial value) 1. writing 0 to adf after reading adf with adf = 1 2. when registers of the mid-speed converter are accessed after the dmac is activated by adi interrupt. 1 [set conditions] 1. single mode: when a/d conversion is complete 2. scan mode: when a/d conversion of all designated channels are complete bit 6 ? a/d interrupt enable (adie): enables or disables interrupt request (adi) due to completion of a/d conversion. bit 6 adie description 0 disables interrupt request (adi) due to completion of a/d conversion (initial value) 1 enables interrupt request (adi) due to completion of a/d conversion 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 403 of 716 rej09b0398-0500 bit 5 ? a/d start (adst): selects start/end of a/d conversion. a 1 is maintained during a/d conversion start. it is also possible to set a 1 by the mtu trigger input. bit 5 adst description 0 a/d conversion halted (initial value) 1 1. single mode: starts a/d conversion. automatically clears to 0 when conversion of the designated channel is complete 2. scan mode: starts a/d conversion. continuous conversion until cleared to 0 by the software bit 4 ? scan mode (scan): selects the a/d conversion mode from single mode and scan mode. for operations during single/scan mode, see section 14.4, operation. when switching modes, proceed while adst = 0. bit 4 scan description 0 single mode (initial value) 1 scan mode bit 3 ? clock select (cks): sets the a/d conversion time. pr oceed conversion time switch while adst = 0. always set cks = 0 when operating frequency exceeds 20mhz. bit 3 cks description 0 conversion time = 266 states (max) (initial value) 1 conversion time = 134 states (max) bits 2 to 0 ? channel select 2 to 0 (ch2 to ch0): selects the analog input channel along with the scan bit. switch channels while adst = 0. 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 404 of 716 rej09b0398-0500 group selection channel selection description ch2 ch1 ch0 single mode scan mode 0 0 0 an0 (initial value) an0 (initial value) 1 an1 an0, an1 1 0 an2 an0 to an2 1 an3 an0 to an3 1 0 0 an4 an4 1 an5 an4, an5 1 0 an6 an4 to an6 1 an7 an4 to an7 14.2.3 a/d control register (adcr) ? trge ????? ? 76543210 01111111 r/w : r/w r r r r r r r initial value : bit : a/d control register (adcr) is register that can read/write in 8 bits and enables or disables a/d conversion start of the mtu trigger input. adcr is initialized to h'7f during power-on reset. bit 7 ? trigger enable (trge): enables or disables a/d conversion start of input from mtu trigger. bit 7 trge description 0 disables a/d conversion start of mtu trigger (initial value) 1 starts a/d conversion on mtu trigger. bits 6 to 0 ? reserved bits: these bits always read as 1. the write value should always be 1. 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 405 of 716 rej09b0398-0500 14.3 interface with cpu although a/d data regi ster addra to addrd are 16-bit register s, the bus width within the chip that integrates with the cpu is 8-bits. so, the lower byte data is read through the temporary register (temp). the upper byte data can be read directly. the procedure for reading data from addr is as follows: first, read the upper byte data from addr. at this time, the upper byte data is read dir ectly into the cpu and the lower byte data is transferred to temp of the mid-sp eed a/d converter. next, read the lower byte to read the temp contents into the cpu. when reading the addr in byte size, read the upper byte before the lower byte. furthermore, it is possible to read only the upper byte, however, please note that contents are not guaranteed when reading only the lower byte. in this case, addr can be read from the upper-byte address with a word transfer instruction (such as mov.w). figure 14.2 shows the data flow when reading from addr. 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 406 of 716 rej09b0398-0500 cpu (h'aa) addrnh (h'aa) addrnl (h'40) temp (h'40) cpu (h'40) addrnh (h'aa) addrnl (h'40) temp (h'40) 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 407 of 716 rej09b0398-0500 14.4 operation the mid-speed converter operates using the contin uous comparison method and is equipped with 10-bit resolution. operations for the single and scan modes are explained below. 14.4.1 single mode (scan = 0) the single mode is selected wh en executing a/d conversion for one channel only. a/d conversion is initiated when the adst bit of the a/d control/status register is set to 1 by the software or external trigger input. the adst bit is held to 1 during the a/d conversion and is automatically cleared to 0 upon completion. when conversion is complete, the adf bit of adcsr is set to 1. at this time, if the adie bit of adcsr is 1, adi interrupt request occurs. the adf bit can be cleared by writing 0 after reading adf = 1. to switch modes or analog input channels during a/d conversion, clear the adst bit to 0 and stop a/d conversion to avoid malfunction. afte r switching (mode/channel change and adst bit setting can be made at the same time), set the adst bit to 1 to restart a/d conversion. an example of operation when channel 1 (an1) is selected in the single mode is shown in figure 14.3. 1. set operation mode to single mode (scan = 0), input channel to an1 (ch2 = ch1 = 0, ch0 = 1) and a/d interrupt request to enable (adie = 1) then start a/d conversion (adst = 1). 2. when a/d conversion is complete, a/d conve rsion result is transferred to addrb. at the same time, adf = 1 will become adf = 0 a nd the mid-speed converter will standby for conversion. 3. since adf = 1 and adie = 1, adi interrupt request will occur. 4. the a/d interrupt process routine will start. 5. after reading adf = 1, write 0 to adf. 6. read the a/d conversion result (addrb) and process. 7. end a/d interrupt process routine execution. when adst bit is set to 1, a/d conversion starts, following steps (2) to (7) above. 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 408 of 716 rej09b0398-0500 adie adst adf addra addrb addrc addrd note: * indicates command execution by the software set * set * set * clear * a/d conversion start clear * channel 3 (an3) operation state channel 0 (an0) operation state channel 1 (an1) operation state channel 2 (an2) operation state conversion standby conversion standby conversion standby conversion standby conversion standby conversion standby a/d conversion (1) a/d conversion (2) readin g conversion result readin g conversion result a/d conversion result (1) a/d conversion result (2) figure 14.3 operation exampl e of mid-speed a/d converter (single mode, channel 1 selected) 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 409 of 716 rej09b0398-0500 14.4.2 scan mode (scan = 1) the scan mode is optimal for monitoring analog input of multiple channels (including channel 1). a/d conversion is started from channel 1 (an0 for ch2 = 0 and an4 for ch1 = 1) of the group when the adst bit of the a/d control/status register (adcsr) is set to 1 by the software or external trigger input. when multiple channels are selected, a/d conve rsion of channel 2 (an1 or an5) is initiated immediately after completion of the channel 1 conversion. a/d conversion is performed repeatedly on the se lected channels until the adst bit is cleared to 0. the results of conversion are transferred to and held in the addr registers for the relevant channels. to switch modes or analog input channels during a/d conversion, clear the adst bit to 0 and stop a/d conversion to avoid malfunction. afte r switching (mode/channel change and adst bit setting can be made at the same time), set adst bit to 1 to restart a/d conversion from channel 1. an example of operation in scan mode when three channels of group 0 (an0 to an2) are selected for a/d conversion is shown in figure 14.4. 1. set the operation mode to scan mode (scan = 1), set the scan group to group 0 (ch2 = 0), set the analog channels to an0 to an2 (ch1 = 1, ch0 = 0), and then start a/d conversion (adst = 1). 2. when a/d conversion for channel 1 (an0) is complete, a/d conversion result is transferred to addra. next, channel 2 (an1) will automatically be selected and conversion will begin. 3. in the same manner, channel 3 (an2) will be converted. 4. when conversion of all of the selected ch annels (an0 to an2) are complete, adf will become 1 and channel 1 (an0) will again be selected and conversion will begin. at this time, if the adie bit is set to 1, adi interrupt request will occur after completing a/d conversion. 5. steps (2) to (4) will be repeated while adst bit is set to 1. a/d conversion will stop when setting the adst b it to 0. when setting the adst bit to 1, a/d conversion will start again from channel 1 (an0). 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 410 of 716 rej09b0398-0500 adst adf addra addrb addrc addrd * 2 a/d continuous conversion set * 1 clear * 1 clear * 1 channel 0 (an0) operation condition channel 1 (an1) operation condition channel 2 (an2) operation condition channel 3 (an3) operation condition conversion standby conversion standby conversion standby conversion standby conversion standby conversion standby conversion standby conversion standby a/d conversion(1) a/d conversion(2) a/d conversion(3) a/d conversion(4) a/d conversion(5) a/d conversion time transfer a/d conversion result(1) a/d conversion result(4) a/d conversion result(2) a/d conversion result(3) notes: 1. indicates command execution by the software 2. data is i g nored durin g conversion figure 14.4 operation exampl e of mid-speed a/d converter (scan mode, three channels selected) (an0 to an2) 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 411 of 716 rej09b0398-0500 14.4.3 input sampling and a/d conversion time the mid-speed a/d converter is equipped with a sample and hold circuit. the mid-speed a/d converter samples input after t d hours has elapsed since setting the adst bit of the a/d control/status register (adcsr) to 1, then begins conversion. the a/d conversion timing is shown in table 14.4. the a/d conversion time, as shown in figure 14.5, includes both t d and input sampling time. here, t d is determined by the write timing to adcsr and is not constant. thus the conversion time changes in the range shown in table 14.4. the conversion time shown in table 14.4 is the time for the first conversion. for the second conversion and after, the time will be 256 state (f ixed) for cks = 0 and 128 state (fixed) for cks = 1. 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 412 of 716 rej09b0398-0500 (1) (2) ck adf t d t spl t conv legend: (1): write cycle of adcsr (2): address of adcsr t d : a/d conversion start delay time t spl : input sampling time t conv : a/d conversion time address write signal input sampling timing figure 14.5 a/d conversion timing 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 413 of 716 rej09b0398-0500 table 14.4 a/d conversion time (single mode) cks = 0 cks = 1 notation min typ max min typ max a/d conversion start delay time t d 10 ? 17 6 ? 9 input sampling time t spl ? 64 ? ? 32 ? a/d conversion time t ccnv 259 ? 266 131 ? 134 note: numbers in the table are in states (t cyc ). 14.4.4 mtu trigger input timing it is possible to start a/d conversion from an mtu trigger input. mtu trigger input is input from mtu when the trge bit of the a/d control register (adcr) is set to 1. a/d conversion is started when the adst bit of the a/d control/status register (adcsr) is set to 1 by mtu trigger. other operations, regardless of whether in the single or scan mode, are the same as when setting the adst bit to 1 with the software. figure 14.6 shows an example of external trigger input timing. mtu trigger signal a/d conversion ck adst figure 14.6 external trigger input timing 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 414 of 716 rej09b0398-0500 14.5 interrupt the mid-speed a/d converter generates an a/d conversion end interrupt (adi) on completion of a/d conversion. adi interrupt requests can be enabled or disabled by means of the adie bit in adcsr. the dmac can be activated by an adi interrupt. having converted data read by the dmac by means of adi interrupts allows continuous conversion to be carried out without imposing a load on the software. the mid-speed a/d converter's interrupt source is summarized in table 14.5. when the dmac are activated by an adi interrupt , the adf flag of adcsr is cleared to 0 by register access of a/d. table 14.5 mid-speed a/d co nverter interrupt factors interrupt factor content dmac adi interrupt by conversion complete activation enabled 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 415 of 716 rej09b0398-0500 14.6 a/d conversion precision definitions the mid-speed a/d converter converts analog values input from analog input channels to 10-bit digital values by comparing them with an analog reference voltage. in this operation, the absolute precision of the a/d conversion (i.e. the deviation between the input analog value and the output digital value) includes the following kinds of error. (1) offset error (2) full-scale error (3) quantization error (4) nonlinearity error the above four kinds of error are described below with reference to figure 14.7. for the sake of clarity, this figure shows 3-bit mid-speed a/d conversion rather than 10-bit mid-speed a/d conversion. offset error (see figure 14.7 (1)) is the deviation between the actual a/d conversion characteristic and the ideal a/d conversion characteristic when the digital output value changes from the minimum value (zero voltage) of 0000000000 (000 in the figure) to 0000000001 (001 in the figure ). full-scale error (see figure 14.7 (2 )) is the deviation between the actual a/d conversion characteristic and the ideal a/d conversion characteristic when the digital output value changes from 1111111110 (110 in the figure) to the maximum value (full-scale voltage) of 111111111 (111 in the figure). quantization error is the deviation inherent in the mid-speed a/d converter, given by 1/2 lsb (see figure 14.7 (3)). nonlinearity error is the deviation between the actual a/d conversion characteristic and the ideal a/d conversion characteristic from zero voltage to full-scale voltage (see figure 14.7 (4)). this does not include offset error, full-scale error, and quantization error. 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 416 of 716 rej09b0398-0500 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 fs 111 110 101 100 011 010 001 000 analo g input volta g e (3) quantization error (4) nonlinearity error (2) full-scale error ideal a/d conversion characteristic ideal a/d conversion characteristic di g ital output di g ital output le g end: fs: full-scale volta g e fs analo g input volta g e actual a/d conversion characteristic (1) offset error figure 14.7 a/d conversio n precision definitions 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 417 of 716 rej09b0398-0500 14.7 usage notes the following points should be noted when using the mid-speed a/d converter. 14.7.1 analog voltage settings (1) analog input voltage range the voltage applied to analog input pins during a/d conversion should be in the range av ss ann av cc (n = 0 to 7). (2) av cc and av ss input voltages for the av cc and av ss input voltages, set av cc = v cc = 5v 10 % and av ss = v ss . when the mid-speed a/d converter is not used, set av cc = v cc and av ss = v ss . 14.7.2 handling of analog input pins to prevent damage from surges and other abnormal voltages at the analog input pins (an0 to an7), connect a protection circuit such as that show n in figure 14.8. this circuit also includes a cr filter function that suppresses error due to noise. the circuit shown here is only a design example; circuit constants must be decided on the basis of the actual operating conditions. figure 14.9 shows an equivalent circuit for the analog input pins, and table 14.6 summarizes the analog input pin specifications. av cc an0 to an7 av ss sh7016 sh7017 note: * 10 f 0.01 f * 0.1 f 100 figure 14.8 example of analog input pin protection circuit 14. mid-speed a/d converter ? sh7016, sh7017 ? rev.5.00 sep. 27, 2007 page 418 of 716 rej09b0398-0500 an0 to an7 1.0 k 20 pf 1 m analo g multiplexer mid-speed a/d converter note: numbers are only to be noted as reference value figure 14.9 equivalent circuit for the analog input pins table 14.6 analog pin specifications item min max unit analog input capacitance ? 20 pf permissible signal source impedance ? 1 k 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 419 of 716 rej09b0398-0500 section 15 compare match timer (cmt) 15.1 overview this lsi has an on-chip compare match timer (cmt) configured of 16-bit timers for two channels. the cmt has 16-bit counters and can generate interrupts at set intervals. 15.1.1 features the cmt has the following features: ? four types of counter input clock can be selected ? one of four internal clocks ( /8, /32, /128, /512) can be selected independently for each channel. ? interrupt sources ? a compare match interrupt can be reque sted independently for each channel. 15.1.2 block diagram figure 15.1 shows a block diagram of the cmt. 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 420 of 716 rej09b0398-0500 cmi0 control circuit internal bus clock selection control circuit clock selection cmi1 /8 /32 /128 /512 /8 /32 /128 /512 cmcsr1 cmcor1 cmcnt1 cmcnt0 cmcor0 comparator cmstr cmcsr0 comparator bus interface module bus cmt le g end: cmstr: cmcsr: cmcor: cmcnt: cmi: compare match timer start re g ister compare match timer control/status re g ister compare match timer constant re g ister compare match timer counter compare match interrupt figure 15.1 cmt block diagram 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 421 of 716 rej09b0398-0500 15.1.3 register configuration table 15.1 summarizes the cmt register configuration. table 15.1 register configuration channel name abbreviation r/w initial value address access size (bits) shared compare match timer start register cmstr r/w h'0000 h'ffff83d0 8, 16, 32 0 compare match timer control/status register 0 cmcsr0 r/(w) * h'0000 h'ffff83d2 8, 16, 32 compare match timer counter 0 cmcnt0 r/w h'0000 h'ffff83d4 8, 16, 32 compare match timer constant register 0 cmcor0 r/w h'ffff h'ffff83d6 8, 16, 32 1 compare match timer control/status register 1 cmcsr1 r/(w) * h'0000 h'ffff83d8 8, 16, 32 compare match timer counter 1 cmcnt1 r/w h'0000 h'ffff83da 8, 16, 32 compare match timer constant register 1 cmcor1 r/w h'ffff h'ffff83dc 8, 16, 32 note: * the only value that can be written to the cmcsr0 and cmcsr1 cmf bits is a 0 to clear the flags. 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 422 of 716 rej09b0398-0500 15.2 register descriptions 15.2.1 compare match timer start register (cmstr) the compare match timer start register (cmstr) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 count ers (cmcnt). it is initialized to h'0000 by power-on resets and by standby mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? str1 str0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bits 15 to 2 ? reserved: these bits always read as 0. the write value should always be 0. bit 1 ? count start 1 (str1): selects whether to operate or halt compare match timer counter 1. bit 1 str1 description 0 cmcnt1 count operation halted (initial value) 1 cmcnt1 count operation bit 0 ? count start 0 (str0): selects whether to operate or halt compare match timer counter 0. bit 0 str0 description 0 cmcnt0 count operation halted (initial value) 1 cmcnt0 count operation 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 423 of 716 rej09b0398-0500 15.2.2 compare match timer co ntrol/status register (cmcsr) the compare match timer control/status register (c mcsr) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock used for incrementation. it is initialized to h'0000 by power-on resets and by standby mode. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 cmf cmie ? ? ? ? cks1 cks0 initial value: 0 0 0 0 0 0 0 0 r/w: r/(w) * r/w r r r r r/w r/w note: * the only value that can be written is a 0 to clear the flag. bits 15 to 8 and 5 to 2 ? reserved: these bits always read as 0. the write value should always be 0. bit 7 ? compare match flag (cmf): this flag indicates whether or not the cmcnt and cmcor values have matched. bit 7 cmf description 0 cmcnt and cmcor values have not matched (initial status) clear condition: write a 0 to cmf after reading a 1 from it 1 cmcnt and cmcor values have matched bit 6 ? compare match interrupt enable (cmie): selects whether to enable or disable a compare match interrupt (cmi) when the cmcnt and cmcor values have matched (cmf = 1). bit 6 cmie description 0 compare match interrupts (cmi) disabled (initial status) 1 compare match interrupts (cmi) enabled 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 424 of 716 rej09b0398-0500 bits 1, 0 ? clock select 1, 0 (cks1, cks0): these bits select the clock input to the cmcnt from among the four internal clocks obtained by dividing the system clock ( ). when the str bit of the cmstr is set to 1, the cmcnt begins incrementing with the clock selected by cks1 and cks0. bit 1 cks1 bit 0 cks0 description 0 0 /8 (initial status) 1 /32 1 0 /128 1 /512 15.2.3 compare match timer counter (cmcnt) the compare match timer counter (cmcnt) is a 16-bit register used as an upcounter for generating interrupt requests. when an internal clock is select ed with the cks1, cks0 bits of the cmcsr register and the str bit of the cmstr is set to 1, the cmcnt begins incrementing with that clock. when the cmcnt value matches that of the compare match timer constant register (cmcor), the cmcnt is cleared to h'0000 and the cmf flag of the cmcsr is set to 1. if the cmie bit of the cmcsr is set to 1 at this time, a compare match interrupt (cmi) is requested. the cmcnt is initialized to h'0000 by power-on resets and by standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 425 of 716 rej09b0398-0500 15.2.4 compare match timer constant register (cmcor) the compare match timer constant register (cmcor ) is a 16-bit register that sets the compare match period with the cmcnt. the cmcor is initialized to h'ffff by power-on resets and by standby mode. bit: 15 14 13 12 11 10 9 8 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 initial value: 1 1 1 1 1 1 1 1 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 426 of 716 rej09b0398-0500 15.3 operation 15.3.1 period count operation when an internal clock is select ed with the cks1, cks0 bits of the cmcsr register and the str bit of the cmstr is set to 1, the cmcnt begins incrementing with the selected clock. when the cmcnt counter value matches that of the compare match constant register (cmcor), the cmcnt counter is cleared to h'0000 and the cmf flag of the cmcsr register is set to 1. if the cmie bit of the cmcsr register is set to 1 at this time, a compare match interrupt (cmi) is requested. the cmcnt counter begins counting up again from h'0000. figure 15.2 shows the compare match counter operation. cmcor h'0000 cmcnt value time counter cleared by cmcor compare match figure 15.2 counter operation 15.3.2 cmcnt count timing one of four clocks ( /8, /32, /128, /512) obtained by dividing the system clock (ck) can be selected by the cks1, cks0 bits of the cmcsr. figure 15.3 shows the timing. ck n ? 1 n n + 1 internal clock cmcnt input clock cmcnt figure 15.3 count timing 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 427 of 716 rej09b0398-0500 15.4 interrupts 15.4.1 interrupt sources the cmt has a compare match inte rrupt for each channel, with independent vector addresses allocated to each of them . the corresponding interrupt request is output when the interrupt request flag cmf is set to 1 and the interrupt enable bit cmie has also been set to 1. when activating cpu interrupts by interrupt request, the priority between the channels can be changed by using the interrupt controller settings. see section 6, interrupt controller, for details. 15.4.2 compare match flag set timing the cmf bit of the cmcsr register is set to 1 by the compare match signal generated when the cmcor register and the cmcnt counter match. the compare match signal is generated upon the final state of the match (timing at which the cmcnt counter matching count value is updated). consequently, after the cmcor register and the cmcnt counter match, a compare match signal will not be generated until a cmcnt counter input clock occu rs. figure 15.4 shows the cmf bit set timing. 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 428 of 716 rej09b0398-0500 ck cmcnt input clock cmcnt cmcor compare match signal cmf cmi n n 0 figure 15.4 cmf set timing 15.4.3 compare match flag clear timing the cmf bit of the cmcsr register is cleared either by writing a 0 to it after reading a 1. figure 15.5 shows the timing when the cmf bit is cleared by the cpu. t 2 t 1 ck cmf cmcsr write cycle figure 15.5 timing of cmf clear by the cpu 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 429 of 716 rej09b0398-0500 15.5 usage notes take care that the contentions described in sections 15.5.1 to 15.5.3 do not arise during cmt operation. 15.5.1 contention between cm cnt write and compare match if a compare match signal is generated during the t 2 state of the cmcnt counter write cycle, the cmcnt counter clear has priority, so the write to the cmcnt counter is not performed. figure 15.6 shows the timing. t 1 t 2 ck address internal write signal compare match signal cmcnt cmcnt write cycle cmcnt n h'0000 figure 15.6 cmcnt write and compare match contention 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 430 of 716 rej09b0398-0500 15.5.2 contention between cmcnt word write and incrementation if an increment occurs during the t 2 state of the cmcnt counter word write cycle, the counter write has priority, so no increment occurs. figure 15.7 shows the timing. cmcnt write data t 1 t 2 ck address internal write si g nal cmcnt input clock cmcnt cmcnt write cycle cmcnt nm figure 15.7 cmcnt word wr ite and increment contention 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 431 of 716 rej09b0398-0500 15.5.3 contention between cmcnt byte write and incrementation if an increment occurs during the t 2 state of the cmcnt byte write cycle, the counter write has priority, so no increment of the write data results on the writing side. the byte data on the side not performing the writing is also not incremented, so the contents are those before the write. figure 15.8 shows the timing when an increment occurs during the t 2 state of the cmcnth write cycle. t 1 t 2 ck address internal write signal cmcnt input clock cmcnth cmcnt write cycle cmcnth n m cmcnth write data x x cmcntl figure 15.8 cmcnt byte wr ite and increment contention 15. compare match timer (cmt) rev.5.00 sep. 27, 2007 page 432 of 716 rej09b0398-0500 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 433 of 716 rej09b0398-0500 section 16 pin function controller (pfc) 16.1 overview the pin function controller (pfc) is composed of registers for selecting the function of multiplexed pins and the direction of input/output. table 16.1 lists this lsi's multiplexed pins. the multiplex pin functions have restrictions dependent on the operating mode. table 16.2 lists the pin functions and initial values for each operating mode. table 16.1 multiplexed pins port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) pin no. a pa15 i/o (port) ck output (cpg) ? ? 83 a pa14 i/o (port) * rd output (bsc) ? ? 34 a pa13 i/o (port) * wrh output (bsc) ? ? 36 a pa12 i/o (port) * wrl output (bsc) ? ? 38 a pa11 i/o (port) * cs1 output (bsc) ? ? 40 a pa10 i/o (port) * cs0 output (bsc) ? ? 41 a pa9 i/o (port) tclkd input (mtu) irq3 (intc) ? 42 a pa8 i/o (port) tclkc input (mtu) irq2 (intc) ? 43 a pa7 i/o (port) tclkb input (mtu) cs3 output (bsc) ? 44 a pa6 i/o (port) tclka input (mtu) cs2 output (bsc) ? 45 a pa5 i/o (port) sck1 i/o (sci) dreq1 input (dmac) irq1 input (intc) 46 a pa4 i/o (port) txd1 output (sci) ? ? 47 a pa3 i/o (port) rxd1 input (sci) ? ? 48 a pa2 i/o (port) sck0 i/o (sci) dreq0 input (dmac) irq0 input (intc) 49 a pa1 i/o (port) txd0 output (sci) ? ? 50 a pa0 i/o (port) rxd0 input (sci) ? ? 51 b pb9 i/o (port) irq7 input (intc) a21 output (bsc) ? 32 b pb8 i/o (port) irq6 input (intc) a20 output (bsc) wait input (bsc) 31 b pb7 i/o (port) ? a19 output (bsc) ? 30 b pb6 i/o (port) ? a18 output (bsc) ? 29 b pb5 i/o (port) irq3 input (intc) ? rdwr output (bsc) 28 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 434 of 716 rej09b0398-0500 port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) pin no. b pb4 i/o (port) irq2 input (intc) ? cash output (bsc) 26 b pb3 i/o (port) irq1 input (intc) ? casl output (bsc) 25 b pb2 i/o (port) irq0 input (intc) ? ras output (bsc) 24 b pb1 i/o (port) * a17 input (bsc) ? ? 22 b pb0 i/o (port) * a16 output (bsc) ? ? 20 c pc15 i/o (port) * a15 output (bsc) ? ? 19 c pc14 i/o (port) * a14 output (bsc) ? ? 18 c pc13 i/o (port) * a13 output (bsc) ? ? 17 c pc12 i/o (port) * a12 output (bsc) ? ? 16 c pc11 i/o (port) * a11 output (bsc) ? ? 15 c pc10 i/o (port) * a10 output (bsc) ? ? 14 c pc9 i/o (port) * a9 output (bsc) ? ? 13 c pc8 i/o (port) * a8 output (bsc) ? ? 12 c pc7 i/o (port) * a7 output (bsc) ? ? 11 c pc6 i/o (port) * a6 output (bsc) ? ? 10 c pc5 i/o (port) * a5 output (bsc) ? ? 9 c pc4 i/o (port) * a4 output (bsc) ? ? 8 c pc3 i/o (port) * a3 output (bsc) ? ? 7 c pc2 i/o (port) * a2 output (bsc) ? ? 6 c pc1 i/o (port) * a1 output (bsc) ? ? 5 c pc0 i/o (port) * a0 output (bsc) ? ? 4 d pd15 i/o (port) * d15 i/o (bsc) ? ? 52 d pd14 i/o (port) * d14 i/o (bsc) ? ? 53 d pd13 i/o (port) * d13 i/o (bsc) ? ? 54 d pd12 i/o (port) * d12 i/o (bsc) ? ? 56 d pd11 i/o (port) * d11 i/o (bsc) ? ? 57 d pd10 i/o (port) * d10 i/o (bsc) ? ? 58 d pd9 i/o (port) * d9 i/o (bsc) ? ? 59 d pd8 i/o (port) * d8 i/o (bsc) ? ? 60 d pd7 i/o (port) * d7 i/o (bsc) ? ? 62 d pd6 i/o (port) * d6 i/o (bsc) ? ? 63 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 435 of 716 rej09b0398-0500 port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) pin no. d pd5 i/o (port) * d5 i/o (bsc) ? ? 64 d pd4 i/o (port) * d4 i/o (bsc) ? ? 66 d pd3 i/o (port) * d3 i/o (bsc) ? ? 67 d pd2 i/o (port) * d2 i/o (bsc) ? ? 68 d pd1 i/o (port) * d1 i/o (bsc) ? ? 69 d pd0 i/o (port) * d0 i/o (bsc) ? ? 70 e pe15 i/o (port) ? dack1 output (dmac) ? 2 e pe14 i/o (port) ? dack0 output (dmac) ah output (bsc) 1 e pe13 i/o (port) ? ? ? 112 e pe12 i/o (port) ? ? ? 111 e pe11 i/o (port) ? ? ? 110 e pe10 i/o (port) ? ? ? 108 e pe9 i/o (port) ? ? ? 107 e pe8 i/o (port) ? ? ? 106 e pe7 i/o (port) tioc2b i/o (mtu) ? ? 105 e pe6 i/o (port) tioc2a i/o (mtu) ? ? 104 e pe5 i/o (port) tioc1b i/o (mtu) ? ? 102 e pe4 i/o (port) tioc1a i/o (mtu) ? ? 89 e pe3 i/o (port) tioc0d i/o (mtu) drak1 output (dmac) ? 88 e pe2 i/o (port) tioc0c i/o (mtu) dreq1 input (dmac) ? 87 e pe1 i/o (port) tioc0b i/o (mtu) drak0 output (dmac) ? 86 e pe0 i/o (port) tioc0a i/o (mtu) dreq0 input (dmac) ? 85 f pf7 input (port) an7 input (a/d) ? ? 99 f pf6 input (port) an6 input (a/d) ? ? 98 f pf5 input (port) an5 input (a/d) ? ? 96 f pf4 input (port) an4 input (a/d) ? ? 95 f pf3 input (port) an3 input (a/d) ? ? 94 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 436 of 716 rej09b0398-0500 port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) pin no. f pf2 input (port) an2 input (a/d) ? ? 93 f pf1 input (port) an1 input (a/d) ? ? 92 f pf0 input (port) an0 input (a/d) ? ? 91 note: * sh7016, sh7017 only 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 437 of 716 rej09b0398-0500 table 16.2 pin functions in each operating mode (sh7014) pin name on-chip rom disabled pin no. mpu mode 0 mpu mode 1 fp-112 initial function function settable by pfc initial function function settable by pfc 21, 37, 65, 103 vcc vcc vcc vcc 3, 23, 27, 33, 39, 55, 61, 71, 90, 101, 109 vss vss vss vss 70 d0 d0 d0 d0 69 d1 d1 d1 d1 68 d2 d2 d2 d2 67 d3 d3 d3 d3 66 d4 d4 d4 d4 64 d5 d5 d5 d5 63 d6 d6 d6 d6 62 d7 d7 d7 d7 60 d8 d8 d8 d8 59 d9 d9 d9 d9 58 d10 d10 d10 d10 57 d11 d11 d11 d11 56 d12 d12 d12 d12 54 d13 d13 d13 d13 53 d14 d14 d14 d14 52 d15 d15 d15 d15 4 a0 a0 a0 a0 5 a1 a1 a1 a1 6 a2 a2 a2 a2 7 a3 a3 a3 a3 8 a4 a4 a4 a4 9 a5 a5 a5 a5 10 a6 a6 a6 a6 11 a7 a7 a7 a7 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 438 of 716 rej09b0398-0500 pin name on-chip rom disabled pin no. mpu mode 0 mpu mode 1 fp-112 initial function function settable by pfc initial function function settable by pfc 12 a8 a8 a8 a8 13 a9 a9 a9 a9 14 a10 a10 a10 a10 15 a11 a11 a11 a11 16 a12 a12 a12 a12 17 a13 a13 a13 a13 18 a14 a14 a14 a14 19 a15 a15 a15 a15 20 a16 a16 a16 a16 22 a17 a17 a17 a17 24 pb2 pb2/ irq0 / ras pb2 pb2/ irq0 / ras 25 pb3 pb3/ irq1 / casl pb3 pb3/ irq1 / casl 26 pb4 pb4/ irq2 / cash pb4 pb4/ irq2 / cash 28 pb5 pb5/ irq3 /rdwr pb5 pb5/ irq3 /rdwr 29 pb6 pb6/a18 pb6 pb6/a18 30 pb7 pb7/a19 pb7 pb7/a19 31 pb8 pb8/ irq6 /a20/ wait pb8 pb8/ irq6 /a20/ wait 32 pb9 pb9/ irq7 /a21 pb9 pb9/ irq7 /a21 51 pa0 pa0/rxd0 pa0 pa0/rxd0 50 pa1 pa1/txd0 pa1 pa1/txd0 49 pa2 pa2/sck0/ dreq0 / irq0 pa2 pa2/sck0/ dreq0 / irq0 48 pa3 pa3/rxd1 pa3 pa3/rxd1 47 pa4 pa4/txd1 pa4 pa4/txd1 46 pa5 pa5/sck1/ dreq1 / irq1 pa5 pa5/sck1/ dreq1 / irq1 45 pa6 pa6/tclka/ cs2 pa6 pa6/tclka/ cs2 44 pa7 pa7/tclkb/ cs3 pa7 pa7/tclkb/ cs3 43 pa8 pa8/tclkc/ irq2 pa8 pa8/tclkc/ irq2 42 pa9 pa9/tclkd/ irq3 pa9 pa9/tclkd/ irq3 41 cs0 cs0 cs0 cs0 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 439 of 716 rej09b0398-0500 pin name on-chip rom disabled pin no. mpu mode 0 mpu mode 1 fp-112 initial function function settable by pfc initial function function settable by pfc 40 cs1 cs1 cs1 cs1 38 wrl wrl wrl wrl 36 wrh wrh wrh wrh 34 rd rd rd rd 83 ck pa15/ck ck pa15/ck 80 pllvcc pllvcc pllvcc pllvcc 82 pllvss pllvss pllvss pllvss 74 extal extal extal extal 72 xtal xtal xtal xtal 81 pllcap pllcap pllcap pllcap 76 nmi nm i nmi nmi 84 res res res res 35 wdtovf wdtovf wdtovf wdtovf 79 md0 md0 md0 md0 78 md1 md1 md1 md1 75 md2 md2 md2 md2 73 md3 md3 md3 md3 77 vcc vcc vcc vcc 100 avcc avcc avcc avcc 97 avss avss avss avss 91 pf0/an0 pf0/an0 pf0/an0 pf0/an0 92 pf1/an1 pf1/an1 pf1/an1 pf1/an1 93 pf2/an2 pf2/an2 pf2/an2 pf2/an2 94 pf3/an3 pf3/an3 pf3/an3 pf3/an3 95 pf4/an4 pf4/an4 pf4/an4 pf4/an4 96 pf5/an5 pf5/an5 pf5/an5 pf5/an5 98 pf6/an6 pf6/an6 pf6/an6 pf6/an6 99 pf7/an7 pf7/an7 pf7/an7 pf7/an7 85 pe0 pe0/tioc0a/ dreq0 pe0 pe0/tioc0a/ dreq0 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 440 of 716 rej09b0398-0500 pin name on-chip rom disabled pin no. mpu mode 0 mpu mode 1 fp-112 initial function function settable by pfc initial function function settable by pfc 86 pe1 pe1/tioc0b/drak0 pe1 pe1/tioc0b/drak0 87 pe2 pe2/tioc0c/ dreq1 pe2 pe2/tioc0c/ dreq1 88 pe3 pe3/tioc0d/drak1 pe3 pe3/tioc0d/drak1 89 pe4 pe4/tioc1 a pe4 pe4/tioc1a 102 pe5 pe5/tioc1b pe5 pe5/tioc1b 104 pe6 pe6/tioc2a pe6 pe6/tioc2a 105 pe7 pe7/tioc2b pe7 pe7/tioc2b 106 pe8 pe8 pe8 pe8 107 pe9 pe9 pe9 pe9 108 pe10 pe10 pe10 pe10 110 pe11 pe11 pe11 pe11 111 pe12 pe12 pe12 pe12 112 pe13 pe13 pe13 pe13 1 pe14 pe14/dack0/ ah pe14 pe14/dack0/ ah 2 pe15 pe15/dack1 pe15 pe15/dack1 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 441 of 716 rej09b0398-0500 table 16.3 pin arrangement in each operating mode (sh7016, sh7017) pin no. pin name fp-112 21,37,65 103 3,23,27,33 39,55,61,71 90,101,109 70 69 68 67 66 64 63 62 60 59 58 57 56 54 53 52 4 5 6 7 8 9 10 11 12 13 14 15 16 sin g le chip mode mpu mode0 mpu mode 1 mpu mode2 on-chip rom enabled initial function v cc v cc on-chip rom disabled v cc v cc v cc v cc v cc v cc v ss d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 v ss d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 v ss d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 v ss d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 v ss pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 pd10 pd11 pd12 pd13 pd14 pd15 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 pc12 v ss v ss v ss pd0/d0 pd1/d1 pd2/d2 pd3/d3 pd4/d4 pd5/d5 pd6/d6 pd7/d7 pd8/d8 pd9/d9 pd10/d10 pd11/d11 pd12/d12 pd13/d13 pd14/d14 pd15/d15 pc0/a0 pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pc6/a6 pc7/a7 pc8/a8 pc9/a9 pc10/a10 pc11/a11 pc12/a12 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 pd10 pd11 pd12 pd13 pd14 pd15 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 pc12 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 pd9 pd10 pd11 pd12 pd13 pd14 pd15 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pc8 pc9 pc10 pc11 pc12 pfc selected function possiblilities initial function pfc selected function possiblilities initial function pfc selected function possiblilities initial function pfc selected function possiblilities 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 442 of 716 rej09b0398-0500 pin no. pin name fp-112 17 18 19 20 22 24 25 26 28 29 30 31 32 51 50 49 48 47 46 45 44 43 42 41 40 38 36 34 83 80 82 74 72 81 76 84 35 79 78 75 73 77 100 97 sin g le chip mode mpu mode0 mpu mode 1 mpu mode2 on-chip rom enabled initial function on-chip rom disabled a13 a14 a15 a16 a17 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pb9 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pa8 pa9 cs0 cs1 wrl wrh rd ck pllv cc pllv ss extal xtal pllcap nmi res wdtovf md0 md1 md2 md3 v cc av cc av ss a13 a14 a15 a16 a17 pb2/ irq0 / poe0 / ras pb3/ irq1 / poe1 / casl pb4/ irq2 / poe2 / cash pb5/ irq3 / poe3 /rdwr pb6/a18 pb7/a19 pb8/ irq6 /a20/ wait pb9/ irq7 /a21 pa0/rxd0 pa1/txd0 pa2/sck0/ dreq0 / irq0 pa3/rxd1 pa4/txd1 pa5/sck1/ dreq1 / irq1 pa6/tclka/ cs2 pa7/tclkb/ cs3 pa8/tclkc/ irq2 pa9/tclkd/ irq3 cs0 cs1 wrl wrh rd pa15/ck pllv cc pllv ss extal xtal pllcap nmi res wdtovf md0 md1 md2 md3 v cc av cc av ss a13 a14 a15 a16 a17 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pb9 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pa8 pa9 cs0 cs1 wrl wrh rd ck pllv cc pllv ss extal xtal pllcap nmi res wdtovf md0 md1 md2 md3 v cc av cc av ss a13 a14 a15 a16 a17 pb2/ irq0 / ras pb3/ irq1 / casl pb4/ irq2 / cash pb5/ irq3 /rdwr pb6/a18 pb7/a19 pb8/ irq6 /a20/ wait pb9/ irq7 /a21 pa0/rxd0 pa1/txd0 pa2/sck0/ dreq0 / irq0 pa3/rxd1 pa4/txd1 pa5/sck1/ dreq1 / irq1 pa6/tclka/ cs2 pa7/tclkb/ cs3 pa8/tclkc/ irq2 pa9/tclkd/ irq3 cs0 cs1 wrl wrh rd pa15/ck pllv cc pllv ss extal xtal pllcap nmi res wdtovf md0 md1 md2 md3 v cc av cc av ss pc13 pc14 pc15 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pb9 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pa8 pa9 pa10 pa11 pa12 pa13 pa14 ck pllv cc pllv ss extal xtal pllcap nmi res wdtovf md0 md1 md2 md3 v cc av cc av ss pc13/a13 pc14/a14 pc15/a15 pb0/a16 pb1/a17 pb2/ irq0 / ras pb3/ irq1 / casl pb4/ irq2 / cash pb5/ irq3 /rdwr pb6/a18 pb7/a19 pb8/ irq6 /a20/ wait pb9/ irq7 /a21 pa0/rxd0 pa1/txd0 pa2/sck0/ dreq0 / irq0 pa3/rxd1 pa4/txd1 pa5/sck1/ dreq1 / irq1 pa6/tclka/ cs2 pa7/tclkb/ cs3 pa8/tclkc/ irq2 pa9/tclkd/ irq3 pa10/ cs0 pa11/ cs1 pa12/ wrl pa13/ wrh pa14/ rd pa15/ck pllv cc pllv ss extal xtal pllcap nmi res wdtovf md0 md1 md2 md3 v cc av cc av ss pc13 pc14 pc15 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pb8 pb9 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pa8 pa9 pa10 pa11 pa12 pa13 pa14 pa15 pllv cc pllv ss extal xtal pllcap nmi res wdtovf md0 md1 md2 md3 v cc av cc av ss pc13 pc14 pc15 pb0 pb1 pb2/ irq0 pb3/ irq1 pb4/ irq2 pb5/ irq3 pb6 pb7 pb8/ irq6 pb9/ irq7 pa0/rxd0 pa1/txd0 pa2/sck0/ irq0 pa3/rxd1 pa4/txd1 pa5/sck1/ irq1 pa6/tclka pa7/tclkb pa8/tclkc/ irq2 pa9/tclkd/ irq3 pa10 pa11 pa12 pa13 pa14 pa15/ck pllv cc pllv ss extal xtal pllcap nmi res wdtovf md0 md1 md2 md3 v cc av cc av ss pfc selected function possiblilities initial function pfc selected function possiblilities initial function pfc selected function possiblilities initial function pfc selected function possiblilities 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 443 of 716 rej09b0398-0500 pin no. pin name fp-112 91 92 93 94 95 96 98 99 85 86 87 88 89 102 104 105 106 107 108 110 111 112 1 2 sin g le chip mode mpu mode0 mpu mode 1 mpu mode2 on-chip rom enabled initial function on-chip rom disabled pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 pf6/an6 pf7/an7 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 pf6/an6 pf7/an7 pe0/tioc0a/ dreq0 pe1/tioc0b/drak0 pe2/tioc0c/ dreq1 pe3/tioc0d/drak1 pe4/tioc1a pe5/tioc1b pe6/tioc2a pe7/tioc2b pe8 pe9 pe10 pe11 pe12 pe13 pe14/dack0/ ah pe15/dack1 pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 pf6/an6 pf7/an7 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 pf6/an6 pf7/an7 pe0/tioc0a/ dreq0 pe1/tioc0b/drak0 pe2/tioc0c/ dreq1 pe3/tioc0d/drak1 pe4/tioc1a pe5/tioc1b pe6/tioc2a pe7/tioc2b pe8 pe9 pe10 pe11 pe12 pe13 pe14/dack0/ ah pe15/dack1 pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 pf6/an6 pf7/an7 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 pf6/an6 pf7/an7 pe0/tioc0a/ dreq0 pe1/tioc0b/drak0 pe2/tioc0c/ dreq1 pe3/tioc0d/drak1 pe4/tioc1a pe5/tioc1b pe6/tioc2a pe7/tioc2b pe8 pe9 pe10 pe11 pe12 pe13 pe14/dack0/ ah pe15/dack1 pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 pf6/an6 pf7/an7 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 pf6/an6 pf7/an7 pe0/tioc0a pe1/tioc0b pe2/tioc0c pe3/tioc0d pe4/tioc1a pe5/tioc1b pe6/tioc2a pe7/tioc2b pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pfc selected function possiblilities initial function pfc selected function possiblilities initial function pfc selected function possiblilities initial function pfc selected function possiblilities 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 444 of 716 rej09b0398-0500 16.2 register configuration table 16.4 summarizes the registers of the pin function controller. table 16.4 pin function controller registers name abbreviation r/w initial value address access size port a i/o register l paiorl r/w h'0000 h'ffff8386 h'ffff8387 8, 16, 32 port a control register l1 pacrl1 r/w h'0000 * 1 h'4000 h'ffff838c h'ffff838d 8, 16, 32 port a control register l2 pacrl2 r/w h'0000 h'ffff838e h'ffff838f 8, 16, 32 port b i/o register pbior r/w h'0000 h'ffff8394 h'ffff8395 8, 16, 32 port b control register 1 pbcr1 r/w h'0000 h'ffff8398 h'ffff8399 8, 16, 32 port b control register 2 pbcr2 r/w h'0000 h'ffff839a h'ffff839b 8, 16, 32 port c i/o register * 2 pcior r/w h'0000 h'ffff8396 h'ffff8397 8, 16, 32 port c control register * 2 pccr r/w h'0000 h'ffff839c h'ffff839d 8, 16, 32 port d i/o register l * 2 pdiorl r/w h'0000 h'ffff83a6 h'ffff83a7 8, 16, 32 port d control register l * 2 pdcrl r/w h'0000 h'ffff83ac h'ffff83ad 8, 16, 32 port e i/o register peior r/w h'0000 h'ffff83b4 h'ffff83b5 8, 16, 32 port e control register 1 pecr1 r/w h'0000 h'ffff83b8 h'ffff83b9 8, 16, 32 port e control register 2 pecr2 r/w h'0000 h'ffff83ba h'ffff83bb 8, 16, 32 notes: 1. the port a control register l1 initial value varies depending on the operating mode. 2. sh7016, sh7017 only. 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 445 of 716 rej09b0398-0500 16.3 register descriptions 16.3.1 port a i/o register l (paiorl) bit: 15 14 13 12 11 10 9 8 pa15 ior pa14 ior pa13 ior pa12 ior pa11 ior pa10 ior pa9 ior pa8 ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w * r/w * r/w * r/w * r/w * r/w r/w bit: 7 6 5 4 3 2 1 0 pa7 ior pa6 ior pa5 ior pa4 ior pa3 ior pa2 ior pa1 ior pa0 ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * r only in the sh7014 the port a i/o register l (paiorl) is a 16-bit read/write register that selects input or output for the 16 pins of port a (11 pins in the sh7014). bits pa15ior to pa0ior correspond to pins pa15/ck to pa0/rxd0. paiorl is enabled when the port a pins function as general input/outputs (pa15 to pa0), or with the serial clock (sck1, sck0). for other functions, it is disabled. when the port a pin functions pa15 to pa0 are sck1, sck0, a given pin in port a is an output pin if its corresponding paiorl bit is set to 1, and an input pin if the bit is cleared to 0. paiorl is initialized to h'0000 by external power -on reset; however, it is not initialized for reset by wdt, standby mode, or sleep mode, so the previous data is maintained. the settings of bits 14 to 10 of this register are functional only in the sh7016 and sh7017. in the sh7014, there are no pins corresponding to bits 14 to 10; these bits are always read as 0, and their write value should always be 0. 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 446 of 716 rej09b0398-0500 16.3.2 port a control registers l1, l2 (pacrl1 and pacrl2) pacrl1 and pacrl2 are 16-bit read/write regi sters that select the functions of the 16 multiplexed pins of port a (11 pins in the sh7014). pacrl1 selects the function of the pa15/ck to pa8/tclkc/ irq2 pins of port a; pacrl2 selects the function of the pa7/tclkb/ cs3 to pa0/rxd0 pins of port a. port a includes bus control signals ( rd , wrh , wrl , cs0 to cs3 , and ah ) and dmac control signals ( dreq0 and dreq1 ), but in the sh7016 and sh7017, register settings relating to the selection of these pin functions may be invalid depending on the operating mode. for details, see table 16.2, pin functions in each operating mode. pacrl1 is initialized by external power-on reset to h'4000 in extended mode, and to h'0000 in single chip mode. pacrl2 is initialized by external power-on reset to h'0000. neither register is initialized by reset by wdt, standby mode, or sleep mode, so the previous data is maintained. the settings of bits 12, 10, 8, 6, and 4 of pacrl1 are functional only in the sh7016 and sh7017. in the sh7014, there are no pins corresponding to th ese bits; they are always read as 0, and their write value should always be 0. port a control register l1 (pacrl1): bit: 15 14 13 12 11 10 9 8 ? pa15md ? pa14md ? pa13md ? pa12md initial value: 0 0 (1) * 1 0 0 0 0 0 0 r/w: r r/w r r/w * 2 r r/w * 2 r r/w * 2 bit: 7 6 5 4 3 2 1 0 ? pa11md ? pa10md pa9md1 pa9md0 pa8md1 pa8md0 initial value: 0 0 0 0 0 0 0 0 r/w: r r/w * 2 r r/w * 2 r/w r/w r/w r/w notes: 1. bit 14 is initialized to 1 in extended mode. 2. r only in the sh7014. 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 447 of 716 rej09b0398-0500 bit 15 ? reserved: this bit always reads as 0. the write value should always be 0. bit 14 ? pa15 mode (pa15md): selects the function of the pa15/ck pin. bit 14 pa15md description 0 general input/output (pa15) (single chip mode initial value) 1 clock output (ck) (extended mode initial value) bits 13 ? reserved: this bit always read as 0. the write value should always be 0. bit 12 ? pa14 mode (pa14md) ? sh7016, sh7017 ? : selects the function of the pa14/ rd pin. bit 12 pa14md description 0 general input/output (pa14) (initial value) ( rd in on-chip rom invalid mode) 1 read output ( rd ) (pa14 in single chip mode) bit 11 ? reserved: this bit always reads as 0. the write value should always be 0. bit 10 ? pa13 mode (pa13md) ? sh7016, sh7017 ? : selects the function of the pa13/ wrh pin. bit 10 pa13md description 0 general input/output (pa13) (initial value) ( wrh in on-chip rom invalid mode) 1 most significant side write output ( wrh ) (pa13 in single chip mode) bit 9 ? reserved: this bit always reads as 0. the write value should always be 0. 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 448 of 716 rej09b0398-0500 bit 8 ? pa12 mode (pa12md) ? sh7016, sh7017 ? : selects the function of the pa12/ wrl pin. bit 8 pa12md description 0 general input/output (pa12) (initial value) ( wrl in on-chip rom invalid mode) 1 least significant side write output ( wrl ) (pa12 in single chip mode) bit 7 ? reserved: this bit always reads as 0. the write value should always be 0. bit 6 ? pa11 mode (pa11md) ? sh7016, sh7017 ? : selects the function of the pa11/ cs1 pin. bit 6 pa11md description 0 general input/output (pa11) (initial value) ( cs1 in on-chip rom invalid mode) 1 chip select output ( cs1 ) (pa11 in single chip mode) bit 5 ? reserved: this bit always reads as 0. the write value should always be 0. bit 4 ? pa10 mode (pa10md) ? sh7016, sh7017 ? : selects the function of the pa10/ cs0 pin. bit 4 pa10md description 0 general input/output (pa10) (initial value) ( cs0 in on-chip rom invalid mode) 1 chip select output ( cs0 ) (pa10 in single chip mode) 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 449 of 716 rej09b0398-0500 bits 3 and 2 ? pa9 mode 1, 0 (pa9md1 and pa9md0): these bits select the function of the pa9/tclkd/ irq3 pin. bit 3 pa9md1 bit 2 pa9md0 description 0 0 general input/output (pa9) (initial value) 1 mtu timer clock input (tclkd) 1 0 interrupt request input ( irq3 ) 1 reserved bits 1 and 0 ? pa8 mode 1, 0 (pa8md1 and pa8md0): these bits select the function of the pa8/tclkc/ irq2 pin. bit 1 pa8md1 bit 0 pa8md0 description 0 0 general input/output (pa8) (initial value) 1 mtu timer clock input (tclkc) 1 0 interrupt request input ( irq2 ) 1 reserved port a control register l2 (pacrl2): bit: 15 14 13 12 11 10 9 8 pa7 md1 pa7 md0 pa6 md1 pa6 md0 pa5 md1 pa5 md0 ? pa4md initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r r/w bit: 7 6 5 4 3 2 1 0 ? pa3md pa2 md1 pa2 md0 ? pa1md ? pa0md initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r r/w r r/w 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 450 of 716 rej09b0398-0500 bits 15 and 14 ? pa7 mode 1, 0 (pa7md1 and pa7md0): these bits select the function of the pa7/tclkb/ cs3 pin. bit 15 pa7md1 bit 14 pa7md0 description 0 0 general input/output (pa7) (initial value) 1 mtu timer clock input (tclkb) 1 0 chip select output ( cs3 ) (pa7 in single-chip mode) 1 reserved bits 13 and 12 ? pa6 mode 1, 0 (pa6md1 and pa6md0): these bits select the function of the pa6/tclka/ cs2 pin. bit 13 pa6md1 bit 12 pa6md0 description 0 0 general input/output (pa6) (initial value) 1 mtu timer clock input (tclka) 1 0 chip select output ( cs2 ) (pa6 in single-chip mode) 1 reserved bits 11 and 10 ? pa5 mode 1, 0 (pa5md1 and pa5md0): these bits select the function of the pa5/sck1/ dreq1 / irq1 pin. bit 11 pa5md1 bit 10 pa5md0 description 0 0 general input/output (pa5) (initial value) 1 serial clock input/output (sck1) 1 0 dma transfer request received input ( dreq1 ) (pa5 in single-chip mode) 1 interrupt request input ( irq1 ) bit 9 ? reserved: this bit always reads as 0. the write value should always be 0. 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 451 of 716 rej09b0398-0500 bit 8 ? pa4 mode (pa4md): selects the function of the pa4/txd1 pin. bit 8 pa4md description 0 general input/output (pa4) (initial value) 1 transmit data output (txd1) bit 7 ? reserved: this bit always reads as 0. the write value should always be 0. bit 6 ? pa3 mode (pa3md): selects the function of the pa3/rxd1 pin. bit 6 pa3md description 0 general input/output (pa3) (initial value) 1 receive data input (rxd1) bits 5 and 4 ? pa2 mode 1, 0 (pa2md1 and pa2md0): these bits select the function of the pa2/sck0/ dreq0 / irq0 pin. bit 5 pa2md1 bit 4 pa2md0 description 0 0 general input/output (pa2) (initial value) 1 serial clock input/output (sck0) 1 0 dma transfer request received input ( dreq0 ) (pa2 in single-chip mode) 1 interrupt request input ( irq0 ) bit 3 ? reserved: this bit always reads as 0. the write value should always be 0. bit 2 ? pa1 mode (pa1md): selects the function of the pa1/txd0 pin. bit 2 pa1md description 0 general input/output (pa1) (initial value) 1 transmit data output (txd0) bit 1 ? reserved: this bit always reads as 0. the write value should always be 0. 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 452 of 716 rej09b0398-0500 bit 0 ? pa0 mode (pa0md): selects the function of the pa0/rxd0 pin. bit 0 pa0md description 0 general input/output (pa0) (initial value) 1 receive data input (rxd0) 16.3.3 port b i/o register (pbior) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? pb9 ior pb8 ior initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 pb7 ior pb6 ior pb5 ior pb4 ior pb3 ior pb2 ior pb1 ior pb0 ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w * r/w * note: * r only in the sh7014. the port b i/o register l (pbior) is a 16-bit read/write register that selects input or output for the ten pins of port b (eight pins in the sh7014). bits pb9ior to pb0ior correspond to the pb9/ irq7 /a21 pin to pb0/a16 pin. pbior is enabled when the port b pins function as input/outputs (pb9 to pb0). for other functions, it is disabled. for port b pin functions pb9 to pb0, a given pin in port b is an output pin if its corresponding pbior bit is set to 1, and an input pin if the bit is cleared to 0. pbior is initialized to h'0000 by external power-on reset; however, it is not initialized for reset by wdt, standby mode, or sleep mode, so the previous data is maintained. the settings of bits 1 and 0 of pbior are functional only in the sh7016 and sh7017. in the sh7014, there are no pins corresponding to these bits; they are always read as 0, and their write value should always be 0. 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 453 of 716 rej09b0398-0500 16.3.4 port b control registers (pbcr1 and pbcr2) pbcr1 and pbcr2 are 16-bit read/write registers that select the functions of the ten multiplexed pins of port b (eight pins in the sh7014). pbcr1 selects the functions of the top two bits of port b; pbcr2 selects the functions of the bottom eight bits of port b (six bits in the sh7014). port b includes bus control signals (rdwr, ras , cash , casl , and wait ) and address outputs (a21 to a16), but in the sh7016 and sh7017, settings in these registers relating to the selection of these pin functions may be invalid in single-chip mode. for details, see table 16.3, pin functions in each operating mode. pbcr1 and pbcr2 are both initialized to h'0000 by external power-on reset but are not initialized for reset by wdt, standby mode, or sleep mode, so the previous data is maintained. the settings of bits 2 and 0 of pbcr2 are functional only in the sh7016 and sh7017. in the sh7014, there are no pins corresponding to these bits; they are always read as 0, and their write value should always be 0. port b control register 1 (pbcr1): bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? pb9 md1 pb9 md0 pb8 md1 pb8 md0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r/w r/w r/w r/w 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 454 of 716 rej09b0398-0500 bits 15 to 4 ? reserved: these bits always read as 0. the write value should always be 0. bits 3 and 2 ? pb9 mode 1, 0 (pb9md1 and pb9md0): pb9md1 and pb9md0 select the function of the pb9/ irq7 /a21 pin. bit 3 pb9md1 bit 2 pb9md0 description 0 0 general input/output (pb9) (initial value) 1 interrupt request input ( irq7 ) 1 0 address output (a21) (pb9 in single-chip mode) 1 reserved bits 1 and 0 ? pb8 mode 1, 0 (pb8md1 and pb8md0): pb8md1 and pb8md0 select the function of the pb8/ irq6 /a20/ wait pin. bit 1 pb8md1 bit 0 pb8md0 description 0 0 general input/output (pb8) (initial value) 1 interrupt request input ( irq6 ) 1 0 address output (a20) (pb8 in single-chip mode) 1 wait state request input ( wait ) (pb8 in single-chip mode) port b control register 2 (pbcr2): bit: 15 14 13 12 11 10 9 8 pb7md1 pb7md0 pb6md1 pb6md0 pb5md1 pb5md0 pb4md1 pb4md0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pb3md1 pb3md0 pb2md1 pb2md0 ? pb1md ? pb0md initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r/w * r r/w * note: * r only in the sh7014. 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 455 of 716 rej09b0398-0500 bits 15 and 14 ? pb7 mode 1, 0 (pb7md1 and pb7md0): pb7md1 and pb7md0 select the function of the pb7/a19 pin. bit 15 pb7md1 bit 14: pb7md0 description 0 0 general input/output (pb7) (initial value) 1 reserved 1 0 address output (a19) (pb7 in single-chip mode) 1 reserved bits 13 and 12 ? pb6 mode 1, 0 (pb6md1 and pb6md0): pb6md1 and pb6md0 select the function of the pb6/a18 pin. bit 13 pb6md1 bit 12 pb6md0 description 0 0 general input/output (pb6) (initial value) 1 reserved 1 0 address output (a18) (pb6 in single-chip mode) 1 reserved bits 11 and 10 ? pb5 mode 1, 0 (pb5md1 and pb5md0): pb5md1 and pb5md0 select the function of the pb5/ irq3 /rdwr pin. bit 11 pb5md1 bit 10 pb5md0 description 0 0 general input/output (pb5) (initial value) 1 interrupt request input ( irq3 ) 1 0 reserved 1 read/write output (rdwr) (pb5 in single-chip mode) 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 456 of 716 rej09b0398-0500 bits 9 and 8 ? pb4 mode 1, 0 (pb4md1 and pb4md0): pb4md1 and pb4md0 select the function of the pb4/ irq2 / cash pin. bit 9 pb4md1 bit 8 pb4md0 description 0 0 general input/output (pb4) (initial value) 1 interrupt request input ( irq2 ) 1 0 reserved 1 column address strobe ( cash ) (pb4 in single-chip mode) bits 7 and 6 ? pb3 mode 1, 0 (pb3md1 and pb3md0): pb3md1 and pb3md0 select the function of the pb3/ irq1 / casl pin. bit 7 pb3md1 bit 6 pb3md0 description 0 0 general input/output (pb3) (initial value) 1 interrupt request input ( irq1 ) 1 0 reserved 1 column address strobe ( casl ) (pb3 in single-chip mode) bits 5 and 4 ? pb2 mode 1, 0 (pb2md1 and pb2md0): pb2md1 and pb2md0 select the function of the pb2/ irq0 / ras pin. bit 5 pb2md1 bit 4 pb2md0 description 0 0 general input/output (pb2) (initial value) 1 interrupt request input ( irq0 ) 1 0 reserved 1 row address strobe ( ras ) (pb2 in single-chip mode) bit 3 ? reserved: this bit always reads as 0. the write value should always be 0. 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 457 of 716 rej09b0398-0500 bit 2 ? pb1 mode (pb1md) ? sh7016, sh7017 ? : selects the function of the pb1/a17 pin. bit 2 pb1md description 0 general input/output (pb1) (initial value) (a17 in on-chip rom invalid mode) 1 address output (a17) (pb1 in single chip mode) bit 1 ? reserved: this bit always reads as 0. the write value should always be 0. bit 0 ? pb0 mode (pb0md) ? sh7016, sh7017 ? : selects the function of the pb0/a16 pin. bit 0 pb0md description 0 general input/output (pb0) (initial value) (a16 in on-chip rom invalid mode) 1 address output (a16) (pb0 in single chip mode) 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 458 of 716 rej09b0398-0500 16.3.5 port c i/o register (pcior) ? sh7016, sh7017 ? bit: 15 14 13 12 11 10 9 8 pc15 ior pc14 ior pc13 ior pc12 ior pc11 ior pc10 ior pc9 ior pc8 ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pc7 ior pc6 ior pc5 ior pc4 ior pc3 ior pc2 ior pc1 ior pc0 ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the port c i/o register (pcior) is a 16-bit read/write register that selects input or output for the 16 port c pins. bits pc15ior to pc0ior correspond to pins pc15/a15 to pc0/a0. pcior is enabled when the port c pins function as general input/outputs (pc15 to pc0). for other functions, it is disabled. when the port c pin functions are as pc15 to pc0, a given pin in port c is an output pin if its corresponding pcior bit is set to 1, and an input pin if the bit is cleared to 0. pcior is initialized to h'0000 by external power-on reset; however, it is not initialized for reset by wdt, standby mode, or sleep mode, so the previous values are maintained. the settings in this register are functional only in the sh7016 and sh7017. in the sh7014, there are no pins corresponding to this register, and it should not be read or written to. 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 459 of 716 rej09b0398-0500 16.3.6 port c control register (pccr) ? sh7016, sh7017 ? bit: 15 14 13 12 11 10 9 8 pc15 md pc14 md pc13 md pc12 md pc11 md pc10 md pc9 md pc8 md initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pc7 md pc6 md pc5 md pc4 md pc3 md pc2 md pc1 md pc0 md initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w pccr is a 16-bit read/write register that selects the functions for the sixteen port c multiplexed pins. there are instances when th ese register settings will be ignor ed, depending on the operation mode. refer to table 16.3, pin arrangement by mode, for details. pccr is initialized to h'0000 by power-on resets but is not initialized for reset by wdt, standby mode, or sleep mode, so the previous data is maintained. the settings in this register are functional only in the sh7016 and sh7017. in the sh7014, there are no pins corresponding to this register, and it should not be read or written to. bit 15 ? pc15 mode (pc15md): selects the function of the pc15/a15 pin. bit 15 pc15md description 0 general input/output (pc15) (initial value) (a15 in on-chip rom invalid mode) 1 address output (a15) (pc15 in single chip mode) 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 460 of 716 rej09b0398-0500 bit 14 ? pc14 mode (pc14md): selects the function of the pc14/a14 pin. bit 14 pc14md description 0 general input/output (pc14) (initial value) (a14 in on-chip rom invalid mode) 1 address output (a14) (pc14 in single chip mode) bit 13 ? pc13 mode (pc13md): selects the function of the pc13/a13 pin. bit 13 pc13md description 0 general input/output (pc13) (initial value) (a13 in on-chip rom invalid mode) 1 address output (a13) (pc13 in single chip mode) bit 12 ? pc12 mode (pc12md): selects the function of the pc12/a12 pin. bit 12 pc12md description 0 general input/output (pc12) (initial value) (a12 in on-chip rom invalid mode) 1 address output (a12) (pc12 in single chip mode) bit 11 ? pc11 mode (pc11md): selects the function of the pc11/a11 pin. bit 11 pc11md description 0 general input/output (pc11) (initial value) (a11 in on-chip rom invalid mode) 1 address output (a11) (pc11 in single chip mode) 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 461 of 716 rej09b0398-0500 bit 10 ? pc10 mode (pc10md): selects the function of the pc10/a10 pin. bit 10 pc10md description 0 general input/output (pc10) (initial value) (a10 in on-chip rom invalid mode) 1 address output (a10) (pc10 in single chip mode) bit 9 ? pc9 mode (pc9md): selects the function of the pc9/a9 pin. bit 9 pc9md description 0 general input/output (pc9) (initial value) (a9 in on-chip rom invalid mode) 1 address output (a9) (p c9 in single chip mode) bit 8 ? pc8 mode (pc8md): selects the function of the pc8/a8 pin. bit 8 pc8md description 0 general input/output (pc8) (initial value) (a8 in on-chip rom invalid mode) 1 address output (a8) (p c8 in single chip mode) bit 7 ? pc7 mode (pc7md): selects the function of the pc7/a7 pin. bit 7 pc7md description 0 general input/output (pc7) (initial value) (a7 in on-chip rom invalid mode) 1 address output (a7) (p c7 in single chip mode) 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 462 of 716 rej09b0398-0500 bit 6 ? pc6 mode (pc6md): selects the function of the pc6/a6 pin. bit 6 pc6md description 0 general input/output (pc6) (initial value) (a6 in on-chip rom invalid mode) 1 address output (a6) (p c6 in single chip mode) bit 5 ? pc5 mode (pc5md): selects the function of the pc5/a5 pin. bit 5 pc5md description 0 general input/output (pc5) (initial value) (a5 in on-chip rom invalid mode) 1 address output (a5) (p c5 in single chip mode) bit 4 ? pc4 mode (pc4md): selects the function of the pc4/a4 pin. bit 4 pc4md description 0 general input/output (pc4) (initial value) (a4 in on-chip rom invalid mode) 1 address output (a4) (p c4 in single chip mode) bit 3 ? pc3 mode (pc3md): selects the function of the pc3/a3 pin. bit 3 pc3md description 0 general input/output (pc3) (initial value) (a3 in on-chip rom invalid mode) 1 address output (a3) (p c3 in single chip mode) 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 463 of 716 rej09b0398-0500 bit 2 ? pc2 mode (pc2md): selects the function of the pc2/a2 pin. bit 2 pc2md description 0 general input/output (pc2) (initial value) (a2 in on-chip rom invalid mode) 1 address output (a2) (p c2 in single chip mode) bit 1 ? pc1 mode (pc1md): selects the function of the pc1/a1 pin. bit 1 pc1md description 0 general input/output (pc1) (initial value) (a1 in on-chip rom invalid mode) 1 address output (a1) (p c1 in single chip mode) bit 0 ? pc0 mode (pc0md): selects the function of the pc0/a0 pin. bit 0 pc0md description 0 general input/output (pc0) (initial value) (a0 in on-chip rom invalid mode) 1 address output (a0) (p c0 in single chip mode) 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 464 of 716 rej09b0398-0500 16.3.7 port d i/o register l (pdiorl) ? sh7016, sh7017 ? bit: 15 14 13 12 11 10 9 8 pd15 ior pd14 ior pd13 ior pd12 ior pd11 ior pd10 ior pd9 ior pd8 ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pd7 ior pd6 ior pd5 ior pd4 ior pd3 ior pd2 ior pd1 ior pd0 ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the port d i/o register l (pdiorl) is a 16-bit read/write register that selects input or output for the sixteen port d pins. bits pd15ior to pd0ior correspond to the pd15/d15 pin to pd0/d0 pin. pdiorl is enabled when the port d pins function as general input/outputs (pd15 to pd0). for other functions, it is disabled. for port d pin functions pd15 to pd0, a given pin in port d is an output pin if its corresponding pdiorl bit is set to 1, and an input pin if the bit is cleared to 0. pdiorl is initialized to h'0000 by external power -on reset; however, it is not initialized for reset by wdt, standby mode, or sleep mode, so the previous data is maintained. the settings in this register are functional only in the sh7016 and sh7017. in the sh7014, there are no pins corresponding to this register, and it should not be read or written to. 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 465 of 716 rej09b0398-0500 16.3.8 port d control register l (pdcrl) ? sh7016, sh7017 ? bit: 15 14 13 12 11 10 9 8 pd15 md pd14 md pd13 md pd12 md pd11 md pd10 md pd9 md pd8 md initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pd7 md pd6 md pd5 md pd4 md pd3 md pd2 md pd1 md pd0 md initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w pdcrl is a 16-bit read/write register that selects the multiplexed pin functions for the least significant sixteen port d pins. th ere are instances when these re gister settings will be ignored, depending on the operation mode. on-chip rom-disabled extended mode: ? mode 0 (8-bit bus): port d pins are data i/o pins; pdcrl settings are disabled. ? mode 1 (16-bit bus): port d pins are data i/o pins; pdcrl settings are disabled. on-chip rom-enabled extended mode: the port d pins are shared as data i/o pins and general i/o pins; pdcrl settings are enabled. single chip mode: the port d pins are general i/o pins; pdcrl settings are disabled. pdcrl is initialized to h'0000 by external power-on reset but is not initialized for reset by wdt, standby mode, or sleep mode, so the previous data is maintained. the settings in this register are functional only in the sh7016 and sh7017. in the sh7014, there are no pins corresponding to this register, and it should not be read or written to. 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 466 of 716 rej09b0398-0500 bit 15 ? pd15 mode (pd15md): selects the function of the pd15/d15 pin. bit 15 pd15md description 0 general input/output (pd15) (initial value) (d15 in on-chip rom invalid mode) 1 data input/output (d15) (pd15 in single chip mode) bit 14 ? pd14 mode (pd14md): selects the function of the pd14/d14 pin. bit 14 pd14md description 0 general input/output (pd14) (initial value) (d14 in on-chip rom invalid mode) 1 data input/output (d14) (pd14 in single chip mode) bit 13 ? pd13 mode (pd13md): selects the function of the pd13/d13 pin. bit 13 pd13md description 0 general input/output (pd13) (initial value) (d13 in on-chip rom invalid mode) 1 data input/output (d13) (pd13 in single chip mode) bit 12 ? pd12 mode (pd12md): selects the function of the pd12/d12 pin. bit 12 pd12md description 0 general input/output (pd12) (initial value) (d12 in on-chip rom invalid mode) 1 data input/output (d12) (pd12 in single chip mode) 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 467 of 716 rej09b0398-0500 bit 11 ? pd11 mode (pd11md): selects the function of the pd11/d11 pin. bit 11 pd11md description 0 general input/output (pd11) (initial value) (d11 in on-chip rom invalid mode) 1 data input/output (d11) (pd11 in single chip mode) bit 10 ? pd10 mode (pd10md): selects the function of the pd10/d10 pin. bit 10 pd10md description 0 general input/output (pd10) (initial value) (d10 in on-chip rom invalid mode) 1 data input/output (d10) (pd10 in single chip mode) bit 9 ? pd9 mode (pd9md): selects the function of the pd9/d9 pin. bit 9 pd9md description 0 general input/output (pd9) (initial value) (d9 in on-chip rom invalid mode) 1 data input/output (d9) (pd9 in single chip mode) bit 8 ? pd8 mode (pd8md): selects the function of the pd8/d8 pin. bit 8 pd8md description 0 general input/output (pd8) (initial value) (d8 in on-chip rom invalid mode) 1 data input/output (d8) (pd8 in single chip mode) 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 468 of 716 rej09b0398-0500 bit 7 ? pd7 mode (pd7md): selects the function of the pd7/d7 pin. bit 7 pd7md description 0 general input/output (pd7) (initial value) (d7 in on-chip rom invalid mode) 1 data input/output (d7) (pd7 in single chip mode) bit 6 ? pd6 mode (pd6md): selects the function of the pd6/d6 pin. bit 6 pd6md description 0 general input/output (pd6) (initial value) (d6 in on-chip rom invalid mode) 1 data input/output (d6) (pd6 in single chip mode) bit 5 ? pd5 mode (pd5md): selects the function of the pd5/d5 pin. bit 5 pd5md description 0 general input/output (pd5) (initial value) (d5 in on-chip rom invalid mode) 1 data input/output (d5) (pd5 in single chip mode) bit 4 ? pd4 mode (pd4md): selects the function of the pd4/d4 pin. bit 4 pd4md description 0 general input/output (pd4) (initial value) (d4 in on-chip rom invalid mode) 1 data input/output (d4) (pd4 in single chip mode) 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 469 of 716 rej09b0398-0500 bit 3 ? pd3 mode (pd3md): selects the function of the pd3/d3 pin. bit 3 pd3md description 0 general input/output (pd3) (initial value) (d3 in on-chip rom invalid mode) 1 data input/output (d3) (pd3 in single chip mode) bit 2 ? pd2 mode (pd2md): selects the function of the pd2/d2 pin. bit 2 pd2md description 0 general input/output (pd2) (initial value) (d2 in on-chip rom invalid mode) 1 data input/output (d2) (pd2 in single chip mode) bit 1 ? pd1 mode (pd1md): selects the function of the pd1/d1 pin. bit 1 pd1md description 0 general input/output (pd1) (initial value) (d1 in on-chip rom invalid mode) 1 data input/output (d1) (pd1 in single chip mode) bit 0 ? pd0 mode (pd0md): selects the function of the pd0/d0 pin. bit 0 pd0md description 0 general input/output (pd0) (initial value) (d0 in on-chip rom invalid mode) 1 data input/output (d0) (pd0 in single chip mode) 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 470 of 716 rej09b0398-0500 16.3.9 port e i/o register (peior) the port e i/o register (peior) is a 16-bit read/write register that selects input or output for the 16 port e pins. bits pe15ior to pe0ior correspond to pins pe15/dack1 to pe0/tioc0a/ dreq0 . peior is enabled when the port e pins function as general input/outputs (pe15 to pe0) or tioc pin of the mtu. for other functions, it is disabled. when the port e pin functions are as pe15 to pe0, or tioc pin of the mtu, a given pin in port e is an output pin if its corresponding peior bit is set to 1, and an input pin if the bit is cleared to 0. peior is initialized to h'0000 by external power-o n reset; however, it is not initialized for reset by wdt, standby mode, or sleep mode, so the previous data is maintained. bit: 15 14 13 12 11 10 9 8 pe15 ior pe14 ior pe13 ior pe12 ior pe11 ior pe10 ior pe9 ior pe8 ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pe7 ior pe6 ior pe5 ior pe4 ior pe3 ior pe2 ior pe1 ior pe0 ior initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 471 of 716 rej09b0398-0500 16.3.10 port e control registers 1, 2 (pecr1 and pecr2) pecr1 and pecr2 are 16-bit read/write registers that select the functions of the sixteen multiplexed pins of port e. pecr1 selects the f unctions of the upper eight bit pins of port e; pecr2 selects the function of the lower eight bit pins of port e. port e includes a bus control signal ( ah ) and dmac control signals (dack1, dack0, drak1, and drak0), but in the sh7016 and sh7017, settings in these registers relating to the selection of these pin functions may be invalid in single-chip mode. for details, see table 16.3, pin functions in each operating mode. pecr1 and pecr2 are both initialized to h'0000 by external power-on reset but are not initialized for reset by wdt, standby mode, or sleep mode, so the previous data is maintained. port e control register 1 (pecr1): bit: 15 14 13 12 11 10 9 8 pe15 md1 pe15 md0 pe14 md1 pe14 md0 ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bits 15 and 14 ? pe15 mode 1, 0 (pe15md1 and pe15md0): these bits select the function of the pe15/dack1 pin. bit 15 pe15md1 bit 14 pe15md0 description 0 0 input/output (pe15) (initial value) 1 reserved 1 0 dma request received output (dack1) (pe15 in single-chip mode) 1 reserved 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 472 of 716 rej09b0398-0500 bits 13 and 12 ? pe14 mode 1, 0 (pe14md1 and pe14md0): these bits select the function of the pe14/dack0/ ah pin. bit 13 pe14md1 bit 12 pe14md0 description 0 0 input/output (pe14) (initial value) 1 reserved 1 0 dma request received output (dack0) (pe14 in single-chip mode) 1 address hold output ( ah ) (pe14 in single-chip mode) bits 11 to 0 ? reserved: these bits always reads as 0. the write values should always be 0. port e control register 2 (pecr2): bit: 15 14 13 12 11 10 9 8 ? pe7md ? pe6md ? pe5md ? pe4md initial value: 0 0 0 0 0 0 0 0 r/w: r r/w r r/w r r/w r r/w bit: 7 6 5 4 3 2 1 0 pe3 md1 pe3 md0 pe2 md1 pe2 md0 pe1 md1 pe1 md0 pe0 md1 pe0 md0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 15 ? reserved: this bit always reads as 0. the write value should always be 0. bit 14 ? pe7 mode (pe7md): selects the function of the pe7/tioc2b pin. bit 14 pe7md description 0 general input/output (pe7) (initial value) 1 mtu input capture input/output compare output (tioc2b) bit 13 ? reserved: this bit always reads as 0. the write value should always be 0. 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 473 of 716 rej09b0398-0500 bit 12 ? pe6 mode (pe6md): selects the function of the pe6/tioc2a pin. bit 12 pe6md description 0 general input/output (pe6) (initial value) 1 mtu input capture input/output compare output (tioc2a) bit 11 ? reserved: this bit always reads as 0. the write value should always be 0. bit 10 ? pe5 mode (pe5md): selects the function of the pe5/tioc1b pin. bit 10 pe5md description 0 general input/output (pe5) (initial value) 1 mtu input capture input/output compare output (tioc1b) bit 9 ? reserved: this bit always reads as 0. the write value should always be 0. bit 8 ? pe4 mode (pe4md): selects the function of the pe4/tioc1a pin. bit 8 pe4md description 0 general input/output (pe4) (initial value) 1 mtu input capture input/output compare output (tioc1a) bits 7 and 6 ? pe3 mode 1, 0 (pe3md1 and pe3md0): these bits select the function of the pe3/tioc0d/drak1 pin. bit 7 pe3md1 bit 6 pe3md0 description 0 0 general input/output (pe3) (initial value) 1 mtu input capture input/output compare output (tioc0d) 1 0 dreq1 request received output (drak1) (pe3 in single-chip mode) 1 reserved 16. pin function controller (pfc) rev.5.00 sep. 27, 2007 page 474 of 716 rej09b0398-0500 bits 5 and 4 ? pe2 mode 1, 0 (pe2md1 and pe2md0): these bits select the function of the pe2/tioc0c/ dreq1 pin. bit 5 pe2md1 bit 4 pe2md0 description 0 0 general input/output (pe2) (initial value) 1 mtu input capture input/output compare output (tioc0c) 1 0 dreq1 request receive input (pe2 in single-chip mode) 1 reserved bits 3 and 2 ? pe1 mode 1, 0 (pe1md1 and pe1md0): these bits select the function of the pe1/tioc0b/drak0 pin. bit 3 pe1md1 bit 2 pe1md0 description 0 0 general input/output (pe1) (initial value) 1 mtu input capture input/output compare output (tioc0b) 1 0 dreq0 request received output (drak0) (pe1 in single-chip mode) 1 reserved bits 1 and 0 ? pe0 mode 1, 0 (pe0md1 and pe0md0): these bits select the function of the pe0/tioc0a/ dreq0 pin. bit 1 pe0md1 bit 0 pe0md0 description 0 0 general input/output (pe0) (initial value) 1 mtu input capture input/output compare output (tioc0a) 1 0 dreq0 request receive input (pe0 in single-chip mode) 1 reserved 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 475 of 716 rej09b0398-0500 section 17 i/o ports (i/o) 17.1 overview the sh7016 and sh7017 have six ports, a to f, and the sh7014 has four ports, a, b, e, and f. the pins of the ports are multiplexed for use as general-purpose i/os (the port f pins are general input) or for other functions. use the pin function controller (pfc) to select the function of multiplexed pins. the ports each have one data register for storing pin data. the initialize function after power-on reset differs depending on the opera ting mode of each pin. see tables 16.2 and 16.3, pin arrangement by mode, for details. 17.2 port a port a is a 16-pin input/output port (11-pin in the sh7014) as shown in table 17.1. 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 476 of 716 rej09b0398-0500 table 17.1 port a rom disabled extended mode (modes 0, 1) rom enabled extended mode (mode 2) * single chip mode * pa15 (i/o)/ck (output) pa15 (i/o)/ck (output) pa15 (i/o)/ck (output) rd (output) pa14 (i/o)/ rd (output) pa14 (i/o) wrh (output) pa13 (i/o)/ wrh (output) pa13 (i/o) wrl (output) pa12 (i/o)/ wrl (output) pa12 (i/o) cs1 (output) pa11 (i/o)/ cs1 (output) pa11 (i/o) cs0 (output) pa10 (i/o)/ cs0 (output) pa10 (i/o) pa9 (i/o)/tclkd (input)/ irq3 (input) pa9 (i/o)/tclkd (input)/ irq3 (input) pa9 (i/o)/tclkd (input)/ irq3 (input) pa8 (i/o)/tclkc (input)/ irq2 (input) pa8 (i/o)/tclkc (input)/ irq2 (input) pa8 (i/o)/tclkc (input)/ irq2 (input) pa7 (i/o)/tclkb (input)/ cs3 (input) pa7 (i/o)/tclkb (input)/ cs3 (input) pa7 (i/o)/tclkb (input) pa6 (i/o)/tclka (input)/ cs2 (input) pa6 (i/o)/tclka (input)/ cs2 (input) pa6 (i/o)/tclka (input) pa5 (i/o)/sck1 (i/o)/ dreq1 (input)/ irq1 (input) pa5 (i/o)/sck1 (i/o)/ dreq1 (input)/ irq1 (input) pa5 (i/o)/sck1 (i/o)/ irq1 (input) pa4 (i/o)/txd1 (output) pa4 (i/o)/tx d1 (output) pa4 (i/o)/txd1 (output) pa3 (i/o)/rxd1 (input) pa3 (i/o)/rx d1 (input) pa3 (i/o)/rxd1 (input) pa2 (i/o)/sck0 (i/o)/ dreq0 (input)/ irq0 (input) pa2 (i/o)/sck0 (i/o)/ dreq0 (input)/ irq0 (input) pa2 (i/o)/sck0 (i/o)/ irq0 (input) pa1 (i/o)/txd0 (output) pa1 (i/o)/tx d0 (output) pa1 (i/o)/txd0 (output) pa0 (i/o)/rxd0 (input) pa0 (i/o)/rx d0 (input) pa0 (i/o)/rxd0 (input) note: * sh7016, sh7017 only. 17.2.1 register configuration table 17.2 summarizes the port a register. table 17.2 port a register name abbreviation r/w initial value address access size port a data register l padrl r/w h'0000 h'ffff8382 h'ffff8383 8, 16, 32 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 477 of 716 rej09b0398-0500 17.2.2 port a data register l (padrl) bit: 15 14 13 12 11 10 9 8 pa15dr pa14dr pa13dr pa12dr pa11dr pa10dr pa9dr pa8dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w * r/w * r/w * r/w * r/w * r/w r/w bit: 7 6 5 4 3 2 1 0 pa7dr pa6dr pa5dr pa4 dr pa3dr pa2dr pa1dr pa0dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * r only in the sh7014. padrl is a 16-bit read/write register that stores data for port a. the bits pa15dr to pa0dr correspond to the pa15/ck to pa0/rxd0 pins. when the pins are used as ordinary outputs, they will output whatever value is written in the padrl; when padrl is read, the register value will be output regardless of the pin status. when the pins are used as ordinary inputs, the pin status rather than the register value is read directly when padrl is read. when a value is written to padrl, that value can be written into padrl, but it will not affect the pin status. table 17.3 shows the read/write operations of the port a data register. padrl is initialized by an external power-on reset. however, padrl is not initialized for a reset by wdt, standby mode, or sleep mode. the settings of bits 14 to 10 of this register are functional only in the sh7016 and sh7017. in the sh7014, there are no pins corresponding to bits 14 to 10; these bits are always read as 0, and their write value should always be 0. table 17.3 read/write operation of the port a data register (padr) paior pin status read write 0 ordinary input pin status can write to padr, but it has no effect on pin status other function pin status can write to padr, but it has no effect on pin status 1 ordinary output padr value value written is output by pin other function padr value can write to padr, but it has no effect on pin status 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 478 of 716 rej09b0398-0500 17.3 port b port b is a 10-pin input/output port (8-pin in the sh7014) as shown in table 17.4. table 17.4 port b rom disabled extended mode (modes 0, 1) rom enabled extended mode (mode 2) * single chip mode * pb9 (i/o)/ irq7 (input)/ a21 (output) pb9 (i/o)/ irq7 (input)/ a21 (output) pb9 (i/o)/ irq7 (input) pb8 (i/o)/ irq6 (input)/ a20 (output)/ wait (input) pb8 (i/o)/ irq6 (input)/ a20 (output)/ wait (input) pb8 (i/o)/ irq6 (input) pb7 (i/o)/a19 (output) pb7 (i/o)/a19 (output) pb7 (i/o) pb6 (i/o)/a18 (output) pb6 (i/o)/a18 (output) pb6 (i/o) pb5 (i/o)/ irq3 (input)/rdwr (output) pb5 (i/o)/ irq3 (input)/ rdwr (output) pb5 (i/o)/ irq3 (input) pb4 (i/o)/ irq2 (input)/ cash (output) pb4 (i/o)/ irq2 (input)/ cash (output) pb4 (i/o)/ irq2 (input) pb3 (i/o)/ irq1 (input)/ casl (output) pb3 (i/o)/ irq1 (input)/ casl (output) pb3 (i/o)/ irq1 (input) pb2 (i/o)/ irq0 (input)/ ras (output) pb2 (i/o)/ irq0 (input)/ ras (output) pb2 (i/o)/ irq0 (input) a17 (output) pb1 (i/o)/a17 (output) pb1 (i/o) a16 (output) pb0 (i/o)/a16 (output) pb0 (i/o) note: * sh7016 and sh7017 only. 17.3.1 register configuration table 17.5 summarizes the port b register. table 17.5 port b register name abbreviation r/w initial value address access size port b data register pbdr r/w h'0000 h'ffff8390 h'ffff8391 8, 16, 32 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 479 of 716 rej09b0398-0500 17.3.2 port b data register (pbdr) bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? pb9dr pb8dr initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r/w r/w bit: 7 6 5 4 3 2 1 0 pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w * r/w * note: * r only in the sh7014. pbdr is a 16-bit read/write register that stor es data for port b. the bits pb9dr to pb0dr correspond to the pb9/ irq7 /a21 to pb0/a16 pins. when the pins are used as ordinary outputs, they will output whatever value is written in the pbdr; when pbdr is read, the register value will be read regardless of the pin status. when the pins are used as ordinary inputs, the pin status rather than the register value is read directly when pbdr is read. when a value is written to pbdr, that value can be written into pbdr, but it will not affect the pin status. table 17.6 shows the read/write operations of the port b data register. pbdr is initialized by an external power-on reset. however, pbdr is not initialized for a reset by wdt, standby mode, or sleep mode. the settings of bits 1 and 0 of this register are functional only in the sh7016 and sh7017. in the sh7014, there are no pins corresponding to these bits; they are always read as 0, and their write value should always be 0. table 17.6 read/write operation of the port b data register (pbdr) pbior pin status read write 0 ordinary input pin status can write to pbdr, but it has no effect on pin status other function pin status can write to pbdr, but it has no effect on pin status 1 ordinary output pbdr value value written is output by pin other function pbdr value can write to pbdr, but it has no effect on pin status 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 480 of 716 rej09b0398-0500 17.4 port c ? sh7016, sh7017 ? port c is a 16 pin input/output port as listed in table 17.7. there is no port c in the sh7014. table 17.7 port c rom disabled extended mode (modes 0, 1) rom enabled extended mode (mode 2) single chip mode a15 (output) pc15 (i/o)/a15 (output) pc15 (i/o) a14 (output) pc14 (i/o)/a14 (output) pc14 (i/o) a13 (output) pc13 (i/o)/a13 (output) pc13 (i/o) a12 (output) pc12 (i/o)/a12 (output) pc12 (i/o) a11 (output) pc11 (i/o)/a11 (output) pc11 (i/o) a10 (output) pc10 (i/o)/a10 (output) pc10 (i/o) a9 (output) pc9 (i/o)/ a9 (output) pc9 (i/o) a8 (output) pc8 (i/o)/ a8 (output) pc8 (i/o) a7 (output) pc7 (i/o)/ a7 (output) pc7 (i/o) a6 (output) pc6 (i/o)/ a6 (output) pc6 (i/o) a5 (output) pc5 (i/o)/ a5 (output) pc5 (i/o) a4 (output) pc4 (i/o)/ a4 (output) pc4 (i/o) a3 (output) pc3 (i/o)/ a3 (output) pc3 (i/o) a2 (output) pc2 (i/o)/ a2 (output) pc2 (i/o) a1 (output) pc1 (i/o)/ a1 (output) pc1 (i/o) a0 (output) pc0 (i/o)/ a0 (output) pc0 (i/o) 17.4.1 register configuration table 17.8 summarizes the port c register. table 17.8 port c register name abbreviation r/w initial value address access size port c data register pcdr r/w h'0000 h'ffff8392 h'ffff8393 8, 16, 32 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 481 of 716 rej09b0398-0500 17.4.2 port c data register (pcdr) bit: 15 14 13 12 11 10 9 8 pc15dr pc14dr pc13dr pc12dr pc11dr pc10dr pc9dr pc8dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w pcdr is a 16-bit read/write register that stor es data for port c. the bits pc15dr to pc0dr correspond to the pc15/a15 to pc0/a0 pins. when the pins are used as ordinary outputs, they will output whatever value is written in the pcdr; when pcdr is read, the register value will be read regardless of the pin status. when the pins are used as ordinary inputs, the pin status rather than the register value is read directly when pc dr is read. when a value is written to pcdr, that value can be written into pcdr, but it will not affect the pin status. table 17.9 shows the read/write operations of the port c data register. pcdr is initialized by an external power-on reset. however, pcdr is not initialized for a reset by wdt, standby mode, or sleep mode. the settings in this register are functional only in the sh7016 and sh7017. in the sh7014, there are no pins corresponding to this register, and it should not be read or written to. table 17.9 read/write operation of the port c data register (pcdr) pcior pin status read write 0 ordinary input pin status can write to pcdr, but it has no effect on pin status other function pin status can write to pcdr, but it has no effect on pin status 1 ordinary output pcdr value value written is output by pin other function pcdr value can write to pcdr, but it has no effect on pin status 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 482 of 716 rej09b0398-0500 17.5 port d ? sh7016, sh7017 ? port d is a 16-pin input/output port, as shown in table 17.10. there is no port d in the sh7014. table 17.10 port d extended mode without rom (mode 0) extended mode without rom (mode 1) extended mode with rom (mode 2) single chip mode d15 (i/o) d15 (i/o) pd15 ( i/o)/d15 (i/o ) pd15 (i/o) d14 (i/o) d14 (i/o) pd14 ( i/o)/d14 (i/o ) pd14 (i/o) d13 (i/o) d13 (i/o) pd13 ( i/o)/d13 (i/o ) pd13 (i/o) d12 (i/o) d12 (i/o) pd12 ( i/o)/d12 (i/o ) pd12 (i/o) d11 (i/o) d11 (i/o) pd11 ( i/o)/d11 (i/o ) pd11 (i/o) d10 (i/o) d10 (i/o) pd10 ( i/o)/d10 (i/o ) pd10 (i/o) d9 (i/o) d9 (i/o) pd9 (i/o)/d9 (i/o) pd9 (i/o) d8 (i/o) d8 (i/o) pd8 (i/o)/d8 (i/o) pd8 (i/o) d7 (i/o) d7 (i/o) pd7 (i/o)/d7 (i/o) pd7 (i/o) d6 (i/o) d6 (i/o) pd6 (i/o)/d6 (i/o) pd6 (i/o) d5 (i/o) d5 (i/o) pd5 (i/o)/d5 (i/o) pd5 (i/o) d4 (i/o) d4 (i/o) pd4 (i/o)/d4 (i/o) pd4 (i/o) d3 (i/o) d3 (i/o) pd3 (i/o)/d3 (i/o) pd3 (i/o) d2 (i/o) d2 (i/o) pd2 (i/o)/d2 (i/o) pd2 (i/o) d1 (i/o) d1 (i/o) pd1 (i/o)/d1 (i/o) pd1 (i/o) d0 (i/o) d0 (i/o) pd0 (i/o)/d0 (i/o) pd0 (i/o) 17.5.1 register configuration table 17.11 summarizes the port d register. table 17.11 port d register name abbreviation r/w initial value address access size port d data register l pddrl r/w h'0000 h'ffff83a2 h'ffff83a3 8, 16, 32 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 483 of 716 rej09b0398-0500 17.5.2 port d data register l (pddrl) bit: 15 14 13 12 11 10 9 8 pd15dr pd14dr pd13dr pd12dr pd11dr pd10dr pd9dr pd8dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w pddrl is a 16-bit read/write register that stores data for port d. the bits pd15dr to pd0dr correspond to the pd15/d15 to pd0/d0 pins. when the pins are used as ordinary outputs, they will output whatever value is written in the pddrl; when pddrl is read, the register value will be read regardless of the pin status. when the pins are used as ordinary inputs, the pin status rather than the register value is read directly when pddrl is read. when a value is written to pddrl, that value can be written into pddrl, but it will not affect the pin status. table 17.12 shows the read/write operations of the port d data register. pddrl is initialized by an external power-on reset. however, pddrl is not initialized for a reset by wdt, standby mode, or sleep mode. the settings in this register are functional only in the sh7016 and sh7017. in the sh7014, there are no pins corresponding to this register, and it should not be read or written to. table 17.12 read/write operation of the port d data register (pddr) pdior pin status read write 0 ordinary input pin status can write to pddr, but it has no effect on pin status other function pin status can write to pddr, but it has no effect on pin status 1 ordinary output pddr value value written is output by pin other function pddr value can write to pddr, but it has no effect on pin status 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 484 of 716 rej09b0398-0500 17.6 port e port e is a 16-pin input/output port, as listed in table 17.13. table 17.13 port e extended modes (modes 0, 1, 2) * 1 single chip mode * 2 pe15 (i/o)/ dack1 (output) pe15 (i/o) pe14 (i/o)/dack0 (output)/ ah (output) pe14 (i/o) pe13 (i/o) pe13 (i/o) pe12 (i/o) pe12 (i/o) pe11 (i/o) pe11 (i/o) pe10 (i/o) pe10 (i/o) pe9 (i/o) pe9 (i/o) pe8 (i/o) pe8 (i/o) pe7 (i/o)/tioc2b (i/o) pe7 (i/o)/tioc2b (i/o) pe6 (i/o)/tioc2a (i/o) pe6 (i/o)/tioc2a (i/o) pe5 (i/o)/tioc1b (i/o) pe5 (i/o)/tioc1b (i/o) pe4 (i/o)/tioc1a (i/o) pe4 (i/o)/tioc1a (i/o) pe3 (i/o)/tioc0d (i/o)/drak1 (output) pe3 (i/o)/tioc0d (i/o) pe2 (i/o)/tioc0c (i/o)/ dreq1 (input) pe2 (i/o)/tioc0c (i/o) pe1 (i/o)/tioc0b (i/o)/drak0 (output) pe1 (i/o)/tioc0b (i/o) pe0 (i/o)/tioc0a (i/o)/ dreq0 (input) pe0 (i/o)/tioc0a (i/o) notes: 1. modes 0 and 1 only in the sh7014. 2. sh7016 and sh7017 only. 17.6.1 register configuration table 17.14 summarizes the port e register. table 17.14 port e register name abbreviation r/w initial value address access size port e data register pedr r/w h'0000 h'ffff83b0 h'ffff83b1 8, 16, 32 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 485 of 716 rej09b0398-0500 17.6.2 port e data register (pedr) bit: 15 14 13 12 11 10 9 8 pe15dr pe14dr pe13dr pe12dr pe11dr pe10dr pe9dr pe8dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit: 7 6 5 4 3 2 1 0 pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w pedr is a 16-bit read/write register that stores data for port e. the bits pe15dr to pe0dr correspond to the pe15/dack1 to pe0/tioc0a/ dreq0 pins. when the pins are used as ordinary outputs, they will output whatever value is written in the pedr; when pedr is read, the register value will be read regardless of the pin st atus. when the pins are used as ordinary inputs, the pin status rather than the register value is r ead directly when pedr is read. when a value is written to pedr, that value can be written into pedr, but it will not affect the pin status. table 17.15 shows the read/write operations of the port e data register. pedr is initialized by a external power-on reset. however, pedr is not initialized for a reset by wdt, standby mode, or sleep mode, so the previous data is retained. table 17.15 read/write operation of the port e data register (pedr) peior pin status read write 0 ordinary input pin status can write to pedr, but it has no effect on pin status other function pin status can write to pedr, but it has no effect on pin status 1 ordinary output pedr value value written is output by pin other function pedr value can write to pedr, but it has no effect on pin status 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 486 of 716 rej09b0398-0500 17.7 port f port f is an 8-pin input port. all modes are configured in the following way: ? pf7 (input)/an7 (input) ? pf6 (input)/an6 (input) ? pf5 (input)/an5 (input) ? pf4 (input)/an4 (input) ? pf3 (input)/an3 (input) ? pf2 (input)/an2 (input) ? pf1 (input)/an1 (input) ? pf0 (input)/an0 (input) 17.7.1 register configuration table 17.16 summarizes the port f register. table 17.16 port f register name abbreviation r/w initial value address access size port f data register pfdr r external pin dependent h'ffff83b3 8 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 487 of 716 rej09b0398-0500 17.7.2 port f data register (pfdr) bit: 7 6 5 4 3 2 1 0 pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr initial value: * * * * * * * * r/w: r r r r r r r r note: * initial values are dependent on the status of the pins at the time of the reads. pfdr is an 8-bit read-only register that stores data for port f. the bits pf7dr to pf0dr correspond to the pf7/an7 to pf0/an0 pins. any value written into these bits is ignored, and there is no effect on the status of the pins. when a ny of the bits are read, th e pin status rather than the bit value is read directly. however, when an a/d converter analog input is being sampled, values of 1 are read out. table 17.17 shows the read/write operations of the port f data register. pfdr is not initialized by power-on resets, standby m ode, or sleep mode (the bits always reflect the pin status). table 17.17 read/write operation of the port f data register (pfdr) pin i/o pin function read write input ordinary pin status is read ignored (no effect on pin status) ann: analog input 1 is read ignored (no effect on pin status) note: n = 7 to 0 17. i/o ports (i/o) rev.5.00 sep. 27, 2007 page 488 of 716 rej09b0398-0500 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 489 of 716 rej09b0398-0500 section 18 128 kb flash memory (f-ztat) 18.1 features the sh7017 has 128 kbytes of on-chip flash memory. the features of the flash memory are summarized below. ? four flash memory operating modes ? program mode ? erase mode ? program-verify mode ? erase-verify mode ? programming/erase methods the flash memory is programmed 32 bytes at a time. block erase (in single-block units) can be performed. erasing the entire memory requires eras ure of each block in turn. block erasing can be performed as required on 1 kb, 28 kb, and 32 kb blocks. ? programming/erase times the flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming, equivalent to 300 s (typ.) per byte, and the erase time is 100 ms (typ.) per block. ? reprogramming capability the flash memory can be reprogrammed up to 100 times. ? on-board programming modes there are two modes in which flash memory can be programmed/erased/verified on-board: ? boot mode ? user program mode ? automatic bit rate adjustment with data transfer in boot mode, the sh7017's bit rate can be automatically adjusted to match the transfer bit rate of the host. ? flash memory emulation in ram flash memory programming can be emulated in real time by overlapping a part of ram onto flash memory. ? protect modes there are two protect modes, hardware and so ftware, which allow protected status to be designated for flash memory program/erase/verify operations ? programmer mode flash memory can be programmed/erased in programmer mode, using a prom programmer, as well as in on-board programming mode. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 490 of 716 rej09b0398-0500 18.2 overview 18.2.1 block diagram module bus bus interface/controller flash memory (128 kb) operating mode flmcr2 internal address bus internal data bus (32 bits) fwp pin mode pin ebr1 ramer flmcr1 legend: flmcr1: flash memory control register 1 flmcr2: flash memory control register 2 ebr1: erase block register 1 ramer: ram emulation register figure 18.1 block diagram of flash memory 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 491 of 716 rej09b0398-0500 18.2.2 mode transitions when the mode pins and the fwp pin are set in the reset state a nd a reset-start is executed, the sh7017 enters one of the operating modes shown in figure 18.2. in user mode, flash memory can be read but not programmed or erased. flash memory can be programmed and erased in boot mode, user program mode, and programmer mode. boot mode on-board pro g rammin g mode user pro g ram mode user mode reset state pro g rammer mode res = 0 fwp = 0 fwp = 1 * 1 * 1 * 2 notes: only make a transition between user mode and user pro g ram mode when the cpu is not accessin g the flash memory. 1. ram emulation possible 2. md0 = 1, md1 = 0, md2 = 1, md3 = 1 res = 0 md1 = 0, fwp = 0 res = 0 res = 0 md1 = 1, fwp = 1 md1 = 1, fwp = 0 figure 18.2 flash memory mode transitions 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 492 of 716 rej09b0398-0500 18.2.3 on-board programming modes boot mode flash memory sh7017 ram host programming control program sci1 application program (old version) new application program flash memory sh7017 ram host sci1 application program (old version) boot program area new application program flash memory sh7017 ram host sci1 flash memory erase boot program new application program flash memory sh7017 program execution state ram host sci1 new application program boot program programming control program 1. initial state the old program version or data remains written in the flash memory. the user should prepare the programming control program and new application program beforehand in the host. 2. programming control program transfer when boot mode is entered, the boot program in the sh7050 (originally incorporated in the chip) is started and the programming control program in the host is transferred to ram via sci communication. the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, entire flash memory erasure is performed, without regard to blocks. 4. writing new application program the programming control program transferred from the host to ram is executed, and the new application program in the host is written into the flash memory. programming control program boot program boot program boot program area boot program area programming control program figure 18.3 boot mode 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 493 of 716 rej09b0398-0500 user program mode flash memory sh7017 ram host programming/ erase control program sci boot program new application program flash memory sh7017 ram host sci new application program flash memory sh7017 ram host sci flash memory erase boot program new application program flash memory sh7017 program execution state ram host sci boot program boot program fwp assessment program application program (old version) new application program 1. initial state the fwp assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the programming/erase control program should be prepared in the host or in the flash memory. 2. programming/erase control program transfer when user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to ram. 3. flash memory initialization the programming/erase program in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. programming/ erase control program programming/ erase control program programming/ erase control program transfer program application program (old version) transfer program fwp assessment program fwp assessment program transfer program fwp assessment program figure 18.4 user program mode 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 494 of 716 rej09b0398-0500 18.2.4 flash memory emulation in ram emulation should be performed in user mode or user program mode. when the emulation block set in ramer is accessed while the emulation f unction is being executed, data written in the overlap ram is read. ? user mode ? user program mode application pro g ram execution state flash memory emulation block ram sci overlap ram (emulation is performed on data written in ram) figure 18.5 emulation when overlap ram data is confirmed, the rams bit is cleared, ram overlap is released, and writes should actually be performed to the flash memory. when the programming control program is tran sferred to ram, ensure that the transfer destination and the overlap ram do not overlap, as this will cause data in the overlap ram to be rewritten. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 495 of 716 rej09b0398-0500 ? user program mode application program flash memory ram sci programming control program execution state overlap ram (programming data) programming data figure 18.6 programming to the flash memory 18.2.5 differences between boot mode and user program mode table 18.1 differences between boot mode and user program mode boot mode user program mode entire memory erase yes yes block erase no yes programming control program * (2) (1) (2) (3) (1) erase/erase-verify (2) program/program-verify (3) emulation note: * to be provided by the user, in accordance with the recommended algorithm. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 496 of 716 rej09b0398-0500 18.2.6 block configuration the flash memory is divided into three 32 kb blocks, one 28 kb blocks, and four 1 kb blocks. address h'00000 address h'1ffff 32 kb 32 kb 32 kb 1 kb 1 kb 1 kb 1 kb 28 kb 128 kb figure 18.7 block configuration 18.3 pin configuration the flash memory is controlled by means of the pins shown in table 18.2. table 18.2 flash memory pins pin name abbreviation i/o function power-on reset res input power-on reset flash memory protect fwp input flash program/erase protection by hardware mode 3 md3 input sets sh7017 operating mode mode 2 md2 input sets sh7017 operating mode mode 1 md1 input sets sh7017 operating mode mode 0 md0 input sets sh7017 operating mode transmit data txd1 output serial transmit data output receive data rxd1 input serial receive data input 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 497 of 716 rej09b0398-0500 18.4 register configuration the registers used to control the on-chip flash memory when enabled are shown in table 18.3. table 18.3 flash memory registers register name abbreviation r/w initial value address access size flash memory control register 1 flmcr1 r/w * 1 h'00 * 3 h'ffff8580 8 flash memory control register 2 flmcr2 r * 2 h'00 h'ffff8581 8 erase block register 1 ebr1 r/w * 1 h'00 * 4 h'ffff8582 8 ram emulation register ramer r/w h'0000 h'ffff8628 8, 16, 32 notes: flmcr1, flmcr2, and ebr1 are 8-bit registers, and ramer is a 16-bit register. only byte accesses are valid for flmcr1, flmcr2, and ebr1, the access requiring 3 cycles. three cycles are required for a byte or word access to ramer, and 6 cycles for a longword access. when a longword write is performed on ramer, 0 must always be written to the lower word (address h'ffff8630). operation is not guaranteed if any other value is written. 1. in modes in which the on-chip flash memory is disabled, a read will return h'00, and writes are invalid. writes are also disabled when the fwe bit is set to 1 in flmcr1. 2. a read in a mode in which on-chip flash memory is disabled will return h'00. 3. when a low level is input to the fwp pin, the initial value is h'80. 4. when a high level is input to the fwp pin, or if a low level is input and the swe bit in flmcr1 is not set, these registers are initialized to h'00. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 498 of 716 rej09b0398-0500 18.5 register descriptions 18.5.1 flash memory control register 1 (flmcr1) bit: 7 6 5 4 3 2 1 0 fwe swe esu psu ev pv e p initial value: 1/0 0 0 0 0 0 0 0 r/w: r r/w r/w r/w r/w r/w r/w r/w flmcr1 is an 8-bit register used for flash memory operating mode control. program-verify mode or erase-verify mode is entered by setting swe to 1 when fwe = 1. program mode is entered by setting swe to 1 when fwe = 1, then setting the psu bit, and finally setting the p bit. erase mode is entered by setting swe to 1 when fwe = 1, then setting the esu bit, and finally setting the e bit. flmcr1 is initialized by a reset, and in hardware standby mode and software standby mode. its initial value is h'80 when a high leve l is input to the fwe pin, and h'00 when a low level is input. when on-chip flash memory is di sabled, a read will return h'00, and writes are invalid. writes to bits swe, esu, psu, ev, and pv are enabled only when fwe = 1 and swe = 1; writes to the e bit only when fwe = 1, swe = 1, and esu = 1; and writes to the p bit only when fwe = 1, swe = 1, and psu = 1. bit 7 ? flash write enable bit (fwe): sets hardware protection against flash memory programming/erasing. bit 7 fwe description 0 when a low level is input to the fwp pin (hardware-protected state) (initial value) 1 when a high level is input to the fwp pin 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 499 of 716 rej09b0398-0500 bit 6 ? software write enable bit (swe): enables or disables the flash memory. this bit should be set before setting bits 5 to 0, and ebr1 bits 7 to 0. bit 6 swe description 0 writes disabled (initial value) 1 writes enabled [setting condition] when fwe = 1 bit 5 ? erase setup bit (esu): prepares for a transition to eras e mode. do not set the swe, psu, ev, pv, e, or p bit at the same time. bit 5 esu description 0 erase setup cleared (initial value) 1 erase setup [setting condition] when fwe = 1 and swe = 1 bit 4 ? program setup bit (psu): prepares for a transition to program mode. do not set the swe, esu, ev, pv, e, or p bit at the same time. bit 4 psu description 0 program setup cleared (initial value) 1 program setup [setting condition] when fwe = 1 and swe = 1 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 500 of 716 rej09b0398-0500 bit 3 ? erase-verify (ev): selects erase-verify mode transiti on or clearing. do not set the swe, esu, psu, pv, e, or p bit at the same time. bit 3 ev description 0 erase-verify mode cleared (initial value) 1 transition to erase-verify mode [setting condition] when fwe = 1 and swe = 1 bit 2 ? program-verify (pv): selects program-verify mode transition or clearing. do not set the swe, esu, psu, ev, e, or p bit at the same time. bit 2 pv description 0 program-verify mode cleared (initial value) 1 transition to program-verify mode [setting condition] when fwe = 1 and swe = 1 bit 1 ? erase (e): selects erase mode transition or clearin g. do not set the swe, esu, psu, ev, pv, or p bit at the same time. bit 1 e description 0 erase mode cleared (initial value) 1 transition to erase mode [setting condition] when fwe = 1, swe = 1, and esu = 1 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 501 of 716 rej09b0398-0500 bit 0 ? program (p): selects program mode transition or clearing. do not set the swe, psu, esu, ev, pv, or e bit at the same time. bit 0 p description 0 program mode cleared (initial value) 1 transition to program mode [setting condition] when fwe = 1, swe = 1, and psu = 1 18.5.2 flash memory control register 2 (flmcr2) bit: 7 6 5 4 3 2 1 0 fler ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r flmcr2 is an 8-bit register that monitors the presence or absence of flash memory program/erase protection (error protection). flmcr2 is initialized to h'00 by a reset, and in hardware standby mode. when on-chip flash memory is disabled, a read will return h'00. bit 7 ? flash memory error (fler): indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error- protection state. bit 7 fler description 0 flash memory is operating normally. flash memory program/erase protection (error protection) is disabled. [clearing condition] power-on reset (initial value) 1 an error has occurred during flash memory programming/erasing. flash memory program/erase protection (error protection) is enabled. [setting condition] see section 18.8.3, error protection. bits 6 to 0 ? reserved: these bits are always read as 0. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 502 of 716 rej09b0398-0500 18.5.3 erase block register 1 (ebr1) ebr1 is an 8-bit readable/writa ble register that specifies the flash memory erase area block by block. ebr1 is initialized to h'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin, and when a high level is input to the fwe pin and the swe bit in flmcr1 is not set. when a bit in ebr1 is set to 1, the corresponding block can be erased. other blocks are erase-protected. set only one bit in ebr1 (more than one bit cannot be set). when on-chip flash memory is di sabled, a read will return h'00, and writes are invalid. the flash memory block configuration is shown in table 18.4. bit: 7 6 5 4 3 2 1 0 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w table 18.4 flash memory erase blocks block (size) address eb0 (32 kb) h'000000 to h'007fff eb1 (32 kb) h'008000 to h'00ffff eb2 (32 kb) h'010000 to h'017fff eb3 (28 kb) h'018000 to h'01efff eb4 (1 kb) h'01f000 to h'01f3ff eb5 (1 kb) h'01f400 to h'01f7ff eb6 (1 kb) h'01f800 to h'01fbff eb7 (1 kb) h'01fc00 to h'01ffff 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 503 of 716 rej09b0398-0500 18.5.4 ram emulation register (ramer) ramer specifies the area of flash memory to be overlapped with part of ram when emulating real-time flash memory programming. ramer is initialized to h'0000 by a reset and in hardware standby mode. it is not initialized in software standby mode. ramer settings should be made in user mode or user program mode. flash memory area divisions are shown in table 18.5. to ensure correct operation of the emulation function, the rom for which ram emulation is performed should not be accessed immediately after this register has been mo dified. normal execution of an access immediately after register modification is not guaranteed. bit: 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ? ? initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r bit: 7 6 5 4 3 2 1 0 ? ? ? ? ? rams ram1 ram0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r/w r/w r/w bits 15 to 3 ? reserved: these bits are always read as 0. bit 2 ? ram select (rams): specifies selection or non-selection of flash memory emulation in ram. when rams = 1, all flash memory block are program/erase-protected. bit 2 rams description 0 emulation not selected program/erase-protection of all flash memory blocks is disabled (initial value) 1 emulation selected program/erase-protection of all flash memory blocks is enabled bits 1 and 0 ? flash memory area se lection (ram1, ram0): these bits are used together with bit 2 to select the flash memory area to be overlapped with ram. (see table 18.5.) 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 504 of 716 rej09b0398-0500 table 18.5 flash memory area divisions addresses block name rams ram1 ram0 h'fff800 to h'fffbff ram area 1 kb 0 * * h'01f000 to h'01f3ff eb4 (1 kb) 1 0 0 h'01f400 to h'01f7ff eb5 (1 kb) 1 0 1 h'01f800 to h'01fbff eb6 (1 kb) 1 1 0 h'01fc00 to h'01ffff eb7 (1 kb) 1 1 1 legend: * : don't care 18.6 on-board programming modes when pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. there are two on-board programming modes: boot mode and user program mode. the pin settings for transition to each of these modes are shown in table 18.6. for a diagram of the transitions to the various flash memory modes, see figure 18.2. table 18.6 setting on-board programming modes mode pll multiple fwp md3 md2 md1 md0 boot mode expanded mode 1 0 0 0 0 0 single chip mode 0 0 0 1 expanded mode 2 0 1 0 0 single chip mode 0 1 0 1 expanded mode 4 1 0 0 0 single chip mode 1 0 0 1 expanded mode 1 0 0 0 1 0 user program mode single chip mode 0 0 1 1 expanded mode 2 0 1 1 0 single chip mode 0 1 1 1 expanded mode 4 1 0 1 0 single chip mode 1 0 1 1 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 505 of 716 rej09b0398-0500 18.6.1 boot mode when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. the sci to be used is set to channel asynchronous mode. when a reset-start is executed after the sh7017 pins have been set to boot mode, the boot program built into the sh7017 is started and the programming control program prepared in the host is serially transmitted to the sh7017 via the sci. in the sh7017, the programming control program received via the sci is written into the programming control program area in on-chip ram. after the transfer is completed, c ontrol branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). the transferred programming control program must therefore include coding that follows the programming algorithm given later. the system configuration in boot mode is shown in figure 18.8, and the boot mode execution procedure in figure 18.9. rxd1 txd1 sci1 sh7017 flash memory write data reception verify data transmission host on-chip ram figure 18.8 system configuration in boot mode 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 506 of 716 rej09b0398-0500 note: if a memory cell does not operate normally and cannot be erased, one h'ff byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. start set pins to boot mode and execute reset-start host transfers data (h'00) continuously at prescribed bit rate sh7017 measures low period of h'00 data transmitted by host sh7017 calculates bit rate and sets value in bit rate register after bit rate adjustment, sh7017 transmits one h'00 data byte to host to indicate end of adjustment host confirms normal reception of bit rate adjustment end indication (h'00), and transmits one h'55 data byte after receiving h'55, sh7017 transmits one h'aa data byte to host host transmits number of programming control program bytes (n), upper byte followed by lower byte sh7017 transmits received number of bytes to host as verify data (echo-back) n = 1 host transmits programming control program sequentially in byte units sh7017 transmits received programming control program to host as verify data (echo-back) transfer received programming control program to on-chip ram n = n? no yes end of transmission check flash memory data, and if data has already been written, erase all blocks after confirming that all flash memory data has been erased, sh7017 transmits one h'aa data byte to host execute programming control program transferred to on-chip ram n + 1 n figure 18.9 boot mode execution procedure 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 507 of 716 rej09b0398-0500 automatic sci bit rate adjustment start bit stop bit d0 d1 d2 d3 d4 d5 d6 d7 low period (9 bits) measured (h'00 data) hi g h period (1 or more bits) figure 18.10 automatic sci bit rate adjustment when boot mode is initiated, the sh7017 measur es the low period of the asynchronous sci communication data (h'00) transmitted continuo usly from the host. the sci transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. the sh7017 calculates the bit rate of the transmission from the host from the measured low period, and transmits one h'00 byte to the host to indicate the end of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally , and transmit one h'55 byte to the sh7017. if reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. depending on the host's transmission bit rate and the sh7017's system clock frequency, there will be a discrepancy between the b it rates of the host and the sh7017. to ensure correct sci operation, the host's transfer bit rate should be set to 4800bps, 9600bps. table 18.7 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the sh7017 bit rate is possible. the boot program should be executed within this system clock range. table 18.7 system clock frequencies for which automatic adjustment of sh7017 bit rate is possible host bit rate system clock frequency for which automatic adjustment of sh7017 bit rate is possible 9600bps 8 to 28.7mhz 4800bps 4 to 20mhz 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 508 of 716 rej09b0398-0500 on-chip ram area divisions in boot mode: in boot mode, the ram area is divided into an area used by the boot program and an area to which the programming control program is transferred via the sci, as shown in figure 18 .11. the boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. h'fffff000 h'fffff800 h'ffffffff pro g rammin g control pro g ram area (2 kbytes) boot pro g ram area (2 kbytes) figure 18.11 ram areas in boot mode note: the boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to ram. note also that the boot program remains in this area of the on-chip ram even after control branches to the programming control program. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 509 of 716 rej09b0398-0500 18.6.2 user program mode after setting fwp, the user should branch to, and execute, the previously prepared programming/erase control program. as the flash memory itself cannot be read while flash memory programming/erasing is being executed, the control program that performs programming and erasing should be run in on-chip ram or external memory. use the following procedure (figure 18.12) to execute the programming control program that writes to flash memory (when transferred to ram). execute user application pro g ram execute pro g rammin g / erase control pro g ram in ram (flash memory rewritin g ) transfer pro g rammin g /erase control pro g ram to ram fwp = 1 (user pro g ram mode) write fwp assessment pro g ram and transfer pro g ram 1 2 3 4 5 figure 18.12 user program mode execution procedure note: when programming and erasing, start the watchdog timer so that measures can be taken to prevent program runaway, etc. memory cells may not operate normally if overprogrammed or overerased due to program runaway. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 510 of 716 rej09b0398-0500 18.7 programming/erasing flash memory a software method, using the cpu, is employed to program and erase flash memory in the on- board programming modes. there are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. transitions to these modes can be made by setting the psu, esu, p, e, pv, and ev bits in flmcr1. the flash memory cannot be read while being programmed or erased. therefore, the program (programming control program) that controls flash memory programming/erasing should be located and executed in on-chip ram or external memory. notes: 1. operation is not guaranteed if setting/resetting of the swe, esu, psu, ev, pv, e, and p bits in flmcr1 is executed by a program in flash memory. 2. when programming or erasing, a low level is input to the fwp pin (programming/erasing will not be executed if a high level is input to the fwp pin). 3. programming should be performed in th e erased state. do not perform additional programming on previously programmed addresses. 18.7.1 program mode follow the procedure shown in the program/program-verify flowchart in figure 18.7 to write data or programs to flash memory. performing prog ram operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. programming should be carri ed out 32 bytes at a time. following the elapse of 10 s or more after the swe bit is set to 1 in flash memory control register 1 (flmcr1), 32-byte program data is stored in the program data area and reprogram data area, and the 32-byte data in the program data area in ram is written consecutively to the program address (the lower 8 bits of the first address written to must be h'00, h'20, h'40, h'60, h'80, h'a0, h'c0, or h'e0). thirty-two cons ecutive byte data transfers are performed. the program address and program data are latched in the flash memory. a 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, h'ff data must be written to the extra addresses. next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. set a minimum value of 300 s or more as the wdt overflow period. after this, preparation for program mode (program setup) is carried out by setting the psu bit in flmcr1, and after the elapse of 50 s or more, the operating mode is switched to program mode by setting the p bit in flmcr1. the time during which the p bit is set is the flash memory programming time. use a fixed 200 s pulse for the write time. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 511 of 716 rej09b0398-0500 18.7.2 program-verify mode in program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. after the elapse of a given programming time, the programming mode is exited (the p bit in flmcr1 is cleared, th en the psun bit is cleared at least 10 s later). the watchdog timer is cleared after the elapse of 10 s or more, and the operating mode is switched to program-verify mode by setting the pv bit in flmcr1. before reading in program-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of 4 s or more. when the flash memory is read in this state (verify data is read in 32-bit units), the data at the latched address is read. wait at least 2 s after the dummy write before performing this read operation. next, the written data is compared with the verify data, and reprogram data is computed (see figure 18.13) and transferred to the reprogram data area. after 32 bytes of data have been verified, exit program-verify mode, wait for at least 4 s, then clear the swe bit in flmcr1. if reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. however, ensure that the program/program-verify sequence is not repeated more th an 1000 times on the same bits. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 512 of 716 rej09b0398-0500 set swe-bit of flmcr1 wait 10 s n = 1 m = 0 successively write 32-byte data in rewrite data area in ram to flash memory enable wdt set psu bit in flmcr1(2) wait 50 s set psu bit in flmcr1(2) wait 200 s write start set psu bit in flmcr1(2) wait 10 s wait 10 s ng ng ng ng ok ok ok wait 4 s wait 2 s * 4 * 2 * 3 store 32 bytes write data in write data area and rewrite data area * 4 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 5 * 1 wait 4 s set psu bit in flmcr1(2) disable wdt set psu bit in flmcr1(2) perform dummy-write of h'ff to verify address set psu bit in flmcr1(2) clear swe bit of flmcr1 m = 1 write end write data = verify data? 32 byte data verify complete? m = 0? increment address ok clear swe bit of flmcr1 n 1000? n n + 1 notes: start ram write data storage area (32 byte) transfer rewrite data to rewrite data area write end write failure read verify data * 3 operate rewrite data previous write data 0 0 1 1 verify data (v) 0 1 0 1 rewrite data (x) 1 0 1 1 description rewrite should not be performed to bits already written to. write is incomplete; rewrite should be performed. ? left in the erased state. rewrite data storage area (32 byte) data writes must be performed in the memory- erased state. do not write additional data to an address to which data is already written. 1. transfer data in a byte unit. the lower eight bits of the start address to which data is written must be h'00, h'20, h'40, h '60, h'80, h'a0, h'c0, or h'e0. transfer 32-byte data even when writing fewer than 32 bytes. in this case, set h'ff in unused addresses. 2. read verify data in logword form (32 bits). 3. already programmed bits are not reprogrammed. reprogram data is determined by the computation shown below. 4. the write data storage area (32 bytes) and rewrite data storage area (32 bytes) must be located in ram. the contents of the rewrite data storage area are rewritten as writing progresses. 5. set the values of x, y, z, , , , , , and n to match the characteristics of the memory device. figure 18.13 program/pr ogram-verify flowchart 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 513 of 716 rej09b0398-0500 ? sample 32-byte programming program the wait time set values (number of loops) are for the case where f = 28.7 mhz. for other frequencies, the set value is given by the following expression: wait time ( s) f (mhz) 4 registers used r4 (input): program data storage address r5 (input): programming destination address r7 (output): ok (normal) or ng (error) r0 to r3, r8 to r13: work registers flmcr1 .equ h'80 flmcr2 .equ h'81 ok .equ h'0 ng .equ h'1 wait10u .equ 72 wait50u .equ 359 wait4u .equ 29 wait2u .equ 14 wait200u .equ 1435 wdt_tcsr .equ h'ffff8610 wdt_573u .equ h'a579 sweset .equ b'01000000 psu1set .equ b'00010000 p1set .equ b'00000001 p1clear .equ b'11111110 psu1clear .equ b'11101111 pvset .equ b'00000100 pvclear .equ b'11111011 sweclear .equ b'10111111 maxverify .equ 1000 ; flashprogram .equ $ mov #h'01,r2 ; r2 work register (1) mov.l #pdatabuff,r0 ; save program data to work area mov r4,r12 mov #8,r13 copy_loop .equ $ 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 514 of 716 rej09b0398-0500 mov.l @r12+,r1 mov.l r1,@r0 add.l #4,r0 add.l #-1,r13 cmp/pl r13 bt copy_loop mov.l #h'ffff8500,r0 ; initialize gbr ldc r0,gbr ; mov.l #wait10u,r3 mov.l #flmcr1,r0 ; initialize r0 to flcmr1 address or.b #sweset,@(r0,gbr) ; set swe wait_1 subc r2,r3 ; wait 10 s bf wait_1 ; mov.l #h'20000,r9 cmp/gt r5,r9 bt program_start mov.l #flmcr2,r0 program_start .equ $ mov.l #0,r9 ; initialize n (r9) to 0 ; program_loop .equ $ mov.l #0,r10 ; initialize m (r10) to 0 mov.l #32,r3 ; write 32-byte data consecutively mov.l #pdatabuff,r12 mov.l r5,r13 write_loop .equ $ mov.b @r12+,r1 mov.b r1,@r13 add.l #1,r13 add.l #-1,r3 cmp/pl r3 bt write_loop ; mov.l #wdt_tcsr,r1 ; enable wdt mov.w #wdt_573u,r3 ; 573.4 s cycle mov.w r3,@r1 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 515 of 716 rej09b0398-0500 ; mov.l #wait50u,r3 or.b #psu1set,@(r0,gbr) ; set psu wait_2 subc r2,r3 ; wait 50 s bf wait_2 ; mov.l #wait200u,r3 or.b #p1set,@(r0,gbr) ; set p wait_3 subc r2,r3 ; wait 200 s bf wait_3 ; mov.l #wait10u,r3 and.b #p1clear,@(r0,gbr) ; clear p wait_4 subc r2,r3 ; wait 10 s bf wait_4 ; mov.l #wait10u,r3 and.b #psu1clear,@(r0,gbr) ; clear psu wait_5 subc r2,r3 ; wait 10 s bf wait_5 ; mov.l #wdt_tcsr,r1 ; disable wdt mov.w #h'a55f,r3 mov.w r3,@r1 ; mov.l #wait4u,r3 or.b #pvset,@(r0,gbr) ; set pv wait_6 subc r2,r3 ; wait 4 s bf wait_6 ; mov.l pdatabuff,r3 mov.l r4,r1 mov.l r5,r12 mov.l #8,r13 mov.l #h'ffffffff,r11 ; verifyloop .equ $ mov.l r11,@r12 ; write h'ff to verify address 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 516 of 716 rej09b0398-0500 mov.l r11,@r3 ; reprogram data ram (pdatabuff) initialization mov.l #wait2u,r7 wait_7 subc r2,r7 ; wait 2 s bf wait_7 ; mov.l @r12+,r7 mov.l @r1+,r8 cmp/eq r7,r8 ; verify bt verify_ok mov.l #1,r10 ; verify ng, m <- 1 xor r8,r7 ; program data computation not r7,r7 or r7,r8 mov.l r8,@r3 ; store in reprogram data ram (pdatabuff) verify_ok .equ $ add.l #4,r3 add.l #-1,r13 cmp/pl r13 bt verifyloop ; mov.l #wait4u,r7 and.b #pvclear,@(r0,gbr) ; clear pv wait_8 subc r2,r7 ; wait 4 s bf wait_8 ; cmp/pl r10 ; if m=0 then goto program_ok bf program_ok add #1,r9 mov.l #ng,r7 ; r7 <- ng (return value) mov.l #maxverify,r12 ; if n>=maxverify then program ng cmp/eq r9,r12 bt program_end bra program_loop nop program_ok .equ $ mov.l #ok,r7 ; r7 <- ok (return value) program_end .equ $ mov.b #h'00,r0 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 517 of 716 rej09b0398-0500 mov.b r0,@(flmcr1,gbr) ; clear swe ; rts nop ; .align 4 pdatabuff .res.b 32 18.7.3 erase mode when erasing flash memory, the erase/erase-verify flowchart shown in figure 18.14 should be followed. to perform data or program erasure, set the 1 b it flash memory area to be erased in erase block register 1 (ebr1) at least 10 s after setting the swe bit to 1 in flash memory control register 1 (flmcr1). next, the watchdog timer is set to prevent overerasing in the event of program runaway, etc. set 9.2 ms as the wdt overflow period. after this, preparation for erase mode (erase setup) is carried out by setting the esu bit in flmcr1, and after the elapse of 200 s or more, the operating mode is switched to erase mode by setting the e bit in flmcr1. the time during which the e bit is set is the flash memory erase time. ensure that the erase time does not exceed 5 ms. note: with flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all ?0?) is not necessary before starting the erase procedure. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 518 of 716 rej09b0398-0500 18.7.4 erase-verify mode in erase-verify mode, data is read after memory has been erased to ch eck whether it has been correctly erased. after the elapse of the erase time, erase mode is exited (the e bit in flmcr1 is cl eared, then the esu bit is cleared at least 10 s later), the watchdog timer is cl eared after the elapse of 10 s or more, and the operating mode is switched to erase-verify mode by setting the ev bit in flmcr1. before reading in erase-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of 20 s or more. when the flash memory is read in this state (verify data is read in 32-bit units), the data at the latched address is read. wait at least 2 s after the dummy write before performing this read operation. if the read data has been erased (all ?1?), a dummy write is pe rformed to the next address, and erase-verify is performed. if the read data has not been erased, set erase mode again, and repeat the erase/erase- verify sequence in the same way. however, ensu re that the erase/erase-verify sequence is not repeated more than 60 times. when verification is completed, exit erase-verify mode, and wait for at least 5 s. if erasure has been completed on all the erase blocks, clear the swe bit in flmcr1. if there are any unerased blocks, set 1 bit for the flash memory area to be erased, and repeat the erase/erase-verify sequence in the same way. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 519 of 716 rej09b0398-0500 erase complete start set swe bit in flmcr1 set esu-bit of flmcr1 set e-bit of flmcr1 wait 10 s wait 200 s n = 1 set ebr1 wdt enable * 3 wait 5 ms wait 10 s wait 10 s wait 20 s set top block address to verify address wait 2 s wait 5 s * 2 * 4 erase start clear e-bit of flmcr1 clear esu-bit of flmcr1 set ev-bit of flmcr1 dummy write h'ff to verify address read verify data clear ev-bit of flmcr1 wait 5 s clear ev-bit of flmcr1 clear swe-bit in flmcr1 wdt disable erase stop * 1 verify data = all "1" ? last block address ? all objective blocks erased ? erase error clear swe-bit of flmcr1 n > 60 ng ng ng ng ok ok ok ok n n + 1 address increment notes: 1. prepro g rammin g (settin g erase block data to all "0") is not necessary. 2. verify data is read in 32-bit (lon g word) units. 3. set only one bit in ebr1. more than one bit cannot be set. 4. erasin g is performed in block units. to erase a number of blocks, each block must be erased in turn. figure 18.14 erase/erase-verify flowchart (single-block erase) 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 520 of 716 rej09b0398-0500 ? sample one-block erase program the wait time set values (number of loops) are for the case where f = 28.7 mhz. for other frequencies, the set value is given by the following expression: wait time ( s) f (mhz) 4 the wdt overflow cycle set value is for the case where f = 28.7 mhz. for other frequencies, ensure that the overflow cy cle is a minimum of 5.3 ms. registers used r5 (input): memory block table pointer r7 (output): ok (normal) or ng (error) r0 to r3, r6, r8 and r9: work registers flmcr1 .equ h'80 flmcr2 .equ h'81 ebr1 .equ h'82 ebr2 .equ h'83 wait10u .equ 72 wait2u .equ 14 wait200u .equ 1435 wait5m .equ 35875 wait20u .equ 144 wait5u .equ 36 wdt_tcsr .equ h'ffff8610 wdt_9m .equ h'a57d sweset .equ b'01000000 esuset .equ b'00100000 eset .equ b'00000010 eclear .equ b'11111101 esuclear .equ b'11011111 evset .equ b'00001000 evclear .equ b'11110111 sweclear .equ b'10111111 maxerase .equ 60 ; flasherase .equ $ mov.l #h'ffff8500,r0 ldc r0,gbr ; initialize gbr mov.l #1,r2 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 521 of 716 rej09b0398-0500 ; mov.l #wait10u,r3 mov.l #flmcr1,r0 or.b #sweset,@(r0,gbr) ; set swe ewait_1 subc r2,r3 ; wait 10 s bf ewait_1 ; mov.l #0,r9 ; initialize n (r9) to 0 ; mov.b @(6,r5),r0 mov.b r0,@(ebr1,gbr) ; erase memory block (ebr1) setting mov.b @(7,r5),r0 mov.b r0,@(ebr2,gbr) ; erase memory block (ebr2) setting ; mov.l #flmcr1,r0 mov.l @r5,r6 ; erase memory block start address -> r6 mov.l #h'020000,r7 cmp/gt r6,r7 bt eraseloop mov.l #flmcr2,r0 ; eraseloop .equ $ mov.l #wdt_tcsr,r1 ; enable wdt mov.w #wdt_9m,r3 ; 9.2 ms cycle mov.w r3,@r1 ; mov.l #wait200u,r3 or.b #esuset,@(r0,gbr) ; set esu ewait_2 subc r2,r3 ; wait 200 s bf ewait_2 ; mov.l #wait5m,r3 or.b #eset,@(r0,gbr) ; set e ewait_3 subc r2,r3 ; wait 5 ms bf ewait_3 ; mov.l #wait10u,r3 and.b #eclear,@(r0,gbr) ; clear e 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 522 of 716 rej09b0398-0500 ewait_4 subc r2,r3 ; wait 10 s bf ewait_4 ; mov.l #wait10u,r3 and.b #esuclear,@(r0,gbr) ; clear esu ewait_5 subc r2,r3 ; wait 10 s bf ewait_5 ; mov.l #wdt_tcsr,r1 ; disable wdt mov.w #h'a55f,r3 mov.w r3,@r1 ; mov.l #wait20u,r3 or.b #evset,@(r0,gbr) ; set ev ewait_6 subc r2,r3 ; wait 20 s bf ewait_6 ; mov.l @r5,r6 ; erase memory block start address -> r6 blockverify_1 .equ $ ; erase-verify mov.l #h'ffffffff,r8 mov.l r8,@r6 ; h'ff dummy write mov.l #wait2u,r3 ewait_7 subc r2,r3 bf ewait_7 ; mov.l @r6+,r1 ; read verify data cmp/eq r8,r1 bf blockverify_ng mov.l @(8,r5),r7 cmp/eq r6,r7 ; check for last address of memory block bf blockverify_1 mov.l #wait5u,r3 and.b #evclear,@(r0,gbr) ; clear ev ewait_8 subc r2,r3 ; wait 5 s bf ewait_8 ; mov.l #ok,r7 ; r7 <- ok (return value) bra flasherase_end ; verify ok 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 523 of 716 rej09b0398-0500 nop ; blockverify_ng .equ $ add.l #1,r9 ; verify ng, n <- n + 1 mov.l #wait5u,r3 and.b #evclear,@(r0,gbr) ; clear ev ewait_9 subc r2,r3 ; wait 5 s bf ewait_9 mov.l #maxerase,r7 ; if n > maxerase then erase ng cmp/eq r7,r9 bf eraseloop mov.l #ng,r7 ; r7 <- ng (return value) flasherase_end .equ $ mov.l #flmcr1,r0 and.b #sweclear,@(r0,gbr) ; clear swe ; rts nop ; ; memory block table memory block start address: ebr value .align 4 flash_blockdata .equ $ eb0 .data.l h'00000000,h'00000100 eb1 .data.l h'00008000,h'00000200 eb2 .data.l h'00010000,h'00000400 eb3 .data.l h'00018000,h'00000800 eb4 .data.l h'00020000,h'00000001 eb5 .data.l h'00028000,h'00000002 eb6 .data.l h'00030000,h'00000004 eb7 .data.l h'00038000,h'00000008 eb8 .data.l h'0003f000,h'00000010 eb9 .data.l h'0003f400,h'00000020 eb10 .data.l h'0003f800,h'00000040 eb11 .data.l h'0003fc00,h'00000080 dummy .data.l h'00040000 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 524 of 716 rej09b0398-0500 18.8 protection there are two kinds of flash memory program/erase protection, hardware protection and software protection. 18.8.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. hardware protection is reset by settings in flash memory control register 1 (flmcr1) and erase block register 1 (ebr1). the flmcr1 and ebr1 settings are retained in the error-protected st ate. (see table 18.8.) table 18.8 hardware protection functions item description program erase fwp pin protection ? when a low level is input to the fwp pin, flmcr1 and ebr1 are initialized, and the program/erase-protected state is entered. yes yes reset/standby protection ? in a reset (including a wdt overflow reset) and in standby mode, flmcr1 and ebr1 are initialized, and the program/erase- protected state is entered. ? in a power-on reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. yes yes 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 525 of 716 rej09b0398-0500 18.8.2 software protection software protection can be implemented by setting the swe bit in flmcr1, erase block register 1 (ebr1) and the rams bit in the ram emulation register (ramer). when software protection is in effect, setting the p or e bit in flash memory control register 1 (flmcr1) does not cause a transition to program mode or erase mode. (see table 18.9.) table 18.9 software protection functions item description program erase swe pin protection ? clearing the swe bit to 0 in flmcr1 sets the program/erase-protected state for all blocks. (execute in on-chip ram or external memory.) yes yes block specification protection ? erase protection can be set for individual blocks by settings in erase block register 1 (ebr1). ? setting ebr1 to h'00 places all blocks in the erase-protected state. ? yes emulation protection ? setting the rams bit to 1 in the ram emulation register (ramer) places all blocks in the program/erase-protected state. yes yes 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 526 of 716 rej09b0398-0500 18.8.3 error protection in error protection, an error is detected when sh7017 runaway occurs during flash memory programming/erasing, or operati on is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. if the sh7017 malfunctions during flash memory programming/erasing, the fler bit is set to 1 in flmcr2 and the error protection state is entere d. the flmcr1 and ebr1 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode. fler bit setting conditions are as follows: 1. when flash memory is read during programming/erasing (including a vector read or instruction fetch) 2. immediately after exception handling (excluding a reset) during programming/erasing 3. when a sleep instruction (including software standby) is executed during programming/erasing 4. when the bus is released during programming/erasing error protection is released only by a power-on reset and in hardware standby mode. figure 18.15 shows the flash memory state transition diagram. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 527 of 716 rej09b0398-0500 rd vf pr er fler = 0 error occurrence res = 0 res = 0 rd vf pr er fler = 0 pro g ram mode erase mode reset or standby (hardware protection) rd vf pr er fler = 1 rd vf pr er fler = 1 error protection mode error protection mode (standby) standby mode flmcr1, ebr1 initialization state flmcr1, ebr1 initialization state standby mode release rd: memory read possible vf: verify-read possible pr: pro g rammin g possible er: erasin g possible rd : memory read not possible vf : verify-read not possible pr : pro g rammin g not possible er : erasin g not possible le g end: res = 0 error occurrence (standby) figure 18.15 flash memory state transitions 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 528 of 716 rej09b0398-0500 18.9 flash memory emulation in ram making a setting in the ram emulation register (ramer) enables part of ram to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in ram in real time. after the ramer setting has been made, accesses cannot be made from the flash memory area or the ram area overlapping flash memory. emulation can be performed in user mode and user program mode. figure 18.16 shows an example of emulation of real-time flash memory programming. start emulation pro g ram end of emulation pro g ram tunin g ok ? yes no set ramer write tunin g data to overlap ram execute application pro g ram clear ramer write to flash memory emulation block figure 18.16 flowchart for flash memory emulation in ram 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 529 of 716 rej09b0398-0500 h'000000 h'01f000 h'01f400 h'01f800 h'01fc00 h'01ffff flash memory eb0 to eb3 this area can be accessed from both the ram area and flash memory area eb7 eb6 eb5 eb4 h'fffff800 h'fffffbff on-chip ram figure 18.17 example of ram overlap operation example in which flash memory block area (eb4) is overlapped 1. set bits rams, ram1, and ram0 in ramer to 1, 0, 1, to overlap part of ram onto the area (eb4) for which real-time programming is required. 2. real-time programming is performed using the overlapping ram. 3. after the program data has been confirmed, the rams bit is cleared, releasing ram overlap. 4. the data written in the overlapping ram is written into the flash memory space (eb4). notes: 1. when the rams bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of ram1 and ram0 (emulation protection). in this state, setting the p or e bit in flash memory control register 1 (flmcr1) will not cause a transition to program mode or erase mode. when actually programming a flash memory area, the rams bit should be cleared to 0. 2. a ram area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in ram is being used. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 530 of 716 rej09b0398-0500 18.10 note on flash memory programming/erasing in the on-board programming modes (user mode and user program mode), nmi input should be disabled to give top priority to the program/erase operations (including ram emulation). 18.11 flash memory programmer mode programs and data can be written and erased in programmer mode as well as in the on-board programming modes. in programmer mode, flash memory read mode, auto-program mode, auto- erase mode, and status read mode are supported. in auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. in programmer mode, set the mode pins to pll 2 mode (see table 18.10) and input a 6 mhz input clock, so that the sh7017 runs at 12 mhz. table 18.10 shows the pin settings for programmer mode. for the pin names in programmer mode, see section 1.3.2, pin arrangement by mode. table 18.10 prom mode pin settings pin names settings mode pins: md3, md2, md1, md0 1101 (pll 2) fwe pin high level input (in auto-program and auto-erase modes) res pin power-on reset circuit xtal, extal, pllv cc , pllcap, pllv ss pins oscillator circuit note: in programmer mode, the fwp pin has its polarity reversed and functions as the fwe (flash write enable) pin. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 531 of 716 rej09b0398-0500 18.11.1 socket adapter pin correspondence diagram connect the socket adapter to the chip as shown in figure 18.19. this will enable conversion to a 32-pin arrangement. the on-chip rom memory map is shown in figure 18.18, and the socket adapter pin correspondence diagram in figure 18.19. h'00000000 addresses in mcu mode addresses in pro g rammer mode h'0001ffff h'00000 h'1ffff on-chip rom space 128 kb figure 18.18 on-chip rom memory map 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 532 of 716 rej09b0398-0500 pin no. 77 13 20 19 44 70 69 68 67 66 64 63 62 4 5 6 7 8 9 10 11 12 43 14 15 16 17 18 42 21, 37, 46, 49, 50, 65, 73, 75, 76, 79, 100, 103 3, 23, 27, 33, 39, 55, 61, 71 78, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 101, 109 26 84 72 74 80 81 82 other than the above pin no. 1 26 2 3 31 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 24 23 25 4 28 29 22 32 16 30 hn28f101p (32 pins) pin name fwe a9 a16 a15 we i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 a0 a1 a2 a3 a4 a5 a6 a7 a8 oe a10 a11 a12 a13 a14 ce v cc v ss a17 pin name fwe a9 a16 a15 we d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 a3 a4 a5 a6 a7 a8 oe a10 a11 a12 a13 a14 ce v ss a17 res xtal extal pllv cc pllcap pllv ss n.c.(open) hd64f7017 (112 pins) socket adapter (conversion to 32-pin arrangement) power-on reset circuit oscillator circuit pll circuit legend: fwe: flash write enable i/o7 to i/o0: data input/output a17 to a0: address input oe : output enable ce : chip enable we : write enable note: use address pin a17 as v ss . v cc figure 18.19 socket adapter pin correspondence table (sh7017: fp-112) 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 533 of 716 rej09b0398-0500 18.11.2 programmer mode operation table 18.11 shows how the different operating modes are set when using programmer mode, and table 18.12 lists the commands used in programme r mode. details of each mode are given below. ? memory read mode memory read mode supports byte reads. ? auto-program mode auto-program mode supports programming of 128 byt es at a time. status polling is used to confirm the end of auto-programming. ? auto-erase mode auto-erase mode supports automatic erasing of the entire flash memory. status polling is used to confirm the end of auto-programming. ? status read mode status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the i/o 6 signal. in status read mode, error information is output if an error occurs. table 18.11 settings for various op erating modes in programmer mode pin names mode fwe ce oe we i/o0 to i/o7 a0 to a17 read h or l l l h data output ain output disable h or l l h h hi-z x command write h or l l h l data input * ain chip disable h or l h x x hi-z x notes: 1. chip disable is not a standby state; internally, it is an operation state. 2. * ain indicates that there is also address input in auto-program mode. 3. for command writes in auto-program and auto-erase modes, input a high level to the fwe pin. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 534 of 716 rej09b0398-0500 table 18.12 programmer mode commands 1st cycle 2nd cycle command name number of cycles mode address data mode address data memory read mode 1 + n write x h'00 read ra dout auto-program mode 129 write x h'40 write wa din auto-erase mode 2 write x h'20 write x h'20 status read mode 2 write x h'71 write x h'71 notes: 1. in auto-program mode. 129 cycles are r equired for command writing by a simultaneous 128-byte write. 2. in memory read mode, the number of cycles depends on the number of address write cycles (n). 18.11.3 memory read mode 1. after completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. when reading memory conten ts, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. in memory read mode, command writes can be performed in the same way as in the command wait state. 3. once memory read mode has been ente red, consecutive reads can be performed. 4. after powering on, memory read mode is entered. table 18.13 ac characteristics in transition to memory read mode conditions: v cc = 5.0 v 10 % , v ss = 0 v, t a = 25c 5c item symbol min max unit notes command write cycle t nxtc 20 s ce hold time t ceh 0 ns ce setup time t ces 0 ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns we rise time t r 30 ns we fall time t f 30 ns 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 535 of 716 rej09b0398-0500 ce oe ce a16 to a0 oe we i/o7 to i/o0 note: data is latched on the rising edge of we . t ceh t wep t f t r t ces t nxtc address stable t ds t dh command write memory read mode figure 18.20 timing waveforms fo r memory read after memory write table 18.14 ac characteristics in transition from memory read mode to another mode conditions: v cc = 5.0 v 10 % , v ss = 0 v, t a = 25c 5c item symbol min max unit notes command write cycle t nxtc 20 s ce hold time t ceh 0 ns ce setup time t ces 0 ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns we rise time t r 30 ns we fall time t f 30 ns 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 536 of 716 rej09b0398-0500 ce oe ce a16 to a0 oe we i/o7 to i/o0 note: do not enable we and oe at the same time. t ceh t wep t f t r t ces t nxtc address stable t ds t dh other mode command write memory read mode figure 18.21 timing waveforms in transition from memory read mode to another mode table 18.15 ac characteristics in memory read mode conditions: v cc = 5.0 v 10 % , v ss = 0 v, t a = 25c 5c item symbol min max unit notes access time t acc 20 s ce output delay time t ce 150 ns oe output delay time t oe 150 ns output disable delay time t df 100 ns data output hold time t oh 5 ns 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 537 of 716 rej09b0398-0500 ce a16 to a0 oe we i/o7 to i/o0 v il v il v ih t acc t acc t oh t oh address stable address stable figure 18.22 ce and oe enable state read timing waveforms ce a16 to a0 oe we i/o7 to i/o0 v ih t acc t ce t oe t oe t ce t acc t oh t df t df t oh address stable address stable figure 18.23 ce and oe clock system read timing waveforms 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 538 of 716 rej09b0398-0500 18.11.4 auto-program mode 1. in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. 2. a 128-byte data transfer is necessary even when programming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. the lower 8 bits of the transfer address must be h'00, h'80. if a value other than an effective address is input, processing will switch to a memo ry write operation but a write error will be flagged. 4. memory address transfer is performed in the second cycle (figure 18.24). do not perform transfer after the third cycle. 5. do not perform a command write during a programming operation. 6. perform one auto-program operation for a 1 28-byte block for each address. two or more additional programming operations cannot be pe rformed on a previously programmed address block. 7. confirm normal end of auto-programming by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7status polling uses the auto-program operation end identification pin). 8. status polling i/o6 and i/o7 pin information is re tained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 539 of 716 rej09b0398-0500 table 18.16 ac characteristics in auto-program mode conditions: v cc = 5.0 v 10 % , v ss = 0 v, t a = 25c 5c item symbol min max unit notes command write cycle t nxtc 20 s ce hold time t ceh 0 ns ce setup time t ces 0 ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns status polling start time t wsts 1 ms status polling access time t spa 150 ns address setup time t as 0 ns address hold time t ah 60 ns memory write time t write 1 3000 ms write setup time t pns 100 ns write end setup time t pnh 100 ns we rise time t r 30 ns we fall time t f 30 ns ce a16 to a0 fwe oe we i/o7 i/o6 i/o5 to i/o0 t pns t wep t ds t dh t f t r t as t ah t wsts t write t spa t ces t ceh t nxtc t nxtc t pnh address stable h'40 h'00 data transfer 1 to 128 byte write operation complete verify signal write normal complete verify signal figure 18.24 auto-program mode timing waveforms 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 540 of 716 rej09b0398-0500 18.11.5 auto-erase mode 1. auto-erase mode supports only entire memory erasing. 2. do not perform a command write during auto-erasing. 3. confirm normal end of auto-erasing by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-erase operation end identification pin). 4. status polling i/o6 and i/o7 pin information is re tained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . table 18.17 ac characteristics in auto-erase mode conditions: v cc = 5.0 v 10 % , v ss = 0 v, t a = 25c 5c item symbol min max unit notes command write cycle t nxtc 20 s ce hold time t ceh 0 ns ce setup time t ces 0 ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns status polling start time t ests 1 ms status polling access time t spa 150 ns memory erase time t erase 100 40000 ms erase setup time t ens 100 ns erase end setup time t enh 100 ns we rise time t r 30 ns we fall time t f 30 ns 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 541 of 716 rej09b0398-0500 ce a16 to a0 fwe oe we i/o7 i/o6 i/o5 to i/o0 t ens t wep t ds t dh t f t r t ests t erase t spa t ces t ceh t nxtc t nxtc t enh h'20 h'20 h'00 erase complete verify signal erase normal complete verify signal figure 18.25 auto-erase mode timing waveforms 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 542 of 716 rej09b0398-0500 18.11.6 status read mode 1. status read mode is provided to specify the kind of abnormal end. use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. the return code is retained until a command write other than a status read mode command write is executed. table 18.18 ac characteristics in status read mode conditions: v cc = 5.0 v 10 % , v ss = 0 v, t a = 25c 5c item symbol min max unit notes read time after command write t strd 20 s ce hold time t ceh 0 ns ce setup time t ces 0 ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns oe output delay time t oe 150 ns disable delay time t df 100 ns ce output delay time t ce 150 ns we rise time t r 30 ns we fall time t f 30 ns ce a16 to a0 oe we i/o7 to i/o0 t wep t f t r t oe t df t ds t ds t dh t dh t ces t ceh t ce t ceh t nxtc t nxtc t nxtc t ces h'71 t wep t f t r h'71 note: i/o2 and i/o3 are undefined. figure 18.26 status read mode timing waveforms 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 543 of 716 rej09b0398-0500 table 18.19 status read mode return commands pin name i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 attribute normal end identification command error programming error erase error ? ? programming or erase count exceeded effective address error initial value 0 0 0 0 0 0 0 0 indications normal end: 0 abnormal end: 1 command error: 1 otherwise: 0 programming error: 1 otherwise: 0 erasing error: 1 otherwise: 0 ? ? count exceeded: 1 otherwise: 0 effective address error: 1 otherwise: 0 note: i/o2 and i/o3 are undefined at present. 18.11.7 status polling 1. i/o7 status polling is a fl ag that indicates the operating st atus in auto-program/auto-erase mode. 2. i/o6 status polling is a flag that indicates a normal or abnorma l end in auto-program/auto-erase mode. table 18.20 status polling output truth table pin name during internal operation abnormal end ? normal end i/o7 0 1 0 1 i/o6 0 0 1 1 i/o0 to i/o5 0 0 0 0 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 544 of 716 rej09b0398-0500 18.11.8 programmer mode transition time commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. after the programmer mode setup time, a transition is made to memory read mode. table 18.21 stipulated transition times to command wait state item symbol min max unit notes standby release (oscillation stabilization time) t osc1 10 ms programmer mode setup time t bmv 10 ms v cc hold time t dwn 0 ms t osc1 t bmv t dwn v cc res fwe memory read mode command wait state auto-program mode auto-erase mode command wait state normal/abnormal complete verify note: for the level of fwe input pin, set v il when using other than the auto-program mode and auto-erase mode. figure 18.27 oscillation stabilization time, boot program transfer time, and power-down sequence 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 545 of 716 rej09b0398-0500 18.11.9 notes on memory programming 1. when programming addresses which have previously been programmed, carry out auto- erasing before auto-programming. 2. when performing programming using prom mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. notes: 1. the flash memory is initially in the erased state when the device is shipped by renesas technology. for other chips for which the erasure history is unknown, it is recommended that auto-erasing be executed to check and supplement the initialization (erase) level. 2. auto-programming should be performe d once only on the same address block. additional programming cannot be performe d on previously programmed address blocks. 18. 128 kb flash memory (f-ztat) rev.5.00 sep. 27, 2007 page 546 of 716 rej09b0398-0500 19. mask rom rev.5.00 sep. 27, 2007 page 547 of 716 rej09b0398-0500 section 19 mask rom 19.1 overview this lsi is available with 64 kbytes or 128 kbytes of on-chip rom. the on-chip rom is connected to the cpu, direct memory access cont roller (dmac) through a 32-bit data bus (figures 19.1 and 19.2). the cpu and dmac can access the on-chip rom in 8, 16 and 32-bit widths. data in the on-chip rom can always be accessed in one cycle. internal data bus (32-bit) h'00000000 h'00000004 h'00000001 h'00000005 h'00000002 h'00000006 h'00000003 h'00000007 h'0000fffc h'0000fffd h'0000fffe h'0000ffff on-chip rom figure 19.1 mask rom block diagram (64 kbyte version) 19. mask rom rev.5.00 sep. 27, 2007 page 548 of 716 rej09b0398-0500 internal data bus (32-bit) h'00000000 h'00000004 h'00000001 h'00000005 h'00000002 h'00000006 h'00000003 h'00000007 h'0001fffc h'0001fffd h'0001fffe h'0001ffff on-chip rom figure 19.2 mask rom block diagram (128 kbyte version) the operating mode determines whether the on-chi p rom is valid or not. the operating mode is selected using mode-setting pins md3 to md0 as shown in table 19.1. if you are using the on-chip rom, select mode 2 or mode 3; if you are not, select mode 0 or 1. the on-chip rom is allocated to addresses h'00000000 to h' 0000ffff of memory area 0 for the 64 kbyte version and h'00000000 to h'0001 ffff of memory ar ea 0 for the 128 kbyte version. table 19.1 operation modes and rom mode setting pin operation mode md3 md2 md1 md0 area 0 mode 0 (mcu mode 0) * * 0 0 on-chip rom invalid, external 8-bit space mode 1 (mcu mode 1) * * 0 1 on-chip rom invalid, external 16-bit space mode 2 (mcu mode 2) * * 1 0 on-chip rom valid, external space (bus width set with bus state controller) mode 3 (mcu mode 3) * * 1 1 on-chip rom valid, single-chip mode legend: 0: low 1: high note: * refer to section 3, operating modes. 20. ram rev.5.00 sep. 27, 2007 page 549 of 716 rej09b0398-0500 section 20 ram 20.1 overview the sh7014 and sh7016 have 3 kbytes of on-chip ram, and the sh7017 has 4 kbytes. the on- chip ram is linked to the cpu and direct memo ry access controller (dmac) with a 32-bit data bus (figure 20.1). the cpu can access data in th e on-chip ram in 8, 16, or 32 bit widths. the dmac can access 8 or 16 bit widths. on-chip ram data can always be accessed in one state, making the ram ideal for use as a program area, stack area, or data area, which require high- speed access. the contents of the on-chip ram ar e held in both the sleep and standby modes. memory area 0 addresses h'fffff000 to h'fffffbff (sh7014, sh7016) or h'fffff000 to h'ffffffff (sh7017) are allocated to the on-chip ram. the on-chip ram is also used as cache memory. when the cache is used, 1 kbyte of on-chip ram is available in the sh7014 and sh7016, and 2 kbytes in the sh7017. see section 7, cache memory, for details. h'fffff000 h'fffff004 h'fffff001 h'fffff005 h'fffff002 h'fffff006 h'fffff003 h'fffff007 h'fffffbfc h'fffffbfd h'fffffbfe h'fffffbff on-chip ram h'fffffffc h'fffffffd h'fffffffe h'ffffffff internal data bus (32-bit) note: operation is not g uaranteed if addresses h'fffffc00 to h'ffffffff are accessed in the sh7014 or sh7016. figure 20.1 block diagram of ram 20. ram rev.5.00 sep. 27, 2007 page 550 of 716 rej09b0398-0500 21. power-down state rev.5.00 sep. 27, 2007 page 551 of 716 rej09b0398-0500 section 21 power-down state 21.1 overview in the power-down state, the cpu functions are ha lted. this enables a great reduction in power consumption. 21.1.1 power-down states the power-down state is effected by the following two modes: ? sleep mode ? standby mode table 21.1 describes the transition conditions for entering the modes from the program execution state as well as the cpu and peripheral function status in each mode and the procedures for canceling each mode. 21. power-down state rev.5.00 sep. 27, 2007 page 552 of 716 rej09b0398-0500 table 21.1 power-down state conditions state mode entering procedure clock cpu on-chip peripheral modules cpu registers ram i/o ports canceling procedure sleep execute sleep instruction with sby bit set to 0 in sbycr run halt run held held held ? interrupt ? dmac address error ? power-on reset stand- by execute sleep instruction with sby bit set to 1 in sbycr halt halt halt * 1 held held held or high impe- dance * 2 ? nmi interrupt ? power-on reset legend: sbycr: standby control register sby: standby bit notes: 1. some bits within on-chip peripheral module registers are initialized by the standby mode; some are not. refer to table 21.3, register states in the standby mode, in section 21.4.1, transition to standby mode. also refer to the register descriptions for each peripheral module. 2. the status of the i/o port in standby mode is set by the port high impedance bit (hiz) of the sbycr. refer to section 21.2, standby control register. for pin status other than for the i/o port, refer to appendix c, pin status. 21.1.2 related register table 21.2 shows the register used for power-down state control. table 21.2 related register name abbreviation r/w initial value address access size standby control register sbycr r/w h'1f h'ffff8614 8, 16, 32 21. power-down state rev.5.00 sep. 27, 2007 page 553 of 716 rej09b0398-0500 21.2 standby control register (sbycr) the standby control register (sbycr) is a read/wr ite 8-bit register that sets the transition to standby mode, and the port status in standby mode. the sbycr is initialized to h'1f when reset. bit: 7 6 5 4 3 2 1 0 sby hiz ? ? ? ? ? ? initial value: 0 0 0 1 1 1 1 1 r/w: r/w r/w r r r r r r bit 7 ? standby (sby): specifies transition to the standby mode. the sby bit cannot be set to 1 while the watchdog timer is running (when the timer enable bit (tme) of the wdt timer control/status register (tcsr) is set to 1). to enter the standby mode, always halt the wdt by 0 clearing the tme bit, then set the sby bit. bit 7 sby description 0 executing sleep instruction puts the lsi into sleep mode (initial value) 1 executing sleep instruction puts the lsi into standby mode bit 6 ? port high impedance (hiz): in the standby mode, this bit selects whether to set the i/o port pin to high impedance or hold the pin status. the hiz bit cannot be set to 1 when the tme bit of the wdt timer control/status register (tcsr) is set to 1. when making the i/o port pin status high impedance, always clear the tme bit to 0 before setting the hiz bit. bit 6 hiz description 0 holds pin status while in standby mode (initial value) 1 keeps pin at high impedance while in standby mode bits 5 to 0 ? reserved: bit 5 always reads as 0. always write 0 to bit 5. bits 4 to 0 always read as 1. always write 1 to these bits. 21. power-down state rev.5.00 sep. 27, 2007 page 554 of 716 rej09b0398-0500 21.3 sleep mode 21.3.1 transition to sleep mode executing the sleep instru ction when the sby bit of sbycr is 0 causes a transition from the program execution state to the sl eep mode. although the cpu halts immediately after executing the sleep instruction, the cont ents of its internal register s remain unchanged. the on-chip peripheral modules continue to run during the sleep mode. 21.3.2 canceling sleep mode sleep mode is canceled by an interrupt, dmac address error, or power-on reset. cancellation by an interrupt: when an interrupt occurs, the sl eep mode is canceled and interrupt exception processing is executed. the sleep mode is not canceled if the interrupt cannot be accepted because its priority level is equal to or less than the mask level set in the cpu's status register (sr) or if an interrupt by an on-chip peripheral module is disabled at the peripheral module. cancellation by a dmac address error: if a dmac address error occurs, the sleep mode is canceled and dmac address error exception processing is executed. cancellation by a power-on reset: a power-on reset resulting from setting the res pin to low level cancels the sleep mode. 21.4 standby mode 21.4.1 transition to standby mode to enter the standby mode, set the sby bit to 1 in sbycr, then execute the sleep instruction. the lsi moves from the program execution state to the standby mode. in the standby mode, power consumption is greatly reduced by halting not only the cpu, but the clock and on-chip peripheral modules as well. cpu register contents and on-chip ram data are held as long as the prescribed voltages are applied. the register contents of some on-chip peripheral modules are initialized, but some are not (table 21.3). the i/o port status can be selected as held or high impedance by the port high impedance bit (hiz) of the sbycr. for pin status other than for the i/o port, refer to appendix b, pin status. 21. power-down state rev.5.00 sep. 27, 2007 page 555 of 716 rej09b0398-0500 table 21.3 register states in the standby mode module registers initialized registers that retain data registers with undefined contents interrupt controller (intc) ? all registers ? cache memory (cac) ? all registers ? bus state controller (bsc) ? all registers ? direct memory access controller (dmac) ? dma channel control registers 0, 1 (chcr0, chcr1) ? dma operation register (dmaor) ? ? dma source address registers 0, 1 (sar0, sar1) ? dma destination address registers 0, 1 (dar0, dar1) ? dma transfer count registers 0, 1 (dmatcr0, dmatcr1) multifunction timer pulse unit (mtu) mtu associated registers ? ? watchdog timer (wdt) ? bits 7 to 5 (ovf, wt/ it , tme) of the timer control status register (tcsr) ? reset control/status register (rstcsr) ? bits 2 to 0 (cks2 to cks0) of the tcsr ? timer counter (tcnt) ? serial communication interface (sci) ? receive data register (rdr) ? transmit data register (tdr) ? serial mode register (smr) ? serial control register (scr) ? serial status register (ssr) ? bit rate register (bbr) ? ? a/d converter (a/d) all registers ? ? compare match timer (cmt) all registers ? ? pin function controller (pfc) ? all registers ? 21. power-down state rev.5.00 sep. 27, 2007 page 556 of 716 rej09b0398-0500 module registers initialized registers that retain data registers with undefined contents i/o port (i/o) ? all registers ? power-down state related ? standby control register (sbycr) ? 21.4.2 canceling the standby mode the standby mode is canceled by an nmi interrupt or a power-on reset. cancellation by an nmi: clock oscillation starts when a rising edge or falling edge (selected by the nmi edge select bit (nmie) of the interrupt c ontrol register (icr) of the intc) is detected in the nmi signal. this clock is supplied only to the watchdog timer (wdt). a wdt overflow occurs if the time established by the clock select bits (cks2 to cks0) in the tcsr of the wdt elapses before transition to the standby mode. the occurrence of this overflow is used to indicate that the clock has stabilized, so the clock is supplied to the entire chip, the standby mode is canceled, and nmi exception processing begins. when canceling standby mode with nmi interrupts, set the cks2 to cks0 bits so that the wdt overflow period is longer than the oscillation stabilization time. when canceling standby mode with an nmi pin set for falling edge, be sure that the nmi pin level upon entering standby (when the clock is halted) is high level, and that the nmi pin level upon returning from standby (when the clock starts after oscillation stabilization) is low level. when canceling standby mode with an nmi pin set for rising edge, be sure that the nmi pin level upon entering standby (when the clock is halted) is low level, and that the nmi pin level upon returning from standby (when the clock starts after oscillation stabilization) is high level. cancellation by a power-on reset: a power-on reset caused by setting the res pin to low level cancels the standby mode. 21. power-down state rev.5.00 sep. 27, 2007 page 557 of 716 rej09b0398-0500 21.4.3 standby mode application example this example describes a transition to standby m ode on the falling edge of an nmi signal, and a cancellation on the rising edge of the nmi signal. the timing is shown in figure 21.1. when the nmi pin is changed from high to low level while the nmi edge select bit (nmie) of the icr is set to 0 (falling edge detection), the nmi inte rrupt is accepted. when the nmie bit is set to 1 (rising edge detection) by an nmi exception service routine, the standby bit (sby) of the sbycr is set to 1, and a sleep instruction is executed, standby mode is entered. thereafter, standby mode is canceled when the nmi pin is changed from low to high level. oscillator ck nmi nmie sby nmi exception processing exception service routine sby = 1 sleep instruction standby mode oscillation start time wdt time set nmi exception processing oscillation settling time figure 21.1 standby mode nmi timing (application example) 21. power-down state rev.5.00 sep. 27, 2007 page 558 of 716 rej09b0398-0500 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 559 of 716 rej09b0398-0500 section 22 electrical ch aracteristics (5 v 28.7 mhz) 22.1 absolute maximum ratings table 22.1 shows the absolute maximum ratings. table 22.1 absolute maximum ratings item symbol rating unit power supply voltage v cc ? 0.3 to +7.0 v input voltage (other than a/d ports) v in ? 0.3 to v cc +0.3 v input voltage (a/d ports) v in ? 0.3 to av cc +0.3 v analog supply voltage av cc ? 0.3 to +7.0 v analog input voltage v an ? 0.3 to av cc +0.3 v operating temperature t opr ? 20 to +75 c programming temperature (f-ztat version only) t we ? 20 to +75 c storage temperature tstg ? 55 to +125 c note: operating the lsi in excess of the absolute maximum ratings may result in permanent damage. 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 560 of 716 rej09b0398-0500 22.2 dc characteristics table 22.2 dc characteristics conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc 10 % , v ss = av ss = 0 v, ta = ? 20 to +75 c item pin symbol min typ max unit measurement conditions input high- level voltage res , nmi, md3 to md0, fwp, pa2, pa5, pa6 to pa9, pe0 to pe15 v ih v cc ? 0.7 ? v cc +0.3 v ? extal v cc 0.7 ? v cc +0.3 v ? a/d port 2.2 ? av cc +0.3 v ? other input pins 2.2 ? v cc +0.3 v ? input low- level voltage res , nmi, md3 to md0, pa2, pa5, pa6 to pa9, pe0 to pe15 v il ? 0.3 ? 0.5 v ? other input pins ? 0.3 ? 0.8 v ? pa2, pa5, pa6 to pa9 vt + ? vt ? 0.4 ? ? v vt + v cc ? 0.7 (max) schmitt trigger input voltage pe0 to pe15 vt ? 0.5 (min) input leakage current res , nmi, md3 to md0, pa2, pa5, pa6 to pa9, pe0 to pe15 | iin | ? ? 1.0 a vin = 0.5 to v cc ? 0.5 v a/d port ? ? 1.0 a vin = 0.5 to av cc ? 0.5 v other input pins ? ? 1.0 a vin = 0.5 to v cc ? 0.5 v three-state leak current (while off) a21 to a0, d15 to d0, cs3 to cs0 , rdwr, ras , casx , wrx , rd , ports a, b, e | i tsi | ? ? 1.0 a vin = 0.5 to v cc ? 0.5 v 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 561 of 716 rej09b0398-0500 item pin symbol min typ max unit measurement conditions all output pins v oh v cc ? 0.5 ? ? v i oh = ? 200 a output high- level voltage 3.5 ? ? v i oh = ? 1 ma output low- level voltage all output pins v ol ? ? 0.4 v i ol = 1.6 ma res cin ? ? 80 pf nmi ? ? 50 pf vin = 0 v, f = 1 mhz, ta = 25c input capacitance all other input pins ? ? 20 pf ordinary operation i cc ? 130 180 ma f = 28 mhz sleep ? 100 150 ma f = 28 mhz current consumption (sh7014) standby ? 0.01 5 a ta 50c ? ? 20 a ta > 50c ordinary operation i cc ? 140 180 ma f = 28 mhz sleep ? 110 150 ma f = 28 mhz current consumption (sh7016, sh7017) standby ? 0.01 5 a ta 50c ? ? 20 a ta > 50c analog supply current (sh7014) ai cc ? 13 22 ma analog supply current (sh7016, sh7017) ai cc ? 5 10 ma ram standby voltage v ram 2.0 ? ? v notes: 1. when the a/d converter is not used (including during standby), do not release the av cc and av ss pins. connect the av cc pin to v cc and the av ss pin to v ss . 2. the current consumption is measured when v ih min = v cc ? 0.5 v, v il max = 0.5 v, with all output pins unloaded. 3. the f-ztat and mask versions have the same functions, and the electrical characteristics of both are within specificat ion, but characteristic-related performance values, operating margins, noise margins, noise emission, etc., are different. caution is therefore required in carrying out system design, and when switching between f-ztat and mask versions. 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 562 of 716 rej09b0398-0500 table 22.3 permitted output current values conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc 10 % , v ss = av ss = 0 v, ta = ? 20 to +75 c item symbol min typ max unit output low-level permissible current (per pin) i ol ? ? 2.0 ma output low-level permissible current (total) i ol ? ? 80 ma output high-level permissible current (per pin) ? i oh ? ? 2.0 ma output high-level permissible current (total) ( ? i oh ) ? ? 25 ma note: to assure lsi reliability, do not exceed the output values listed in this table. 22.3 ac characteristics 22.3.1 clock timing table 22.4 clock timing conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc 10 % , v ss = av ss = 0 v, ta = ? 20 to +75 c item symbol min max unit figures operating frequency f op 4 28.7 mhz 22.1 clock cycle time t cyc 34.8 250 ns clock low-level pulse width t cl 10 ? ns clock high-level pulse width t ch 10 ? ns clock rise time t cr ? 5 ns clock fall time t cf ? 5 ns extal clock input frequency f ex 4 10 mhz 22.2 extal clock input cycle time t excyc 100 250 ns extal clock low-level input pulse width t exl 40 ? ns extal clock high-level input pulse width t exh 40 ? ns extal clock input rise time t exr ? 5 ns extal clock input fall time t exf ? 5 ns reset oscillation settling time t osc1 10 ? ms 22.3 standby return clock settling time t osc2 10 ? ms 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 563 of 716 rej09b0398-0500 t cl t cyc t ch ck 1/2 v cc t cf t cr 1/2 v cc figure 22.1 system clock timing t exl t exh extal 1/2 v cc t exf t exr 1/2 v cc t excyc v ih v ih v il v il v ih figure 22.2 extal clock input timing ck v cc min t osc1 v cc t osc2 res figure 22.3 oscillation settling time 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 564 of 716 rej09b0398-0500 22.3.2 control signal timing table 22.5 control signal timing conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc 10 % , v ss = av ss = 0 v, ta = ? 20 to +75 c item symbol min max unit figure res rise/fall t resr , t resf ? 200 ns 22.4 res pulse width t resw 20 ? t cyc nmi rise/fall t nmir , t nmif ? 200 ns res setup time * t ress 35 ? ns nmi setup time * t nmis 35 ? ns irq7 , irq6 , irq3 to irq0 setup time (edge detection) * t irqes 35 ? ns 22.4, 22.5 irq7 , irq6 , irq3 to irq0 setup time (level detection) * t irqls 35 ? ns nmi hold time t nmih 35 ? ns 22.5 irq7 , irq6 , irq3 to irq0 hold time t irqeh 35 ? ns note: * the res , nmi, irq7 , irq6 , and irq3 to irq0 signals are asynchronous inputs, but when the setup times shown here are provided, the signals are considered to have produced changes at clock rise (for res ) or clock fall (for nmi, irq7 , irq6 , and irq3 to irq0 ). if the setup times are not provided, recognition is delayed until the next clock rise or fall. 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 565 of 716 rej09b0398-0500 t ress t resr t resf v ih v ih v il v il t resw t ress ck res figure 22.4 reset input timing t nmih v ih ck t nmis v il v ih v il t irqeh t irqes t irqls nmi irq edge irq level figure 22.5 interrupt signal input timing 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 566 of 716 rej09b0398-0500 22.3.3 bus timing table 22.6 bus timing conditions: v cc = 5.0 v 10 % , av cc = v cc 10 % , av cc = 5.0 v 10 % , v ss = av ss = 0 v, ta = ? 20 to +75 c item symbol min max unit figure address delay time t ad 2 * 3 18 ns 22.6, 22.7, 22.9 to 22.14, 22.17 cs delay time 1 t csd1 2 * 3 21 ns 22.6, 22.7, 22.17 cs delay time 2 t csd2 2 * 3 21 ns read strobe delay time 1 t rsd1 2 * 3 18 ns read strobe delay time 2 t rsd2 2 * 3 18 ns read data setup time t rds * 4 15 ? ns 22.6, 22.7, 22.9 to 22.14, 22.17 read data hold time t rdh 0 ? ns write strobe delay time 1 t wsd1 2 * 3 18 ns write strobe delay time 2 t wsd2 2 * 3 18 ns write data delay time t wdd ? 35 ns write data hold time t wdh 0 10 * 2 ns wait setup time t wts 15 ? ns wait hold time t wth 0 ? ns 22.8, 22.13, 22.17 ras delay time 1 t rasd1 2 * 3 18 ns 22.9 to 22.16 ras delay time 2 t rasd2 2 * 3 18 ns cas delay time 1 t casd1 2 * 3 18 ns cas delay time 2 t casd2 2 * 3 18 ns read data access time t acc * 1 t cyc (n + 2) ? 40 ? ns 22.6, 22.7 access time from read strobe t oe * 1 t cyc (n + 1.5) ? 40 ? ns access time from column address t aa * 1 t cyc (n + 2) ? 40 ? ns 22.9 to 22.14 access time from ras t rac * 1 t cyc (n + rcd + 2.5) ? 40 ? ns access time from cas t cac * 1 t cyc (n + 1) ? 40 ? ns row address hold time t rah t cyc (rcd + 0.5) ? 15 ? ns row address setup time t asr * 5 t cyc 0.5 ? 17.5 ? ns data input setup time t ds t cyc (m + 0.5) ? 25 ? ns data input hold time t dh 20 ? ns 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 567 of 716 rej09b0398-0500 notes: n is the number of waits. m is 0 when the number of dram write cycle waits is 0, and 1 otherwise. rcd is the set value of the rcd bit in dcr. 1. if the access time is satisfied, t rds need not be satisfied. 2. t wdh (max) is a reference value. 3. the delay time min values are reference values (typ). 4. t rds is a reference value. 5. at 28.7 mhz, t asr = 0 ns (min) table 22.7 bus timing conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc 10 % , v ss = av ss = 0 v, ta = ? 20 to +75 c item symbol min max unit figure write address setup time t as 0 ? ns 22.6 to 22.7 write address hold time t wr 5 ? ns write data hold time t wrh 0 ? ns read/write strobe delay time 1 t rwd1 2 * 18 ns 22.9 to 22.14 read/write strobe delay time 2 t rwd2 2 * 18 ns high-speed page mode cas precharge time t cp t cyc ? 25 ? ns 22.14 ras precharge time t rp t cyc (tpc + 1.5) ? 15 ? ns 22.9 to 22.14 cas setup time t csr 10 ? ns 22.15, 22.16 ah delay time 1 t ahd1 2 * 18 ns 22.17 ah delay time 2 t ahd2 2 * 18 ns multiplex address delay time t mad 2 * 18 ns multiplex address hold time t mah 0 ? ns dack delay time t dackd1 2 * 21 ns 22.6, 22.7, 22.9 to 22.14, 22.17 notes: tpc is the set value of the tpc bit in dcr. * the delay time min values are reference values (typ).) 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 568 of 716 rej09b0398-0500 ck t rsd1 a21 to a0 t1 t2 t oe t rsd2 t csd2 t csd1 t ad t rdh t rds t acc t wsd1 t wsd2 t wdd t wdh t dackd1 t dackd1 d15 to d0 (durin g read) note: t rdh is specified from the first ne g ate timin g for a21 to a0, csn , and rd . csn rd (durin g read) wrx (durin g write) d15 to d0 (durin g write) dackn t wrh t wr t as figure 22.6 basic cycle (no waits) 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 569 of 716 rej09b0398-0500 ck t rsd1 a21 to a0 t1 tw t oe t rsd2 t csd2 t csd1 t ad t rdh t rds t acc t wsd1 t as t wsd2 t wr t wdd t wdh t dackd1 t dackd1 d15 to d0 (durin g read) t2 csn rd (durin g read) wrx (durin g write) d15 to d0 (durin g write) dackn note: t rdh is specified from the first ne g ate timin g for a21 to a0, csn , and rd . t wrh figure 22.7 basic cycle (software waits) 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 570 of 716 rej09b0398-0500 ck a21 to a0 t1 tw d15 to d0 (durin g read) t2 tw t wts d15 to d0 (durin g write) two t wth t wts t wth csn rd (durin g read) wrx (durin g write) wait dackn figure 22.8 basic cycle (2 software waits + wait due to wait signal) 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 571 of 716 rej09b0398-0500 ck t rasd1 a21 to a0 tp tr t cac t asr tc2 t ad tc1 t ad t rp t casd1 t rasd2 t casd2 t aa t rac t rds t rdh t casd1 t casd2 t rwd1 t rwd2 t wdh t ds t dh t wdd t dackd1 t dackd1 t rsd1 t rsd2 t wsd1 t wsd2 ras casx (durin g read) rdwr (durin g read) d15 to d0 (durin g read) casx (durin g write) rdwr (durin g write) d15 to d0 (durin g write) dackn rd (durin g read) wrx (durin g write) row address column address t rah note: t rdh is specified from the first ne g ate timin g for a21 to a0, ras , and cas . figure 22.9 dram cycle (normal mode, no waits) 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 572 of 716 rej09b0398-0500 ck t rasd1 a21 to a0 tp tr t cac t asr d15 to d0 (durin g read) tc2 t ad tc1 t ad t rp t casd1 t aa t rac t rds t rdh t casd2 t rwd1 t rwd2 t wdh t ds t dh t wdd t dackd1 t rsd1 t rsd2 t wsd1 t wsd2 d15 to d0 (durin g write) tcw1 ras casx (durin g read) rdwr (durin g read) casx (durin g write) rdwr (durin g write) dackn rd (durin g read) wrx (durin g write) t dackd1 t casd1 t casd2 t rasd2 t rah column address note: t rdh is specified from the first ne g ate timin g for a21 to a0, ras , and cas . row address figure 22.10 dram cycle (normal mode, 1 wait, tpc = 0, rcd = 0) 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 573 of 716 rej09b0398-0500 ck t rasd1 a21 to a0 tp tpw t cac t rah t asr d15 to d0 (durin g read) tc2 t ad tc1 t ad t rp t casd1 t rasd2 t casd2 t aa t rac t rdh t casd1 t casd2 t rwd1 t rwd2 t wdh t ds t dh t wdd t dackd1 t dackd1 t rsd1 t rsd2 t wsd1 t wsd2 d15 to d0 (durin g write) tcw1 tcw2 tr trw ras casx (durin g read) rdwr (durin g read) casx (durin g write) rdwr (durin g write) dackn rd (durin g read) wrx (durin g write) t rds row address column address note: t rdh is specified from the first ne g ate timin g for a21 to a0, ras , and cas . figure 22.11 dram cycle (normal mode, 2 waits, tpc = 1, rcd = 1) 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 574 of 716 rej09b0398-0500 ck t rasd1 a21 to a0 tp tpw t cac t rah t asr d15 to d0 (durin g read) tc2 t ad tc1 t ad t rp t casd1 t aa t rac t rdh t casd1 t casd2 t rwd1 t rwd2 t ds t dh t wdd t dackd1 t dackd1 t rsd1 t rsd2 t wsd1 t wsd2 d15 to d0 (durin g write) tcw1 tcw2 tr trw tcw3 ras casx (durin g read) rdwr (durin g read) casx (durin g write) rdwr (durin g write) dackn rd (durin g read) wrx (durin g write) row address t rasd2 t casd2 t rds t wdh column address note: t rdh is specified from the first ne g ate timin g for a21 to a0, ras , and cas . figure 22.12 dram cycle (normal mode, 3 waits, tpc = 1, rcd = 1) 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 575 of 716 rej09b0398-0500 ck a21 to a0 tp t cac t asr d15 to d0 (durin g read) tc2 tc1 t ad t rp t casd1 t aa t rac t rdh t casd1 t casd2 t rwd1 t rwd2 t wdh t ds t dh t wdd t dackd1 t dackd1 t rsd1 t rsd2 t wsd1 t wsd2 d15 to d0 (durin g write) tcw1 tcw2 tr tcwo t wts t wth ras casx (durin g read) rdwr (durin g read) casx (durin g write) rdwr (durin g write) wait dackn rd (durin g read) wrx (durin g write) t ad row address column address t rasd1 t rah t rds t wth t wts note: t rdh is specified from the first ne g ate timin g for a21 to a0, ras , and cas . t rasd2 t casd2 figure 22.13 dram cycle (normal mode, 2 waits + wait due to wait signal) 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 576 of 716 rej09b0398-0500 ck a21 to a0 tp t asr d15 to d0 (durin g read) tc2 tc1 t ad t rp t rasd2 t casd2 t aa t rac t rdh t rwd1 t rwd2 t ds t dh t dackd1 t dackd1 t rsd1 d15 to d0 (durin g write) tc2 tr tc1 t ad t aa t casd2 t cp t ds t dh t wdh t rsd2 t rsd2 t rsd1 t wsd1 t wsd2 t wsd2 t wsd1 t cp t rwd1 ras casx (durin g read) rdwr (durin g read) casx (durin g write) rdwr (durin g write) dackn rd (durin g read) wrx (durin g write) row address column address column address t rasd1 t rah t casd1 t casd2 t casd1 t cac t rds t cac t rds t rdh t rwd2 t casd1 t casd2 t casd1 t wdd t wdd t wdh t dackd1 note: t rdh is specified from the first ne g ate timin g for a21 to a0, ras , and cas . figure 22.14 dram cycle (high-speed page mode) 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 577 of 716 rej09b0398-0500 ck trp trr2 t rasd1 trc trr1 t casd2 trc t rasd2 t casd2 t csr ras casx rdwr t casd1 figure 22.15 cas before ras refresh (tras1 = 0, tras0 = 0) ck trp trr2 t rasd1 trc trr1 t casd2 trcc t rasd2 t casd2 t csr t casd1 ras casx rdwr figure 22.16 self refresh 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 578 of 716 rej09b0398-0500 ck a21 to a0 ta1 ta2 d15 to d0 (durin g read) t2 t1 t ad t csd2 t rdh t rsd1 t rsd2 t dackd1 t dackd1 d15 to d0 (durin g write) tw two ta3 ta4 t wts t wts t wth t mad t wdh t mad t ahd2 t mah t mah t wdd t wsd1 t wsd2 cs3 ah rd (durin g read) wrx (durin g write) wait dackn t csd1 t ahd1 t rds t wth note: t rdh is specified from the first ne g ate timin g for a21 to a0, cs3 , and rd . figure 22.17 address data multiplex i/o spa ce cycle (1 software wait + 1 external wait) 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 579 of 716 rej09b0398-0500 22.3.4 direct memory a ccess controller timing table 22.8 shows the direct memory access controller timing. table 22.8 direct memory access controller timing conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc 10 % , v ss = av ss = 0 v, ta = ? 20 to +75 c item symbol min max unit figure dreq0 and dreq1 setup time t drqs 18 ? ns 22.18 dreq0 and dreq1 hold time t drqh 18 ? ns dreq0 and dreq1 pulse width t drqw 1.5 ? t cyc 22.19 drak output delay time t drakd 18 ? ns 22.20 ck t drqh t drqs t drqs t drqs dreq0 , dreq1 level dreq0 , dreq1 edge dreq0 , dreq1 level clear figure 22.18 dreq0 and dreq1 input timing (1) 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 580 of 716 rej09b0398-0500 ck t drqw dreq0 , dreq1 edge figure 22.19 dreq0 and dreq1 input timing (2) ck t drakd t drakd drakn figure 22.20 drak output delay time 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 581 of 716 rej09b0398-0500 22.3.5 multifunction timer pulse unit timing table 22.9 shows the multifunction timer pulse unit timing table 22.9 multifunction timer pulse unit timing conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc 10 % , v ss = av ss = 0 v, ta = ? 20 to +75 c item symbol min max unit figure output compare output delay time t tocd ? 100 ns 22.21 input capture input setup time t tics 30 ? ns timer input setup time t tcks 35 ? ns timer clock pulse width (single edge specification) t tckwh/l 1.5 ? t cyc 22.22 timer clock pulse width (both edges specified) t tckwh/l 2.5 ? t cyc timer clock pulse width (phase measurement mode) t tckwh/l 2.5 ? t cyc ck t tocd t tics output compare output input capture input figure 22.21 mtu i/o timing 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 582 of 716 rej09b0398-0500 ck t tckwl tclka to tclkd t tcks t tcks t tckwh figure 22.22 mtu clock input timing 22.3.6 i/o port timing table 22.10 shows the i/o port timing. table 22.10 i/o port timing conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc 10 % , v ss = av ss = 0 v, ta = ? 20 to +75 c item symbol min max unit figure port output data delay time t pwd ? 100 ns 22.23 port input hold time t prh 35 ? ns port input setup time t prs 35 ? ns ck t prs t pwd port (read) port (write) t prh t1 t2 figure 22.23 i/o port i/o timing 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 583 of 716 rej09b0398-0500 22.3.7 watchdog timer timing table 22.11 shows the watchdog timer timing. table 22.11 watchdog timer timing conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc 10 % , v ss = av ss = 0 v, ta = ? 20 to +75 c item symbol min max unit figure wdtovf delay time t wovd ? 100 ns 22.24 t wovd t wovd ck wdtovf figure 22.24 watchdog timer timing 22.3.8 serial communication interface timing table 22.12 shows the serial communication interface timing. table 22.12 serial communication interface timing conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc 10 % , v ss = av ss = 0 v, ta = ? 20 to +75 c item symbol min max unit figure input clock cycle t scyc 4 ? t cyc 22.25 input clock cycle (clock sync) t scyc 6 ? t cyc input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ? 1.5 t cyc input clock fall time t sckf ? 1.5 t cyc transmit data delay time (clock sync) t txd ? 100 ns 22.26 receive data setup time (clock sync) t rxs 100 ? ns receive data hold time (clock sync) t rxh 100 ? ns 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 584 of 716 rej09b0398-0500 sck0, sck1 t sckw t sckr t sckf t scyc figure 22.25 input clock timing t scyc t txd t rxs t rxh sck0, sck1 txd0, txd1 (transmit data) rxd0, rxd1 (receive data) figure 22.26 sci i/o timing (clock sync mode) 22.3.9 high speed a/d converter timing ? sh7014 ? table 22.13 shows the high-speed a/d converter timing. table 22.13 high-speed a/d converter timing conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc 10 % , v ss = av ss = 0 v, ta = ? 20 to +75 c item symbol min typ max unit figure a/d conversion start cks = 0 t d 1.5 1.5 1.5 t cyc 22.27 delay time cks = 1 1.5 1.5 1.5 input sampling time cks = 0 t spl 20 20 20 cks = 1 40 40 40 a/d conversion time cks = 0 t conv 42.5 42.5 42.5 cks = 1 82.5 82.5 82.5 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 585 of 716 rej09b0398-0500 address write si g nal adst samplin g timin g adf t d t conv t spl t cp le g end: t d : t spl : t conv : t cp : a/d conversion start delay time input samplin g time a/d conversion time operation time figure 22.27 analog conversion timing 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 586 of 716 rej09b0398-0500 22.3.10 mid-speed converter timing ? sh7016, sh7017 ? table 22.14 shows the mid-speed a/d converter timing. table 22.14 mid-speed a/d converter timing conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc 10 % , v ss = av ss = 0v, ta = ? 20 to +75 c item symbol min typ max unit figure a/d conversion start cks = 0 t d 10 ? 17 t cyc 22.28 delay time cks = 1 6 ? 9 input sampling time cks = 0 t spl ? 64 ? cks = 1 ? 32 ? a/d conversion time cks = 0 t conv 259 ? 266 cks = 1 131 ? 134 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 587 of 716 rej09b0398-0500 (1) (2) ck adf t d t spl t conv le g end: (1): write cycle of adcsr (2): address of adcsr t d : a/d conversion start delay time t spl : input samplin g time t conv : a/d conversion time address write si g nal input samplin g timin g figure 22.28 analog conversion timing 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 588 of 716 rej09b0398-0500 22.3.11 measuring conditions for ac characteristics ? input reference levels: ? high level: 2.2 v ? low level: 0.8 v ? output reference levels: ? high level: 2.0 v ? low level: 0.8 v c l i ol i oh v ref lsi output pin dut output v note: c l is set with the followin g pins, includin g the total capacitance of the measurement ji g , etc: ck, ras , casx , rdwr, cs0 to cs3 , ah , dack0, dack1 a21 to a0, d15 to d0, rd , wrx port output and peripheral module output pins other than the above. see table 22.3, permitted output current values. 30 pf: 50 pf: 70 pf: i ol , i oh : figure 22.29 output test circuit 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 589 of 716 rej09b0398-0500 22.4 a/d converter characteristics tables 22.15 and 22.16 show a/d converter characteristics for the hd6417014 and hd6417014r, and table 22.17 shows a/d converter characteristics for the sh7016 and sh7017. the hd6417014r has an absolute error of 8 lsb or less. table 22.15 a/d converter characteristics (hd6417014) conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc 10 % , v ss = av ss = 0 v, ta = ? 20 to +75 c 28.7mhz item min typ max unit resolution 10 10 10 bits conversion time * 1 ? ? 2.9 s analog input capacitance ? ? 20 pf permitted signal source impedance ? ? 1 k non-linear error * 2 ? ? 8 lsb offset error * 2 ? ? 8 lsb full-scale error * 2 ? ? 8 lsb quantization error * 2 ? ? 0.5 lsb absolute error * 1 ? ? 15 lsb notes: 1. cks = 1 2. reference values 22. electrical characteristics (5 v 28.7 mhz) rev.5.00 sep. 27, 2007 page 590 of 716 rej09b0398-0500 table 22.16 a/d converter characteristics (hd6417014r) conditions: v cc = 5.0 v 10 % , av cc = v cc 10 % , v cc = av cc = 0 v, ta = ? 20 to +75 c 28.7mhz item min typ max unit resolution 10 10 10 bit conversion time * 1 ? ? 2.9 s analog input capacitance ? ? 20 pf permission signal source impedance ? ? 1 k non-linear error * 2 ? ? 8 lsb offset error * 2 ? ? 8 lsb full scale error * 2 ? ? 8 lsb quantize error * 2 ? ? 0.5 lsb absolute error * 1 ? ? 8 lsb notes: 1. cks = 1 2. reference values table 22.17 a/d converter characteristics (sh7016, sh7017) conditions: v cc = 5.0 v 10 % , av cc = 5.0 v 10 % , av cc = v cc = 0 v, v ss = av ss = 0 v, ta = ? 20 to +75 c 28.7mhz 20mhz item min typ max min typ max unit resolution 10 10 10 10 10 10 bit conversion time (when cks = 0) ? ? 9.3 ? ? 13.4 * 2 s analog input capacity ? ? 20 ? ? 20 pf permission signal source impedance ? ? 1 ? ? 1 k non-linearity error * 1 ? ? 3 ? ? 3 lsb offset error * 1 ? ? 3 ? ? 3 lsb full scale error * 1 ? ? 3 ? ? 3 lsb quantize error * 1 ? ? 0.5 ? ? 0.5 lsb absolute error ? ? 4 ? ? 4 lsb notes: 1. reference value 2. 6.7 s when cks = 1. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 591 of 716 rej09b0398-0500 appendix a on-chip supporting module registers a.1 addresses table a.1 on-chip i/o register addresses bit names address register abbr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff81a0 smr0 c/ a chr pe o/ e stop mp cks1 cks0 sci h'ffff81a1 brr0 h'ffff81a2 scr0 tie rie te re mpie teie cke1 cke0 h'ffff81a3 tdr0 h'ffff81a4 ssr0 tdre rdrf orer fer per tend mpb mpbt h'ffff81a5 rdr0 h'ffff81a6 to h'ffff81af ? ? ? ? ? ? ? ? ? h'ffff81b0 smr1 c/ a chr pe o/ e stop mp cks1 cks0 h'ffff81b1 brr1 h'ffff81b2 scr1 tie rie te re mpie teie cke1 cke0 h'ffff81b3 tdr1 h'ffff81b4 ssr1 tdre rdrf orer fer per tend mpb mpbt h'ffff81b5 rdr1 h'ffff81b6 to h'ffff81ff ? ? ? ? ? ? ? ? ? h'ffff8200 to h'ffff823f ? ? ? ? ? ? ? ? ? mtu h'ffff8240 tstr ? ? ? ? ? cst2 cst1 cst0 h'ffff8241 tsyr ? ? ? ? ? sync2 sync1 sync0 h'ffff8242 to h'ffff825f ? ? ? ? ? ? ? ? ? h'ffff8260 tcr0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'ffff8261 tmdr0 ? ? bfb bfa md3 md2 md1 md0 h'ffff8262 tior0h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ffff8263 tior0l iod3 iod2 iod1 iod0 ioc3 ioc 2 ioc1 ioc0 h'ffff8264 tier0 ttge ? ? tciev tgied tgiec tgieb tgiea h'ffff8265 tsr0 ? ? ? tcfv tgfd tgfc tgfb tgfa h'ffff8266 tcnt0 h'ffff8267 appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 592 of 716 rej09b0398-0500 bit names address register abbr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff8268 tgr0a mtu h'ffff8269 h'ffff826a tgr0b h'ffff826b h'ffff826c tgr0c h'ffff826d h'ffff826e tgr0d h'ffff826f h'ffff8270 to h'ffff827f ? ? ? ? ? ? ? ? ? h'ffff8280 tcr1 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'ffff8281 tmdr1 ? ? ? ? md3 md2 md1 md0 h'ffff8282 tior1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ffff8283 ? ? ? ? ? ? ? ? ? h'ffff8284 tier1 ttge ? tcieu tciev ? ? tgieb tgiea h'ffff8285 tsr1 tcfd ? tcfu tcfv ? ? tgfb tgfa h'ffff8286 tcnt1 h'ffff8287 h'ffff8288 tgr1a h'ffff8289 h'ffff828a tgr1b h'ffff828b h'ffff828c to h'ffff829f ? ? ? ? ? ? ? ? ? h'ffff82a0 tcr2 ? cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'ffff82a1 tmdr2 ? ? ? ? md3 md2 md1 md0 h'ffff82a2 tior2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ffff82a3 ? ? ? ? ? ? ? ? ? h'ffff82a4 tier2 ttge ? tcieu tciev ? ? tgieb tgiea h'ffff82a5 tsr2 tcfd ? tcfu tcfv ? ? tgfb tgfa h'ffff82a6 tcnt2 h'ffff82a7 h'ffff82a8 tgr2a h'ffff82a9 h'ffff82aa tgr2b h'ffff82ab h'ffff82ac to h'ffff8347 ? ? ? ? ? ? ? ? ? appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 593 of 716 rej09b0398-0500 bit names address register abbr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff8348 ipra intc h'ffff8349 h'ffff834a iprb h'ffff834b h'ffff834c iprc h'ffff834d h'ffff834e iprd h'ffff834f h'ffff8350 ipre h'ffff8351 h'ffff8352 iprf h'ffff8353 h'ffff8354 iprg h'ffff8355 h'ffff8356 iprh h'ffff8357 h'ffff8358 icr nmil ? ? ? ? ? ? nmie h'ffff8359 irq0s irq1s irq2s irq3s ? ? irq6s irq7s h'ffff835a isr ? ? ? ? ? ? ? ? h'ffff835b irq0f irq1f irq2f irq3f ? ? irq6f irq7f h'ffff835c to h'ffff8381 ? ? ? ? ? ? ? ? ? h'ffff8382 padrl pa15dr pa14dr * 1 pa13dr * 1 pa12dr * 1 pa11dr * 1 pa10dr * 1 pa9dr pa8dr i/o h'ffff8383 pa7dr pa6dr pa5dr pa4dr pa3dr pa2dr pa1dr pa0dr h'ffff8384 ? ? ? ? ? ? ? ? ? pfc h'ffff8385 ? ? ? ? ? ? ? ? ? h'ffff8386 paiorl pa15ior pa14ior * 1 pa13ior * 1 pa12ior * 1 pa11ior * 1 pa10ior * 1 pa9ior * 1 pa8ior * 1 h'ffff8387 pa7ior pa6ior pa5ior pa4ior pa3ior pa2ior pa1ior pa0ior h'ffff8388 ? ? ? ? ? ? ? ? ? h'ffff8389 ? ? ? ? ? ? ? ? ? appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 594 of 716 rej09b0398-0500 bit names address register abbr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff838a ? ? ? ? ? ? ? ? ? pfc h'ffff838b ? ? ? ? ? ? ? ? ? h'ffff838c pacrl1 ? pa15md ? pa14md * 1 ? pa13md * 1 ? pa12md * 1 h'ffff838d ? pa11md * 1 ? pa10md * 1 pa9md1 pa9md0 pa8md1 pa8md0 h'ffff838e pacrl2 pa7md1 pa7md0 pa6md1 pa6md0 pa5md1 pa5md0 ? pa4md h'ffff838f ? pa3md pa2md1 pa2md0 ? pa1md ? pa0md h'ffff8390 pbdr ? ? ? ? ? ? pb9dr pb8dr i/o h'ffff8391 pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr * 1 pb0dr * 1 h'ffff8392 pcdr * 2 pc15dr pc14dr pc13dr pc12dr pc11dr pc10dr pc9dr pc8dr h'ffff8393 pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr h'ffff8394 pbior ? ? ? ? ? ? pb9ior pb8ior pfc h'ffff8395 pb7ior pb6ior pb5ior pb4ior pb3ior pb2ior pb1ior * 1 pb0ior * 1 h'ffff8396 pcior * 2 pc15ior pc14ior pc13ior pc12ior pc11ior pc10ior pc9ior pc8ior h'ffff8397 pc7ior pc6ior pc5ior pc 4ior pc3ior pc2ior pc1ior pc0ior h'ffff8398 pbcr1 ? ? ? ? ? ? ? ? h'ffff8399 ? ? ? ? pb9md1 pb9md0 pb8md1 pb8md0 h'ffff839a pbcr2 pb7md1 pb7md0 pb6md1 pb6md0 pb5md1 pb5md0 pb4md1 pb4md0 h'ffff839b pb3md1 pb3md0 pb2md1 pb2md0 ? pb1md * 1 ? pb0md * 1 h'ffff839c pccr * 2 pc15md pc14md pc13md pc12md pc11md pc10md pc9md pc8md h'ffff839d pc7md pc6md pc5md pc4md pc3md pc2md pc1md pc0md h'ffff839e ? ? ? ? ? ? ? ? ? h'ffff839f ? ? ? ? ? ? ? ? ? h'ffff83a0 ? ? ? ? ? ? ? ? ? i/o h'ffff83a1 ? ? ? ? ? ? ? ? ? h'ffff83a2 pddrl * 2 pd15dr pd14dr pd13dr pd12dr pd11dr pd10dr pd9dr pd8dr h'ffff83a3 pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr h'ffff83a4 ? ? ? ? ? ? ? ? ? pfc h'ffff83a5 ? ? ? ? ? ? ? ? ? h'ffff83a6 pdiorl * 2 pd15ior pd14ior pd13ior pd12ior pd11ior pd10ior pd9ior pd8ior h'ffff83a7 pd7ior pd6ior pd5ior pd 4ior pd3ior pd2ior pd1ior pd0ior h'ffff83a8 ? ? ? ? ? ? ? ? ? h'ffff83a9 ? ? ? ? ? ? ? ? ? h'ffff83aa ? ? ? ? ? ? ? ? ? h'ffff83ab ? ? ? ? ? ? ? ? ? appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 595 of 716 rej09b0398-0500 bit names address register abbr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff83ac pdcrl * 2 pd15md pd14md pd13md pd12md pd11md pd10md pd9md pd8md pfc h'ffff83ad pd7md pd6md pd5md pd4md pd3md pd2md pd1md pd0md h'ffff83ae ? ? ? ? ? ? ? ? ? h'ffff83af ? ? ? ? ? ? ? ? ? h'ffff83b0 pedr pe15dr pe14dr pe13 dr pe12dr pe11dr pe10dr pe9dr pe8dr i/o h'ffff83b1 pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr h'ffff83b2 pfdr ? ? ? ? ? ? ? ? h'ffff83b3 pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr h'ffff83b4 peior pe15ior pe14ior pe13ior pe12ior pe11ior pe10ior pe9ior pe8ior pfc h'ffff83b5 pe7ior pe6ior pe5ior pe4ior pe3ior pe2ior pe1ior pe0ior h'ffff83b6 ? ? ? ? ? ? ? ? ? h'ffff83b7 ? ? ? ? ? ? ? ? ? h'ffff83b8 pecr1 pe15md1 pe15md0 pe14md1 pe14md0 ? ? ? ? h'ffff83b9 ? ? ? ? ? ? ? ? h'ffff83ba pecr2 ? pe7md ? pe6md ? pe5md ? pe4md h'ffff83bb pe3md1 pe3md0 pe2md1 pe2md0 pe1md1 pe1md0 pe0md1 pe0md0 h'ffff83bc to h'ffff83cf ? ? ? ? ? ? ? ? ? ? h'ffff83d0 cmstr ? ? ? ? ? ? ? ? cmt h'ffff83d1 ? ? ? ? ? ? str1 str0 h'ffff83d2 cmcsr0 ? ? ? ? ? ? ? ? h'ffff83d3 cmf cmie ? ? ? ? cks1 cks0 h'ffff83d4 cmcnt0 h'ffff83d5 h'ffff83d6 cmcor0 h'ffff83d7 h'ffff83d8 cmcsr1 ? ? ? ? ? ? ? ? h'ffff83d9 cmf cmie ? ? ? ? cks1 cks0 h'ffff83da cmcnt1 h'ffff83db h'ffff83dc cmcor1 h'ffff83dd h'ffff83de ? ? ? ? ? ? ? ? ? h'ffff83df ? ? ? ? ? ? ? ? ? appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 596 of 716 rej09b0398-0500 bit names address register abbr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff83e0 adcsr adf adie adst cks grp ch2 ch1 ch0 h'ffff83e1 adcr ? pwr trgs1 trgs0 scan dsmp bufe1 bufe0 h'ffff83e2 to h'ffff83ef ? ? ? ? ? ? ? ? ? a/d (high speed) (sh7014) h'ffff83f0 addra ? ? ? ? ? ? ad9 ad8 h'ffff83f1 ad7 ad6 ad 5 ad4 ad3 ad2 ad1 ad0 h'ffff83f2 addrb ? ? ? ? ? ? ad9 ad8 h'ffff83f3 ad7 ad6 ad 5 ad4 ad3 ad2 ad1 ad0 h'ffff83f4 addrc ? ? ? ? ? ? ad9 ad8 h'ffff83f5 ad7 ad6 ad 5 ad4 ad3 ad2 ad1 ad0 h'ffff83f6 addrd ? ? ? ? ? ? ad9 ad8 h'ffff83f7 ad7 ad6 ad 5 ad4 ad3 ad2 ad1 ad0 h'ffff83f8 addre ? ? ? ? ? ? ad9 ad8 h'ffff83f9 ad7 ad6 ad 5 ad4 ad3 ad2 ad1 ad0 h'ffff83fa addrf ? ? ? ? ? ? ad9 ad8 h'ffff83fb ad7 ad6 ad 5 ad4 ad3 ad2 ad1 ad0 h'ffff83fc addrg ? ? ? ? ? ? ad9 ad8 h'ffff83fd ad7 ad6 ad 5 ad4 ad3 ad2 ad1 ad0 h'ffff83fe addrh ? ? ? ? ? ? ad9 ad8 h'ffff83ff ad7 ad6 ad 5 ad4 ad3 ad2 ad1 ad0 h'ffff8400 to h'ffff841f ? ? ? ? ? ? ? ? ? h'ffff8420 addra ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffff8421 ad1 ad0 ? ? ? ? ? ? h'ffff8422 addrb ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffff8423 ad1 ad0 ? ? ? ? ? ? h'ffff8424 addrc ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d (mid- speed) (sh7016 /17) h'ffff8425 ad1 ad0 ? ? ? ? ? ? h'ffff8426 addrd ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffff8427 ad1 ad0 ? ? ? ? ? ? h'ffff8428 adcsr adf adie adst scan cks ch2 ch1 ch0 h'ffff8429 adcr trge ? ? ? ? ? ? ? h'ffff842a to h'ffff857f ? ? ? ? ? ? ? ? ? appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 597 of 716 rej09b0398-0500 bit names address register abbr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff8580 flmcr1 fwe swe esu1 psu1 ev1 pv1 e1 p1 h'ffff8581 flmcr2 fler ? ? ? ? ? ? ? h'ffff8582 ebr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 h'ffff8583 to h'ffff860f ? ? ? ? ? ? ? ? ? flash (f-ztat version only) h'ffff8610 tcsr ovf wt/it tme ? ? cks2 cks1 cks0 wdt h'ffff8610 tcnt * 3 h'ffff8611 tcnt * 4 h'ffff8612 rstcsr * 3 wovf rste ? ? ? ? ? ? h'ffff8613 rstcsr * 4 wovf rste ? ? ? ? ? ? h'ffff8614 sbycr sby hiz ? ? ? ? ? ? power- down state h'ffff8615 to h'ffff861f ? ? ? ? ? ? ? ? ? bsc h'ffff8620 bcr1 ? ? ? ? ? ? ? ioe h'ffff8621 ? ? ? ? a3sz a2sz a1sz a0sz h'ffff8622 bcr2 iw31 iw30 iw21 iw20 iw11 iw10 iw01 iw00 h'ffff8623 cw3 cw2 cw1 cw0 sw3 sw2 sw1 sw0 h'ffff8624 wcr1 w33 w32 w31 w30 w23 w22 w21 w20 h'ffff8625 w13 w12 w11 w10 w03 w02 w01 w00 h'ffff8626 wcr2 ? ? ? ? ? ? ? ? h'ffff8627 ? ? ddw1 ddw0 dsw3 dsw2 dsw1 dsw0 h'ffff8628 ramer ? ? ? ? ? ? ? ? h'ffff8629 ? ? ? ? ? rams ram1 ram0 flash (f-ztat version only) h'ffff862a dcr tpc rcd tras1 tras0 dww1 dww0 dwr1 dwr0 bsc h'ffff862b diw ? be rasd ? sz0 amx1 amx0 h'ffff862c rtcsr ? ? ? ? ? ? ? ? h'ffff862d ? cmf cmie cks2 cks1 cks0 rfsh rmd h'ffff862e rtcnt ? ? ? ? ? ? ? ? h'ffff862f h'ffff8630 rtcor ? ? ? ? ? ? ? ? h'ffff8631 h'ffff8632 to h'ffff86af ? ? ? ? ? ? ? ? ? appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 598 of 716 rej09b0398-0500 bit names address register abbr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff86b0 dmaor ? ? ? ? ? ? ? ? dmac h'ffff86b1 ? ? ? ? ? ae nmif dme h'ffff86b2 to h'ffff86bf ? ? ? ? ? ? ? ? ? h'ffff86c0 sar0 h'ffff86c1 h'ffff86c2 h'ffff86c3 h'ffff86c4 dar0 h'ffff86c5 h'ffff86c6 h'ffff86c7 h'ffff86c8 dmatcr0 h'ffff86c9 h'ffff86ca h'ffff86cb h'ffff86cc chcr0 ? ? ? ? ? ? ? ? h'ffff86cd ? ? ? ? ? rl am al h'ffff86ce dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 h'ffff86cf ? ds tm ts1 ts0 ie te de h'ffff86d0 sar1 h'ffff86d1 h'ffff86d2 h'ffff86d3 h'ffff86d4 dar1 h'ffff86d5 h'ffff86d6 h'ffff86d7 h'ffff86d8 dmatcr1 h'ffff86d9 h'ffff86da h'ffff86db h'ffff86dc chcr1 ? ? ? ? ? ? ? ? h'ffff86dd ? ? ? ? ? rl am al h'ffff86de dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 h'ffff86df ? ds tm ts1 ts0 ie te de appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 599 of 716 rej09b0398-0500 bit names address register abbr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff87e0 to h'ffff873f ? ? ? ? ? ? ? ? ? ? h'ffff8740 ccr ? ? ? ? ? ? ? ? cac h'ffff8741 ? ? ? cedram cecs3 cecs2 cecs1 cecs0 h'ffff8742 to h'ffff87ff ? ? ? ? ? ? ? ? ? notes: 1. reserved bit in the sh7014. 2. in the sh7014, this address is reserved and must not be accessed. 3. write address. 4. read address. for details, see section 13.2.4, notes on register access, in section 13, watchdog timer. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 600 of 716 rej09b0398-0500 a.2 functions item bit nmae initial value r/w 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 2 mp 0 r/w 1 cks1 0 r/w 0 cks0 0 r/w bit bit 7 6 5 4 3 2 1, 0 value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 name communication mode (c/ a ) character len g th (chr) parity enable (pe) parity mode (o/ e ) stop bit len g th (stop) multiprocessor mode (mp) clock select 1 and 0 (cks1 and cks0) description asynchronous mode clock synchronous mode 8-bit data (initial value) 7-bit data (initial value) parity bit not added or checked (initial value) parity bit added and checked even parity (initial value) odd parity 1 stop bit (initial value) 2 stop bits multiprocessor function disabled (initial value) multiprocessor format selected /4 (initial value) /16 /64 /256 descriptions of bit settin g s initial bit values (when two or more bits are described as a set, the hi g her bits are on the left and the lower bits on the ri g ht.) bit acronym bit numbers re g ister outline bit functions h'ffff81a0 (channel 0) h'ffff81b0 (channel 1) 8/16 serial mode re g ister (smr) start address module access size sci re g ister acronym appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 601 of 716 rej09b0398-0500 intc interrupt priority register a (ipra) h'ffff8348 8/16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name description 15 to 12 (irq0 priority level setting) sets the irq0 priority level 11 to 8 (irq1 priority level setting) sets the irq1 priority level 7 to 4 (irq2 priority level setting) sets the irq2 priority level 3 to 0 (irq3 priority level setting) sets the irq3 priority level interrupt priority register b (iprb) h'ffff834a 8/16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit name description 7 to 4 (irq6 priority level setting) sets the irq6 priority level 3 to 0 (irq7 priority level setting) sets the irq7 priority level appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 602 of 716 rej09b0398-0500 intc interrupt priority register c (iprc) h'ffff834c 8/16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r bit name description 15 to 12 (dmac0 priority level setting) sets the dmac0 priority level 11 to 8 (dmac1 priority level setting) sets the dmac1 priority level interrupt priority register d (iprd) h'ffff834e 8/16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name description 15 to 12 (mtu0 priority level setting) sets the mtu0 priority level 11 to 8 (mtu0 priority level setting) sets the mtu0 priority level 7 to 4 (mtu1 priority level setting) sets the mtu1 priority level 3 to 0 (mtu1 priority level setting) sets the mtu1 priority level appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 603 of 716 rej09b0398-0500 intc interrupt priority register e (ipre) h'ffff8350 8/16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r r r r r r r r bit name description 15 to 12 (mtu2 priority level setting) sets the mtu2 priority level 11 to 8 (mtu2 priority level setting) sets the mtu2 priority level interrupt priority register f (iprf) h'ffff8352 8/16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit name description 7 to 4 (sci0 priority level setting) sets the sci0 priority level 3 to 0 (sci1 priority level setting) sets the sci1 priority level appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 604 of 716 rej09b0398-0500 intc interrupt priority register g (iprg) h'ffff8354 8/16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name D D D D initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r r r r r/w r/w r/w r/w r/w r/w r/w r/w bit name description 15 to 12 (a/d priority level setting) sets the a/d priority level 7 to 4 (cmt0 priority level setting) sets the cmt0 priority level 3 to 0 (cmt1 priority level setting) sets the cmt1 priority level interrupt priority register h (iprh) h'ffff8356 8/16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name D D D D D D D D D D D D initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r r r r r r r r r r r r bit name description 15 to 12 (wdt and bsc priority level setting) set the wdt and bsc priority level appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 605 of 716 rej09b0398-0500 intc interrupt control register (icr) h'ffff8358 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name nmil D D D D D D nmie initial value * 0 0 0 0 0 0 0 r/w r r r r r r r r/w item 7 6 5 4 3 2 1 0 bit name irq0s irq1s irq2s irq3s D D irq6s irq7s initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r r r/w r/w note: * when nmi input is high: 1; when nmi input is low: 0 bit name value description 0 nmi input level is low 15 nmi input level (nmil) 1 nmi input level is high 0 interrupt request is detected on falling edge of nmi input (initial value) 8 nmi edge select (nmie) 1 interrupt request is detected on rising edge of nmi input 0 interrupt request is detected on low level of irq input (initial value) 7 to 4, 1, 0 irq0 to irq3, irq6, irq7 sense select (irq0s to irq3s, irq6s, irq7s) 1 interrupt request is detected on falling edge of irq input appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 606 of 716 rej09b0398-0500 intc irq status register (isr) h'ffff835a 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r r item 7 6 5 4 3 2 1 0 bit name irq0f irq1f irq2f irq3f D D irq6f irq7f initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r r r/w r/w bit name value detection setting description 0 level detection no irqn interrupt request exists. clear condition: when irqn input is high level edge detection no irqn interrupt request was detected. (initial value) clear conditions: 1. when a 0 is written after reading irqnf = 1 status 2. when irqn interrupt exception processing has been execute level detection an irqn interrupt request exists. set condition: when irqn input is low level 7 to 4, 1, 0 irq0 to irq3, irq6, irq7 flags (irq0f to irq3f, irq6f, irq7f) 1 edge detection an irqn interrupt request was detected. set condition: when a falling edge occurs at an irqn input appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 607 of 716 rej09b0398-0500 cac cache control register (ccr) h'ffff8740 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name D D D D D D D D initial value * * * * * * * * r/w r r r r r r r r item 7 6 5 4 3 2 1 0 bit name D D D cedram cecs3 cecs2 cecs1 cecs0 initial value * * * 0 0 0 0 0 r/w r r r r/w r/w r/w r/w r/w note: * undefined bit name value description 0 dram space cache disabled (initial value) 4 dram space cache enable (cedram) 1 dram space cache enabled 0 cs3 space cache disabled (initial value) 3 cs3 space cache enable (cecs3) 1 cs3 space cache enabled 0 cs2 space cache disabled (initial value) 2 cs2 space cache enable (cecs2) 1 cs2 space cache enabled 0 cs1 space cache disabled (initial value) 1 cs1 space cache enable (cecs1) 1 cs1 space cache enabled 0 cs0 space cache disabled (initial value) 0 cs0 space cache enable (cecs0) 1 cs0 space cache enabled appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 608 of 716 rej09b0398-0500 bsc bus control register 1 (bcr1) h'ffff8620 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name D D D D D D D ioe initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r r/w item 7 6 5 4 3 2 1 0 bit name D D D D a3sz a2sz a1sz a0sz initial value 0 0 0 0 1 1 1 1 r/w r r r r r/w r/w r/w r/w bit name value description 0 cs3 space is ordinary space (initial value) 8 multiplex i/o enable (ioe) 1 cs3 space is address/data multiplex i/o space 0 byte (8-bit) size 3 cs3 space size specification (a3sz) 1 word (16-bit) size (initial value) 0 byte (8-bit) size 2 cs2 space size specification (a2sz) 1 word (16-bit) size (initial value) 0 byte (8-bit) size 1 cs1 space size specification (a1sz) 1 word (16-bit) size (initial value) 0 byte (8-bit) size 0 cs0 space size specification (a0sz) 1 word (16-bit) size (initial value) note: a0sz is effective only in on-chip rom effective mode. in on-chip rom ineffective mode, the cs0 space bus size is specified by the mode pin. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 609 of 716 rej09b0398-0500 bsc bus control register 2 (bcr2) h'ffff8622 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name iw31 iw30 iw21 iw20 iw11 iw10 iw01 iw00 initial value 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name cw3 cw2 cw1 cw0 sw3 sw2 sw1 sw0 initial value 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name value description 0 no idle cycle after accessing cs3 space 0 1 inserts one idle cycle 0 inserts two idle cycles iw31, iw30 1 1 inserts three idle cycles (initial value) 0 no idle cycle after accessing cs2 space 0 1 inserts one idle cycle 0 inserts two idle cycles iw21, iw20 1 1 inserts three idle cycles (initial value) 0 no idle cycle after accessing cs1 space 0 1 inserts one idle cycle 0 inserts two idle cycles iw11, iw10 1 1 inserts three idle cycles (initial value) 0 no idle cycle after accessing cs0 space 0 1 inserts one idle cycle 0 inserts two idle cycles 15 to 8 idles between cycles (iw31, iw30, iw21, iw20, iw11, iw10, iw01, iw00) iw01, iw00 1 1 inserts three idle cycles (initial value) 0 no cs3 space continuous access idle cycles 7 idle specification for continuous access (cw3) 1 one cs3 space continuous access idle cycle (initial value) 0 no cs2 space continuous access idle cycles 6 idle specification for continuous access (cw2) 1 one cs2 space continuous access idle cycle (initial value) 0 no cs1 space continuous access idle cycles 5 idle specification for continuous access (cw1) 1 one cs1 space continuous access idle cycle (initial value) 0 no cs0 space continuous access idle cycles 4 idle specification for continuous access (cw0) 1 one cs0 space continuous access idle cycle (initial value) 0 no cs3 space cs assert extension 3 cs assert extension specification (sw3) 1 cs3 space cs assert extension (initial value) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 610 of 716 rej09b0398-0500 bsc bit name value description 0 no cs2 space cs assert extension 2 cs assert extension specification (sw2) 1 cs2 space cs assert extension (initial value) 0 no cs1 space cs assert extension 1 cs assert extension specification (sw1) 1 cs1 space cs assert extension (initial value) 0 no cs0 space cs assert extension 0 cs assert extension specification (sw0) 1 cs0 space cs assert extension (initial value) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 611 of 716 rej09b0398-0500 bsc wait control register 1 (wcr1) h'ffff8624 8/16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name w33 w32 w31 w30 w23 w22 w21 w20 w13 w12 w11 w10 w03 w02 w01 w00 initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name value description 0 0 0 0 no wait (external wait input disabled) 0 0 0 1 1 wait external wait input enabled 15 to 12 cs3 space wait specification (w33 to w30) 1 1 1 1 15 wait external wait input enabled (initial value) 0 0 0 0 no wait (external wait input disabled) 0 0 0 1 1 wait external wait input enabled 11 to 8 cs2 space wait specification (w23 to w20) 1 1 1 1 15 wait external wait input enabled (initial value) 0 0 0 0 no wait (external wait input disabled) 0 0 0 1 1 wait external wait input enabled 7 to 4 cs1 space wait specification (w13 to w10) 1 1 1 1 15 wait external wait input enabled (initial value) 0 0 0 0 no wait (external wait input disabled) 0 0 0 1 1 wait external wait input enabled 3 to 0 cs0 space wait specification (w03 to w00) 1 1 1 1 15 wait external wait input enabled (initial value) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 612 of 716 rej09b0398-0500 bsc wait control register 2 (wcr2) h'ffff8626 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r r item 7 6 5 4 3 2 1 0 bit name D D ddw1 ddw0 dsw3 dsw2 dsw1 dsw0 initial value 0 0 0 0 1 1 1 1 r/w r r r/w r/w r/w r/w r/w r/w bit name value description 0 0 2-cycle (no wait) external wait disabled (initial value) 0 1 3-cycle (1 wait) external wait disabled 1 0 4-cycle (2 wait) external wait enabled 5, 4 dram space dma single address mode access wait specification (ddw1, ddw0) 1 1 5-cycle (3 wait) external wait enabled 0 0 0 0 no wait (external wait input disabled) 0 0 0 1 1 wait (external wait input enabled) 3 to 0 cs space dma single address mode access wait specification (dsw3 to dsw0) 1 1 1 1 15 wait (external wait input enabled) (initial value) dram area control register (dcr) h'ffff862a 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name tpc rcd tras1 tras0 dww1 dww0 dwr1 dwr0 initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name diw D be rasd D sz0 amx1 amx0 initial value 0 0 0 0 0 0 0 0 r/w r/w r r/w r/w r r/w r/w r/w appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 613 of 716 rej09b0398-0500 bsc bit name value description 0 1.5 cycles (initial value) 15 ras precharge cycle count (tpc) 1 2.5 cycles 0 1 cycle (initial value) 14 ras?cas delay cycle count (rcd) 1 2 cycles 0 0 2.5 cycles (initial value) 0 1 3.5 cycles 1 0 4.5 cycles 13, 12 cas?before-ras refresh ras assert cycle count (tras1 and tras0) 1 1 5.5 cycles 0 0 2-cycle (no wait) external wait disabled (initial value) 0 1 3-cycle (1 wait) external wait disabled 1 0 4-cycle (2 wait) external wait enabled 11, 10 dram write cycle wait count (dww1 and dww0) 1 1 5-cycle (3 wait) external wait enabled 0 0 2-cycle (no wait) external wait disabled (initial value) 0 1 3-cycle (1 wait) external wait disabled 1 0 4-cycle (2 wait) external wait enabled 9, 8 dram read cycle wait count (dwr1 and dwr0) 1 1 5-cycle (3 wait) external wait enabled 0 no idle cycles (initial value) 7 dram idle cycle count (diw) 1 1 idle cycle 0 burst disabled (initial value) 5 burst enable (be) 1 dram high-speed page mode enabled 0 access dram by ras up mode (initial value) 4 ras down mode (rasd) 1 access dram by ras down mode 0 byte (8-bit) (initial value) 2 dram bus width specification (sz0) 1 word (16-bit) 0 0 9 bit (initial value) 0 1 10 bit 1 0 11 bit 1, 0 dram address multiplex (amx1 and amx0) 1 1 12 bit appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 614 of 716 rej09b0398-0500 bsc refresh timer control/status register (rtcsr) h'ffff862c 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r r item 7 6 5 4 3 2 1 0 bit name D cmf cmie cks2 cks1 cks0 rfsh rmd initial value 0 0 0 0 0 0 0 0 r/w r r/w r/w r/w r/w r/w r/w r/w bit name value description 0 clear condition: after rtcsr is read when cmf is 1, 0 is written in cmf (initial value) 6 compare match flag (cmf) 1 set condition: rtcnt = rtcor note: when both rtcnt and rtcor are in an initialized state (when values have not been rewritten since initialization, and rtcnt has not had its value changed due to a countup), rtcnt and rtcor match, as both are h'0000, but in this case cmf is not set. 0 disables an interrupt request caused by cmf (initial value) 5 compare match interrupt enable (cmie) 1 enables an interrupt request caused by cmf 0 stops count-up (initial value) 0 1 /2 0 /8 0 1 1 /32 0 /128 0 1 /512 0 /2048 4 to 2 clock select (cks2 to cks0) 1 1 1 /4096 0 do not refresh dram (initial value) 1 refresh control (rfsh) 1 refresh dram 0 cas-before-ras refresh (initial value) 0 refresh mode (rmd) 1 self-refresh appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 615 of 716 rej09b0398-0500 bsc refresh timer counter (rtcnt) h'ffff862e 8/16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w refresh time constant register (rtcor) h'ffff8630 8/16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 616 of 716 rej09b0398-0500 dmac dma source address registers 0, 1 (sar0, sar1) h'ffff86c0 (channel 0) h'ffff86d0 (channel 1) 16/32 bit item 31 30 29 28 27 26 25 24 23 ................................... 0 bit name ................................... initial value D D D D D D D D D ................................... D r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ................................... r/w dma destination address registers 0, 1 (dar0, dar1) h'ffff86c4 (channel 0) h'ffff86d4 (channel 1) 16/32 bit item 31 30 29 28 27 26 25 24 23 ................................... 0 bit name ................................... initial value D D D D D D D D D ................................... D r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ................................... r/w dma transfer count registers 0, 1 (dmatcr0, dmatcr1) h'ffff86c8 (channel 0) h'ffff86d8 (channel 1) 16/32 bit item 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 bit name D D D D D D D D D D D D D D D D initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r r r r r r r r r r r r r r r r item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name initial value D D D D D D D D D D D D D D D D r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 617 of 716 rej09b0398-0500 dmac dma channel control registers 0, 1 (chcr0, chcr1) h'ffff86cc (channel 0) h'ffff86dc (channel 1) 8/16/32 bit item 31 30 29 28 27 26 25 24 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r r item 23 22 21 20 19 18 17 16 bit name D D D D D rl am al initial value 0 0 0 0 0 0 0 0 r/w r r r r r r/w r/w r/w item 15 14 13 12 11 10 9 8 bit name dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name D ds tm ts1 ts0 ie te de initial value 0 0 0 0 0 0 0 0 r/w r r/w r/w r/w r/w r/w r/(w) r/w bit name value description 0 output drak with active high (initial value) 18 request check level (rl) 1 output drak with active low 0 outputs dack during read cycle (initial value) 17 acknowledge mode (am) 1 outputs dack during write cycle 0 active high output (initial value) 16 acknowledge level (al) 1 active low output 0 destination address fixed (initial value) 0 1 destination address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) 0 destination address decremented (?1 during 8-bit transfer, ?2 during 16-bit transfer, ?4 during 32-bit transfer) 15, 14 destination address mode 1, 0 (dm1 and dm0) 1 1 (setting prohibited) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 618 of 716 rej09b0398-0500 dmac bit name value description 0 source address fixed (initial value) 0 1 source address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) 0 source address decremented (?1 during 8-bit transfer, ?2 during 16-bit transfer, ?4 during 32-bit transfer) 13, 12 source address mode 1, 0 (sm1 and sm0) 1 1 (setting prohibited) 0 external request, dual address mode (initial value) 0 1 (prohibited) 0 external request, single address mode. external address space external device. 0 1 1 external request, single address mode. external device external address space. 0 auto-request 0 1 (prohibited) 0 mtutgi0a 0 1 1 1 mtutgi1a 0 mtutgi2a 0 1 (prohibited) 0 (prohibited) 0 1 1 a/d adi 0 sci0txi0 0 1 rxi0 0 sci1txi1 11 to 8 resource select 3 to 0 (rs3 to rs0) 1 1 1 1 rxi1 0 low-level detection (initial value) 6 dreq select (ds) 1 falling-edge detection 0 cycle steal mode (initial value) 5 transfer mode (tm) 1 burst mode 0 specifies byte size (8 bits) (initial value) 0 1 specifies word size (16 bits) 0 specifies longword size (32 bits) 4, 3 transfer size 1, 0 (ts1, ts0) 1 1 (prohibited) 0 interrupt request not generated after dmatcr?specified transfer count (initial value) 2 interrupt enable (ie) 1 interrupt request enabled on completion of dmatcr specified number of transfers appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 619 of 716 rej09b0398-0500 dmac bit name value description 0 dmatcr?specified transfer count not ended (initial value) clear condition: 0 write after te = 1 read, power-on reset, standby mode 1 transfer end flag (te) 1 dmatcr specified number of transfers completed 0 operation of the corresponding channel disabled (initial value) 0 dmac enable (de) 1 operation of the corresponding channel enabled dmac operation register (dmaor) h'ffff86b0 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r r item 7 6 5 4 3 2 1 0 bit name D D D D D ae nmif dme initial value 0 0 0 0 0 0 0 0 r/w r r r r r r/(w) r/(w) * r/w * note: * 0 write only is valid after 1 is read. bit name value description 0 no address error, dma transfer enabled (initial value) clearing condition: write ae = 0 after reading ae = 1 2 address error flag (ae) 1 address error, dma transfer disabled setting condition: address error due to dmac 0 no nmi interrupt, dma transfer enabled (initial value) clearing condition: write nmif = 0 after reading nmif = 1 1 nmi flag (nmif) 1 nmi has occurred, dmc transfer prohibited set condition: nmi interrupt occurrence 0 disable operation on all channels (initial value) 0 dmac master enable (dme) 1 enable operation on all channels appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 620 of 716 rej09b0398-0500 mtu timer control register 0 (tcr0) h'ffff8260 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name value description 0 tcnt clear disabled (initial value) 0 1 tcnt is cleared by tgra compare-match or input captur 0 tcnt is cleared by tgrb compare-match or input capture 0 1 1 synchronizing clear: tcnt is cleared in synchronization with clear of other channel counters operating in sync. * 1 0 tcnt clear disabled 0 1 tcnt is cleared by tgrc compare-match or input capture * 2 0 tcnt is cleared by tgrd compare-match or input capture * 2 7 to 5 counter clear 2 to 0 (cclr2 to cclr0) 1 1 1 synchronizing clear: tcnt is cleared in synchronization with clear of other channel counters operating in sync * 1 0 count on rising edges (initial value) 0 1 count on falling edges 4, 3 clock edge 1, 0 (ckeg1 and ckeg0) * 4 1 x * 3 count on both rising and falling edges 0 internal clock: count with /1 (initial value) 0 1 internal clock: count with /4 0 internal clock: count with /16 0 1 1 internal clock: count with /64 0 external clock: count with the tclka pin input 0 1 external clock: count with the tclkb pin input 0 external clock: count with the tclkc pin input 2 to 0 timer prescaler 2 to 0 (tpsc2 to tpsc0) 1 1 1 external clock: count with the tclkd pin input notes: 1. setting the sync bit of the tsyr to 1 sets the synchronization. 2. when tgrc or tgrd are functioning as buffer registers, tcnt is not cleared because the buffer registers have priority and compare-match/input captures do not occur. 3. x: 0 or 1, don't care. 4. internal clock edge selection is effective when the input clock is /4 or slower. these settings are ignored when /1, or the overflow/underflow of another channel is selected for the input clock. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 621 of 716 rej09b0398-0500 mtu timer mode register 0 (tmdr0) h'ffff8261 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name D D bfb bfa md3 md2 md1 md0 initial value 1 1 0 0 0 0 0 0 r/w r r r/w r/w r/w r/w r/w r/w bit name value description 0 tgrb operates normally (initial value) 5 buffer operation b (bfb) 1 tgrb and tgrd buffer operation 0 tgra operates normally (initial value) 4 buffer operation a (bfa) 1 tgra and tgrc buffer operation 0 normal operation (initial value) 0 1 reserved (do not set) 0 pwm mode 1 0 1 1 pwm mode 2 0 reserved (do not set) 0 1 reserved (do not set) 0 reserved (do not set) 0 1 1 1 reserved (do not set) 0 reserved (do not set) 0 1 reserved (do not set) 0 reserved (do not set) 0 1 1 reserved (do not set) 0 reserved (do not set) 0 1 reserved (do not set) 0 reserved (do not set) 3 to 0 modes 3 to 0 (md3 to md0) 1 1 1 1 reserved (do not set) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 622 of 716 rej09b0398-0500 mtu timer i/o control register 0h (tior0h) h'ffff8262 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name value description 0 output disabled (initial value) 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 initial output is 0 toggle output on compare- match 0 output disabled 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 1 tgr0b is an output compare register initial output is 1 toggle output on compare- match 0 input capture on rising edge 0 1 input capture on falling edge 0 0 1 1 capture input source is the tioc0b pin input capture on both edges 0 0 1 0 7 to 4 i/o control b3 to b0 (iob3 to iob0) 1 1 1 1 tgr0b is an input capture register capture input source is channel 1/ count clock input capture on tcnt1 count up/count down appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 623 of 716 rej09b0398-0500 mtu bit name value description 0 output disabled (initial value) 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 initial output is 0 toggle output on compare- match 0 output disabled 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 1 tgr0a is an output compare register initial output is 1 toggle output on compare- match 0 input capture on rising edge 0 1 input capture on falling edge 0 0 1 1 capture input source is the tioc0a pin input capture on both edges 0 0 1 0 3 to 0 i/o control a3 to a0 (ioa3 to ioa0) 1 1 1 1 tgr0a is an input capture register capture input source is channel 1/ count clock input capture on tcnt1 count up/count down appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 624 of 716 rej09b0398-0500 mtu timer i/o control register 0l (tior0l) h'ffff8263 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name value description 0 output disabled (initial value) 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 initial output is 0 toggle output on compare- match 0 output disabled 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 1 tgr0d is an output compare register initial output is 1 toggle output on compare- match 0 input capture on rising edge 0 1 input capture on falling edge 0 0 1 1 capture input source is the tioc0d pin input capture on both edges 0 0 1 0 7 to 4 i/o control d3 to d0 (iod3 to iod0) 1 1 1 1 tgr0d is an input capture register capture input source is channel 1/ count clock input capture on tcnt1 count up/count down appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 625 of 716 rej09b0398-0500 mtu bit name value description 0 output disabled (initial value) 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 initial output is 0 toggle output on compare- match 0 output disabled 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 1 tgr0c is an output compare register initial output is 1 toggle output on compare- match 0 input capture on rising edge 0 1 input capture on falling edge 0 0 1 1 capture input source is the tioc0c pin input capture on both edges 0 0 1 0 3 to 0 i/o control c3 to c0 (ioc3 to ioc0) 1 1 1 1 tgr0c is an input capture register capture input source is channel 1/ count clock input capture on tcnt1 count up/count down notes: 1. when the bfb bit of tmdr0 is set to 1 and tgr0d is being used as a buffer register, these settings become ineffective and input capture/output compares do not occur. 2. when the bfa bit of tmdr0 is set to 1 and tgr0c is being used as a buffer register, these settings become ineffective and input capture/output compares do not occur. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 626 of 716 rej09b0398-0500 mtu timer interrupt enable regist er 0 (tier0) h'ffff8264 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name ttge D D tciev tgied tgiec tgieb tgiea initial value 0 0 0 0 0 0 0 0 r/w r/w r r r/w r/w r/w r/w r/w bit name value description 0 disable a/d conversion start requests (initial value) 7 a/d conversion start request enable (ttge) 1 enable a/d conversion start request generation 0 disable tcfv interrupt requests (tciv) (initial value) 4 overflow interrupt enable (tciev) 1 enable tcfv interrupt requests (tciv) 0 disable interrupt requests (tgid) due to the tgfd bit (initial value) 3 tgr interrupt enable d (tgied) 1 enable interrupt requests (tgid) due to the tgfd bit 0 disable interrupt requests (tgic) due to the tgfc bit (initial value) 2 tgr interrupt enable c (tgiec) 1 enable interrupt requests (tgic) due to the tgfc bit 0 disable interrupt requests (tgib) due to the tgfb bit (initial value) 1 tgr interrupt enable b (tgieb) 1 enable interrupt requests (tgib) due to the tgfb bit 0 disable interrupt requests (tgia) due to the tgfa bit (initial value) 0 tgr interrupt enable a (tgiea) 1 enable interrupt requests (tgia) due to the tgfa bit appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 627 of 716 rej09b0398-0500 mtu timer status register 0 (tsr0) h'ffff8265 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name D D D tcfv tgfd tgfc tgfb tgfa initial value 1 1 0 0 0 0 0 0 r/w r r r r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * only 0 writes to clear the flags are possible. bit name value description 0 clear condition: with tcfv = 1, a 0 write to tcfv after reading it (initial value) 4 overflow flag (tcfv) 1 set condition: when the tcnt value overflows (h'ffff h'0000) (initial value) 0 clear condition: with tgfd = 1, a 0 write to tgfd following a read (initial value) 3 input capture/output compare flag d (tgfd) 1 set conditions: ? when tgrd is functioning as an output compare register (tcnt = tgrd) ? when tgrd is functioning as input capture (the tcnt value is sent to tgrd by the input capture signal) 0 clear condition: with tgfc = 1, a 0 write to tgfc following a read (initial value) 2 input capture/output compare flag c (tgfc) 1 set conditions: ? when tgrc is functioning as an output compare register (tcnt = tgrc) ? when tgrc is functioning as input capture (the tcnt value is sent to tgrc by the input capture signal) 0 clear condition: with tgfb = 1, a 0 write to tgfb following a read (initial value) 1 input capture/output compare flag b (tgfb) 1 set conditions: ? when tgrb is functioning as an output compare register (tcnt = tgrb) ? when tgrb is functioning as input capture (the tcnt value is sent to tgrb by the input capture signal) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 628 of 716 rej09b0398-0500 mtu bit name value description 0 clear condition: with tgfa = 1, a 0 write to tgfa following a read * (initial value) 0 input capture/output compare flag a (tgfa) 1 set conditions: ? when tgra is functioning as an output compare register (tcnt = tgra) ? when tgra is functioning as input capture (the tcnt value is sent to tgra by the input capture signal) note: * cleared by dmac transfer due to tgfa. timer counters 0 (t cnt0) h'ffff8266 16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w timer general register 0 (tgr0) h'ffff8268 (0a) h'ffff826a (0b) h'ffff826c (0c) h'ffff826e (0d) 16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 629 of 716 rej09b0398-0500 mtu timer control register 1 (tcr1) h'ffff8280 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name D cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value 0 0 0 0 0 0 0 0 r/w r r/w r/w r/w r/w r/w r/w r/w bit name value description 0 tcnt clear disabled (initial value) 0 1 tcnt is cleared by tgra compare-match or input capture 0 tcnt is cleared by tgrb compare-match or input capture 7 to 5 counter clear 2 to 0 (reserved * 2 , cclr1, cclr0) 0 1 1 synchronizing clear: tcnt is cleared in synchronization with clear of other channel counters operating in sync * 1 0 count on rising edges (initial value) 0 1 count on falling edges 4, 3 clock edge 1, 0 (ckeg1, ckeg0) * 5 1 x * 3 count on both rising and falling edges 0 internal clock: count with /1 (initial value) 0 1 internal clock: count with /4 0 internal clock: count with /16 0 1 1 internal clock: count with /64 0 external clock: count with the tclka pin input 0 1 external clock: count with the tclkb pin input 0 internal clock: count with /256 2 to 0 * 4 timer prescaler 2 to 0 (tpsc2 to tpsc0) 1 1 1 count with the tcnt2 overflow/underflow notes: 1. setting the sync bit of the tsyr to 1 sets the synchronization. 2. the bit 7 of channels 1 is reserved. it always reads 0, and cannot be modified. 3. x: 0 or 1, don't care. 4. these settings are ineffective when channel 1 is in phase counting mode. 5. internal clock edge selection is effective when the input clock is /4 or slower. these settings are ignored when /1, or the overflow/underflow of another channel is selected for the input clock. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 630 of 716 rej09b0398-0500 mtu timer mode register 1 (tmdr1) h'ffff8281 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name D D D D md3 md2 md1 md0 initial value 1 1 0 0 0 0 0 0 r/w r r r r r/w r/w r/w r/w bit name value description 0 normal operation (initial value) 0 1 reserved (do not set) 0 pwm mode 1 0 1 1 pwm mode 2 0 phase counting mode 1 0 1 phase counting mode 2 0 phase counting mode 3 0 1 1 1 phase counting mode 4 0 reserved (do not set) 0 1 reserved (do not set) 0 reserved (do not set) 0 1 1 reserved (do not set) 0 reserved (do not set) 0 1 reserved (do not set) 0 reserved (do not set) 3 to 0 modes 3 to 0 (md3 to md0) 1 1 1 1 reserved (do not set) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 631 of 716 rej09b0398-0500 mtu timer i/o control register 1 (tior1) h'ffff8282 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name value description 0 output disabled (initial value) 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 initial output is 0 toggle output on compare- matc 0 output disabled 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 1 tgr1b is an output compare register initial output is 1 toggle output on compare- matc 0 input capture on rising edge 0 1 input capture on falling edge 0 0 1 1 capture input source is the tioc1b pin input capture on both edges 0 0 1 0 7 to 4 i/o control b3 to b0 (iob3 to iob0) 1 1 1 1 tgr1b is an output compare register capture input source tgr0c compare/match input capture input capture on channel 0/tgr0c compare- match/input capture generation appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 632 of 716 rej09b0398-0500 mtu bit name value description 0 output disabled (initial value) 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 initial output is 0 toggle output on compare- match 0 output disabled 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 1 tgr1a is an output compare register initial output is 1 toggle output on compare- match 0 input capture on rising edge 0 1 input capture on falling edge 0 0 1 1 capture input source is the tioc1a pin input capture on both edges 0 0 1 0 3 to 0 i/o control a3 to a0 (ioa3 to ioa0) 1 1 1 1 tgr1a is an input capture register capture input source tgr0a compare/match input capture input capture on channel 0/tgr0a compare- match/input capture generation appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 633 of 716 rej09b0398-0500 mtu timer interrupt enable regist er 1 (tier1) h'ffff8284 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name ttge D tcieu tciev D D tgieb tgiea initial value 0 1 0 0 0 0 0 0 r/w r/w r r/w r/w r r r/w r/w bit name value description 0 disable a/d conversion start requests (initial value) 7 a/d conversion start request enable (ttge) 1 enable a/d conversion start request generation 0 disable udf interrupt requests (tciu) (initial value) 5 underflow interrupt enable (tcieu) 1 enable udf interrupt requests (tciu) 0 disable tcfv interrupt requests (tciv) (initial value) 4 overflow interrupt enable (tciev) 1 enable tcfv interrupt requests (tciv) 0 disable interrupt requests (tgib) due to the tgfb bit (initial value) 1 tgr interrupt enable b (tgieb) 1 enable interrupt requests (tgib) due to the tgfb bit 0 disable interrupt requests (tgia) due to the tgfa bit (initial value) 0 tgr interrupt enable a (tgiea) 1 enable interrupt requests (tgia) due to the tgfa bit appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 634 of 716 rej09b0398-0500 mtu timer status register 1 (tsr1) h'ffff8285 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name tcfd D tcfu tcfv D D tgfb tgfa initial value 1 1 0 0 0 0 0 0 r/w r/w r r/(w) * r/(w) * r r r/(w) * r/(w) * note: * only 0 writes to clear the flags are possible. bit name value description 0 tcnt counts down 7 count direction flag (tcfd) 1 tcnt counts up (initial value) 0 clear condition: with tcfu = 1, a 0 write to tcfu after reading it (initial value) 5 underflow flag (tcfu) 1 set condition: when the tcnt value underflows (h'0000 h'ffff) 0 clear condition: with tcfv = 1, a 0 write to tcfv after reading it (initial value) 4 overflow flag (tcfv) 1 set condition: when the tcnt value overflows (h'ffff h'0000) 0 clear condition: with tgfb = 1, a 0 write to tgfb following a read (initial value) 1 input capture/output compare flag b (tgfb) 1 set conditions: ? when tgrb is functioning as an output compare register (tcnt = tgrb) ? when tgrb is functioning as input capture (the tcnt value is sent to tgrb by the input capture signal) 0 clear condition: with tgfa = 1, a 0 write to tgfa following a read * (initial value) 0 input capture/output compare flag a (tgfa) 1 set conditions: ? when tgra is functioning as an output compare register (tcnt = tgra) ? when tgra is functioning as input capture (the tcnt value is sent to tgra by the input capture signal) note: * cleared by dmac transfer due to tgfa. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 635 of 716 rej09b0398-0500 mtu timer counters 1 (t cnt1) h'ffff8286 16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w timer general register 1 (tgr1) h'ffff8288 (1a) h'ffff828a (1b) 16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 636 of 716 rej09b0398-0500 mtu timer control register 2 (tcr2) h'ffff82a0 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name D cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value 0 0 0 0 0 0 0 0 r/w r r/w r/w r/w r/w r/w r/w r/w bit name value description 0 tcnt clear disabled (initial value) 0 1 tcnt is cleared by tgra compare-match or input capture 0 tcnt is cleared by tgrb compare-match or input capture 7 to 5 counter clear 2 to 0 (reserved * 2 , cclr1, cclr0) 0 1 1 synchronizing clear: tcnt is cleared in synchronization with clear of other channel counters operating in sync * 1 0 count on rising edges (initial value) 0 1 count on falling edges 4, 3 clock edge 1, 0 (ckeg1 and ckeg0) * 5 1 x * 3 count on both rising and falling edges 0 internal clock: count with /1 (initial value) 0 1 internal clock: count with /4 0 internal clock: count with /16 0 1 1 internal clock: count with /64 0 external clock: count with the tclka pin input 0 1 external clock: count with the tclkb pin input 0 external clock: count with the tclkc pin input 2 to 0 * 4 timer prescaler 2 to 0 (tpsc2 to tpsc0) 1 1 1 internal clock: count with /1024 notes: 1. setting the sync bit of the tsyr to 1 sets the synchronization. 2. the bit 7 of channels 2 is reserved. it always reads 0, and cannot be modified. 3. x: 0 or 1, don't care. 4. these settings are ineffective when channel 2 is in phase counting mode. 5. internal clock edge selection is effective when the input clock is /4 or slower. these settings are ignored when /1 is selected for the input clock. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 637 of 716 rej09b0398-0500 mtu timer mode register 2 (tmdr2) h'ffff82a1 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name D D D D md3 md2 md1 md0 initial value 1 1 0 0 0 0 0 0 r/w r r r r r/w r/w r/w r/w bit name value description 0 normal operation (initial value) 0 1 reserved (do not set) 0 pwm mode 1 0 1 1 pwm mode 2 0 phase counting mode 1 0 1 phase counting mode 2 0 phase counting mode 3 0 1 1 1 phase counting mode 4 0 reserved (do not set) 0 1 reserved (do not set) 0 reserved (do not set) 0 1 1 reserved (do not set) 0 reserved (do not set) 0 1 reserved (do not set) 0 reserved (do not set) 3 to 0 modes 3 to 0 (md3 to md0) 1 1 1 1 reserved (do not set) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 638 of 716 rej09b0398-0500 mtu timer i/o control register 2 (tior2) h'ffff82a2 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name value description 0 output disabled (initial value) 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 initial output is 0 toggle output on compare- match 0 output disabled 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 1 tgr2b is an output compare register initial output is 1 toggle output on compare- match 0 input capture on rising edge 0 1 input capture on falling edge 0 0 1 1 input capture on both edges 0 input capture on rising edge 0 1 input capture on falling edge 0 7 to 4 i/o control b3 to b0 (iob3 to iob0) 1 1 1 1 tgr2b is an input capture register capture input source is the tioc2b pin input capture on both edges appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 639 of 716 rej09b0398-0500 mtu bit name value description 0 output disabled (initial value) 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 initial output is 0 toggle output on compare- match 0 output disabled 0 1 output 0 on compare-match 0 output 1 on compare-match 0 1 1 1 tgr2a is an output compare register initial output is 1 toggle output on compare- match 0 input capture on rising edge 0 1 input capture on falling edge 0 0 1 1 input capture on both edges 0 input capture on rising edge 0 1 input capture on falling edge 0 3 to 0 i/o control a3 to a0 (ioa3 to ioa0) 1 1 1 1 tgr2a is an input capture register capture input source is the tioc2a pin input capture on both edges appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 640 of 716 rej09b0398-0500 mtu timer interrupt enable register 2 (tier2) h'ffff82a4 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name ttge D tcieu tciev D D tgieb tgiea initial value 0 1 0 0 0 0 0 0 r/w r/w r r/w r/w r r r/w r/w bit name value description 0 disable a/d conversion start requests (initial value) 7 a/d conversion start request enable (ttge) 1 enable a/d conversion start request generation 0 disable udf interrupt requests (tciu) (initial value) 5 underflow interrupt enable (tcieu) 1 enable udf interrupt requests (tciu) 0 disable tcfv interrupt requests (tciv) (initial value) 4 overflow interrupt enable (tciev) 1 enable tcfv interrupt requests (tciv) 0 disable interrupt requests (tgib) due to the tgfb bit (initial value) 1 tgr interrupt enable b (tgieb) 1 enable interrupt requests (tgib) due to the tgfb bit 0 disable interrupt requests (tgia) due to the tgfa bit (initial value) 0 tgr interrupt enable a (tgiea) 1 enable interrupt requests (tgia) due to the tgfa bit appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 641 of 716 rej09b0398-0500 mtu timer status register 2 (tsr2) h'ffff82a5 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name tcfd D tcfu tcfv D D tgfb tgfa initial value 1 1 0 0 0 0 0 0 r/w r r r/(w) * r/(w) * r r r/(w) * r/(w) * note: * only 0 writes to clear the flags are possible. bit name value description 0 tcnt counts down 7 count direction flag (tcfd) 1 tcnt counts up (initial value) 0 clear condition: with tcfu = 1, a 0 write to tcfu after reading it (initial value) 5 underflow flag (tcfu) 1 set condition: when the tcnt value underflows (h'0000 h'ffff) 0 clear condition: with tcfv = 1, a 0 write to tcfv after reading it (initial value) 4 overflow flag (tcfv) 1 set condition: when the tcnt value overflows (h'ffff h'0000) 0 clear condition: with tgfb = 1, a 0 write to tgfb following a read (initial value) 1 input capture/output compare flag b (tgfb) 1 set conditions: ? when tgrb is functioning as an output compare register (tcnt = tgrb) ? when tgrb is functioning as input capture (the tcnt value is sent to tgrb by the input capture signal) 0 clear condition: with tgfa = 1, a 0 write to tgfa following a read * (initial value) 0 input capture/output compare flag a (tgfa) 1 set conditions: ? when tgra is functioning as an output compare register (tcnt = tgra) ? when tgra is functioning as input capture (the tcnt value is sent to tgra by the input capture signal) note: * cleared by dmac transfer due to tgfa. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 642 of 716 rej09b0398-0500 mtu timer counters 2 (tcnt2) h'ffff82a6 16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w timer general register 2 (tgr2) h'ffff82a8 (2a) h'ffff82aa (2b) 16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w timer start register (tstr) h'ffff8240 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name D D D D D cst2 cst1 cst0 initial value 0 0 0 0 0 0 0 0 r/w r r r r r r/w r/w r/w bit name value description 0 tcntn count is halted (initial value) 2 to 0 counter start 2 to 0 (cst2 to cst0) 1 tcntn count note: n = 2 to 0 if 0 is written to the cst bit during operation with the tioc pin in output status, the counter stops, but the tioc pin output compare output level is maintained. if a write is done to the tior register while the cst bit is a 0, the pin output level is updated to the established initial output value. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 643 of 716 rej09b0398-0500 mtu timer synchro register (tsyr) h'ffff8241 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name D D D D D sync2 sync1 sync0 initial value 0 0 0 0 0 0 0 0 r/w r r r r r r/w r/w r/w bit name value description 0 timer counter (tcntn) independent operation (tcntn preset/clear unrelated to other channels) (initial value) 2 to 0 timer synchronization 2 to 0 (sync2 to sync0) 1 timer counter synchronous operation * 1 tcntn synchronous preset/ synchronous clear * 2 possible notes: n = 2 to 0 1. minimum of two channel sync bits must be set to 1 for synchronous operation. 2. tcnt counter clear sources (cclr2 to cclr0 bits of the tcr register) must be set in addition to the sync bit in order to have clear synchronization. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 644 of 716 rej09b0398-0500 wdt timer counter (tcnt) h'ffff8610 (write) * 1 h'ffff8611 (read) * 2 D bit item 7 6 5 4 3 2 1 0 bit name initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w notes: 1. write by word transfer. it cannot be written in byte or longword. 2. read by byte transfer. it cannot be read in word or longword. timer control/status register (tcsr) h'ffff8610 D bit item 7 6 5 4 3 2 1 0 bit name ovf wt/ it tme D D cks2 cks1 cks0 initial value 0 0 0 0 0 0 0 0 r/w r/(w) * r/w r/w r r r/w r/w r/w note: * the tcsr differs from other registers in that it is more difficult to write to. see section 11.2.4, register access, for details. bit name value description 0 no overflow of tcnt in interval timer mode (initial value) cleared by reading ovf, then writing 0 in ovf 7 overflow flag (ovf) 1 tcnt overflow in the interval timer mode 0 interval timer mode: interval timer interrupt request to the cpu when tcnt overflows (initial value) 6 timer mode select (wt/ it ) 1 watchdog timer mode: wdtovf signal output externally when tcnt overflows * 1 0 timer disabled: tcnt is initialized to h'00 and count-up stops (initial value) 5 timer enable (tme) 1 timer enabled: tcnt starts counting. a wdtovf signal or interrupt is generated when tcnt overflows. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 645 of 716 rej09b0398-0500 wdt description bit name value clock source overflow interval * 2 ( = 28.7 mhz) 0 /2 (initial value) 17.9 s 0 1 /64 573.4 s 0 /128 1.1 ms 0 1 1 /256 2.3 ms 0 /512 4.6 ms 0 1 /1024 9.2 ms 0 /4096 36.7 ms 2 to 0 clock select 2 to 0 (cks2 to cks0) 1 1 1 /8192 73.4 ms notes: 1. section 11.2.3, reset control/status register (rstcsr), describes in detail what happens when tcnt overflows in the watchdog timer mode. 2. the overflow interval listed is the time from when the tcnt begins counting at h'00 until an overflow occurs. reset control/status register (rstcsr) h'ffff8612 (write) h'ffff8613 (read) D bit item 7 6 5 4 3 2 1 0 bit name wovf rste D D D D D D initial value 0 0 0 1 1 1 1 1 r/w r/(w) * r/w r r r r r r note: * only 0 can be written in bit 7 to clear the flag. bit name value description 0 no tcnt overflow in watchdog timer mode (initial value) cleared when software reads wovf, then writes 0 in wovf 7 watchdog timer overflow flag (wovf) 1 set by tcnt overflow in watchdog timer mode 0 not reset when tcnt overflows (initial value) lsi not reset internally, but tcnt and tcsr reset within wdt. 6 reset enable (rste) 1 reset when tcnt overflows appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 646 of 716 rej09b0398-0500 sci receive data register (rdr) h'ffff81a5 (channel 0) h'ffff81b5 (channel 1) 8/16 bit item 7 6 5 4 3 2 1 0 bit name initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r r transmit data register (tdr) h'ffff81a3 (channel 0) h'ffff81b3 (channel 1) 8/16 bit item 7 6 5 4 3 2 1 0 bit name initial value 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 647 of 716 rej09b0398-0500 sci serial mode register (smr) h'ffff81a0 (channel 0) h'ffff81b0 (channel 1) 8/16 bit item 7 6 5 4 3 2 1 0 bit name c/ a chr pe o/ e stop mp cks1 cks0 initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name value description 0 asynchronous mode (initial value) 7 communication mode (c/ a ) 1 clocked synchronous mode 0 eight-bit data (initial value) 6 character length (chr) 1 seven-bit data * 1 0 parity bit not added or checked (initial value) 5 parity enable (pe) 1 parity bit added and checked * 2 0 even parity * 3 (initial value) 4 parity mode (o/ e ) 1 odd parity * 4 0 one stop bit * 5 (initial value) 3 stop bit length (stop) 1 two stop bits * 6 0 multiprocessor function disabled (initial value) 2 multiprocessor mode (mp) 1 multiprocessor format selected 0 (initial value) 0 1 /4 0 /16 1, 0 clock select 1 and 0 (cks1 and cks0) 1 1 /64 notes: 1. when 7-bit data is selected, the msb (bit 7) of the transmit data register is not transmitted. 2. when pe is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (o/ e ) setting. receive data parity is checked according to the even/odd (o/ e ) mode setting. 3. if even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 4. if odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. 5. in transmitting, a single bit of 1 is added at the end of each transmitted character. 6. in transmitting, two bits of 1 are added at the end of each transmitted character. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 648 of 716 rej09b0398-0500 sci serial control register (scr) h'ffff81a2 (channel 0) h'ffff81b2 (channel 1) 8/16 bit item 7 6 5 4 3 2 1 0 bit name tie rie te re mpie teie cke1 cke0 initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name value description 0 transmit-data-empty interrupt request (txi) is disabled * 1 (initial value) 7 transmit interrupt enable (tie) 1 transmit-data-empty interrupt request (txi) is enabled 0 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are disabled * 2 (initial value) 6 receive interrupt enable (rie) 1 receive-data-full interrupt (rxi) and receive-error interrupt (eri) requests are enabled 0 transmitter disabled * 3 (initial value) 5 transmit enable (te) 1 transmitter enabled * 4 0 receiver disabled * 5 (initial value) 4 receive enable (re) 1 receiver enabled * 6 0 multiprocessor interrupts are disabled (initial value) (normal receive operation) mpie is cleared when the mpie bit is cleared to 0, or the multiprocessor bit (mpb) is set to 1 in receive data. 3 multiprocessor interrupt enable (mpie) 1 multiprocessor interrupts are enabled * 7 receive-data-full interrupt requests (rxi), receive-error interrupt requests (eri), and setting of the rdrf, fer, and orer status flags in the serial status register (ssr) are disabled until data with the multiprocessor bit set to 1 is received. 0 transmit-end interrupt (tei) requests are disabled * 8 (initial value) 2 transmit-end interrupt enable (teie) 1 transmit-end interrupt (tei) requests are enabled * 8 appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 649 of 716 rej09b0398-0500 sci description bit name value asynchronous mode clock synchronous mode 0 0 internal clock, sck pin used for input pin (input signal is ignored) or output pin (output level is undefined) * 10 internal clock, sck pin used for synchronous clock output * 10 0 1 internal clock, sck pin used for clock output * 11 internal clock, sck pin used for synchronous clock output 1 0 external clock, sck pin used for clock input * 12 external clock, sck pin used for synchronous clock input 1, 0 clock enable 1 and 0 (cke1 and cke0) * 9 1 1 external clock, sck pin used for clock input * 12 external clock, sck pin used for synchronous clock input notes: 1. the txi interrupt request can be cleared by reading tdre after it has been set to 1, then clearing tdre to 0, or by clearing tie to 0. 2. rxi and eri interrupt requests can be cleared by reading the rdrf flag or error flag (fer, per, or orer) after it has been set to 1, then clearing the flag to 0, or by clearing rie to 0. 3. the transmit data register empty bit (tdre) in the serial status register (ssr) is locked at 1. 4. serial transmission starts when the transmit data register empty (tdre) bit in the serial status register (ssr) is cleared to 0 after writing of transmit data into the tdr. select the transmit format in the smr before setting te to 1. 5. clearing re to 0 does not affect the receive flags (rdrf, fer, per, orer). these flags retain their previous values. 6. serial reception starts when a start bit is detected in the asynchronous mode, or synchronous clock input is detected in the clock synchronous mode. select the receive format in the smr before setting re to 1. 7. the sci does not transfer receive data from the rsr to the rdr, does not detect receive errors, and does not set the rdrf, fer, and orer flags in the serial status register (ssr). when it receives data that includes mpb = 1, mpb is set to 1, and the sci automatically clears mpie to 0, generates rxi and eri interrupts (if the tie and rie bits in the scr are set to 1), and allows the fer and orer bits to be set. 8. the tei request can be cleared by reading the tdre bit in the serial status register (ssr) after it has been set to 1, then clearing tdre to 0 and clearing the transmit end (tend) bit to 0; or by clearing the teie bit to 0. 9. the sck pin is multiplexed with other functions. use the pin function controller (pfc) to select the sck function for this pin, as well as the i/o direction. 10. initial value. 11. the output clock frequency is the same as the bit rate. 12. the input clock frequency is 16 times the bit rate. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 650 of 716 rej09b0398-0500 sci serial status register (ssr) h'ffff81a4 (channel 0) h'ffff81b4 (channel 1) 8/16 bit item 7 6 5 4 3 2 1 0 bit name tdre rdrf orer fer per tend mpb mpbt initial value 1 0 0 0 0 1 0 0 r/w r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * the only value that can be written is a 0 to clear the flag. bit name value description 0 tdr contains valid transmit data clearing conditions: ? when 0 is written to tdre after reading tdre = 1 ? when dmac writes data in tdr 7 transmit data register empty (tdre) 1 tdr does not contain valid transmit data (initial value) setting conditions: ? power-on reset or standby mode ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr 0 rdr does not contain valid received data (initial value) clearing conditions: ? power-on reset or standby mode ? when 0 is written to rdrf after reading rdrf = 1 ? when dmac reads data from rdr 6 receive data register full (rdrf) 1 rdr contains valid received data setting condition: when serial reception ends normally and receive data is transferred from rsr to rdr appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 651 of 716 rej09b0398-0500 sci bit name value description 0 receiving is in progress or has ended normally * 1 (initial value) clearing conditions: ? power-on reset or standby mode ? when 0 is written to orer after reading orer = 1 5 overrun error (orer) 1 a receive overrun error occurred setting condition: when the next serial reception is completed while rdrf = 1 * 2 0 receiving is in progress or has ended normally * 3 (initial value) clearing conditions: ? power-on reset or standby mode ? when 0 is written to fer after reading fer = 1 4 framing error (fer) 1 a receive framing error occurred * 4 setting condition: when at the end of an sci receive operation the final stop bit of the receive data is checked and its value * 4 is 0 0 receiving is in progress or has ended normally * 5 (initial value) clearing conditions: ? power-on reset or standby mode ? when 0 is written to per after reading per = 1 3 parity error (per) 1 a receive parity error occurred * 6 setting condition: per is set to 1 if the number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (o/ e ) in the serial mode register (smr) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 652 of 716 rej09b0398-0500 sci bit name value description 0 transmission is in progress clearing conditions: ? when 0 is written to tdre after reading tdre = 1 ? when dmac writes data in tdr 2 transmit end (tend) 1 end of transmission (initial value) clearing conditions: ? power-on reset or standby mode ? when the te bit in scr is 0 ? when tdre = at transmission of the last bit of a 1-byte serial transmit character 0 multiprocessor bit value in receive data is 0 * 7 (initial value) 1 multiprocessor bit (mpb) 1 multiprocessor bit value in receive data is 1 0 multiprocessor bit value in transmit data is 0 (initial value) 0 multiprocessor bit transfer (mpbt) 1 multiprocessor bit value in transmit data is 1 notes: 1. the orer flag is not affected and retains their previous values when the re bit in scr is cleared to 0. 2. rdr continues to hold the data received before the overrun error, so subsequent receive data is lost. serial receiving cannot continue while orer is set to 1. in the clock synchronous mode, serial transmitting is disabled. 3. the fer flag is not affected and retains their previous values when the re bit in scr is cleared to 0. 4. when the stop bit length is two bits, only the first bit is checked to see if it is a 1. the second stop bit is not checked. when a framing error occurs, the sci transfers the receive data into the rdr but does not set rdrf. serial receiving cannot continue while fer is set to 1. in the clock synchronous mode, serial transmitting is also disabled. in addition, serial transmission cannot continue in clock synchronous mode. 5. the per flag is not affected and retains their previous values when the re bit in scr is cleared to 0. 6. when a parity error occurs, the sci transfers the receive data into the rdr but does not set rdrf. serial receiving cannot continue while per is set to 1. in the clock synchronous mode, serial transmitting is also disabled. in addition, serial transmission cannot continue in clock synchronous mode. 7. if re is cleared to 0 when a multiprocessor format is selected, the mpb retains its previous value. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 653 of 716 rej09b0398-0500 sci bit rate register (brr) h'ffff81a1 (write) h'ffff81b1 (read) 8/16 bit item 7 6 5 4 3 2 1 0 bit name initial value 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 654 of 716 rej09b0398-0500 a/d (sh7014) a/d data registers a to h (addra to addrh) h'ffff83f0 h'ffff83f2 h'ffff83f4 h'ffff83f6 h'ffff83f8 h'ffff83fa h'ffff83fc h'ffff83fe 8/16 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name D D D D D D ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r r r r r r r r r r r r r r r r a/d control/status regist er (adcsr) h'ffff83e0 8/16 bit item 7 6 5 4 3 2 1 0 bit name adf adie adst cks grp ch2 ch1 ch0 initial value 0 0 0 0 0 0 0 0 r/w r/(w) * r/w r/w r/w r/w r/w r/w r/w note: * only 0 can be written to bit 7 to clear the flag. bit name value description 0 clear conditions: (initial value) ? with adf = 1, by reading the adf flag then writing 0 in adf ? when the dmac is activated by an adi interrupt 7 a/d end flag (adf) 1 set conditions: ? single mode: when a/d conversion ends after conversion for all designated channels * ? scan mode: after one round of a/d conversion for all specified channels 0 disables interrupt requests (adi) after a/d conversion ends (initial value) 6 a/d interrupt enable (adie) 1 enables interrupt requests (adi) after a/d conversion ends appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 655 of 716 rej09b0398-0500 a/d (sh7014) bit name value description 0 a/d conversion halted (initial value) 5 a/d start (adst) 1 ? single mode: start a/d conversion. automatically cleared to 0 after conversion for the designated channel ends. ? scan mode: start a/d conversion. continuous conversion until 0 cleared by software. 0 conversion time = 40 states (high speed a/d converter standard clock = /2) (initial value) 4 clock select (cks) 1 conversion time = 80 states (when /4 is selected) 0 select mode (initial value) 3 group mode (grp) 1 group mode select mode (grp = 0) group mode (grp = 1) 0 an0 (initial value) an0 0 1 an1 an0, an1 0 an2 an0 to an2 0 1 1 an3 an0 to an3 0 an4 an0 to an4 0 1 an5 an0 to an5 0 an6 an0 to an6 2 to 0 channel select 2 to 0 (ch2 to ch0) 1 1 1 an7 an0 to an7 note: * during buffer operation, this is not set until operation of the specified buffer has ended. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 656 of 716 rej09b0398-0500 a/d (sh7014) a/d control register (adcr) h' ffff83e1 8/16 bit item 7 6 5 4 3 2 1 0 bit name D pwr trgs1 trgs0 scan dsmp bufe1 bufe0 initial value 0 0 0 0 0 0 0 0 r/w r r/w r/w r/w r/w r/w r/w r/w bit name value description 0 low power conversion mode (initial value) 6 power (pwr) 1 high speed start mode 0 enable a/d conversion start by software (initial value) 0 1 enables a/d conversion start by mtu conversion start trigger 0 5, 4 timer trigger select 1, 0 (trgs1, trgs0) 1 1 reserved 0 single mode (initial value) 3 scan mode (scan) 1 scan mode 0 normal sampling operation (initial value) 2 simultaneous sampling (dsmp) 1 simultaneous sampling operation 0 normal operation (initial value) 0 1 addra and addrb buffer operation: conversion result addra addrb 0 addra and addrc, also addrb and addrd buffer operation: conversion result 1 addra addrc, conversion result 2 addrb addrd (addrc and addrd are buffer registers) 1, 0 buffer enable 1, 0 (bufe1, bufe0) 1 1 addra to addrd buffer operation: conversion result addra addrb addrc addrd (addrb to addrd are buffer registers) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 657 of 716 rej09b0398-0500 a/d (sh7016, sh7017) a/d data register a to d (addra to addrd) h'ffff8420 h'ffff8422 h'ffff8424 h'ffff8426 8/16 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 D D D D D D initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r r r r r r r r r r r r r r r r a/d control/status register (adcsr) h'ffff8428 8/16 bit item 7 6 5 4 3 2 1 0 bit name adf adie adst scan cks ch2 ch1 ch0 initial value 0 0 0 0 0 0 0 0 r/w r/(w) * r/w r/w r/w r/w r/w r/w r/w note: * only 0 can be written to bit 7 to clear the flag. bit name value description 0 clear conditions: (initial value) 1. writing 0 to adf after reading adf with adf = 1 2. when registers of the mid-speed converter are accessed after the dmac is activated by adi interrupt 7 a/d end flag (adf) 1 set conditions: 1. single mode: when a/d conversion is complete 2. scan mode: when a/d conversion of all designated channels are complete 0 disables interrupt request (adi) due to completion of a/d conversion (initial value) 6 a/d interrupt enable (adie) 1 enables interrupt request (adi) due to completion of a/d conversion appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 658 of 716 rej09b0398-0500 a/d (sh7016, sh7017) bit name value description 0 a/d conversion halted (initial value) 5 a/d start (adst) 1 1. single mode: starts a/d conversion. automatically clears to 0 when conversion of the designated channel is complete 2. scan mode: starts a/d conversion. continuous conversion until cleared to 0 by the software 0 single mode (initial value) 4 scan mode (scan) 1 scan mode 0 conversion time = 266 states (max) (initial value) 3 clock select (cks) 1 conversion time = 134 states (max) single mode scan mode 0 an0 (initial value) an0 0 1 an1 an0, an1 0 an2 an0 to an2 0 1 1 an3 an0 to an3 0 an4 an4 0 1 an5 an4, an5 0 an6 an4 to an6 2 to 0 channel select 2 to 0 (ch2 to ch0) 1 1 1 an7 an4 to an7 a/d control register (adcr) h'ffff8429 8/16 bit item 7 6 5 4 3 2 1 0 bit name trge D D D D D D D initial value 0 1 1 1 1 1 1 1 r/w r/w r r r r r r r bit name value description 0 disables a/d conversion start of mtu trigger (initial value) 7 trigger enable (trge) 1 starts a/d conversion on mtu trigger appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 659 of 716 rej09b0398-0500 cmt compare match timer start regi ster (cmstr) h'ffff83d0 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r r item 7 6 5 4 3 2 1 0 bit name D D D D D D str1 str0 initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r/w r/w bit name value description 0 cmcnt1 count operation halted (initial value) 1 count start 1 (str1) 1 cmcnt1 count operation 0 cmcnt0 count operation halted (initial value) 0 count start 0 (str0) 1 cmcnt0 count operation compare match timer control/status register (cmcsr) h'ffff83d2 (channel 0) h'ffff83d8 (channel 1) 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r r item 7 6 5 4 3 2 1 0 bit name cmf cmie D D D D cks1 cks0 initial value 0 0 0 0 0 0 0 0 r/w r/(w) * r/w r r r r r/w r/w note: * the only value that can be written is a 0 to clear the flag. bit name value description 0 cmcnt and cmcor values have not matched clear condition: write a 0 to cmf after reading a 1 from it (initial value) 7 compare match flag (cmf) 1 cmcnt and cmcor values have matched 0 compare match interrupts (cmi) disabled (initial value) 6 compare match interrupt enable (cmie) 1 compare match interrupts (cmi) enabled appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 660 of 716 rej09b0398-0500 cmt bit name value description 0 0 /8 (initial value) 0 1 /32 1 0 /128 1, 0 clock select 1, 0 (cks1, cks0) 1 1 /512 compare match timer counter (cmcnt) h'ffff83d4 (channel 0) h'ffff83da (channel 1) 8/16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w compare match timer constant register (cmcor) h'ffff83d6 (channel 0) h'ffff83dc (channel 1) 8/16/32 bit item 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit name initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 661 of 716 rej09b0398-0500 pfc port a i/o register l (paiorl) h'ffff8386 h'ffff8387 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name pa15ior pa14ior * pa13ior * pa12ior * pa11ior * pa10ior * pa9ior pa8ior initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name pa7ior pa6ior pa5ior pa4ior pa3ior pa2ior pa1ior pa0ior initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w note: * reserved bit on the sh7014. port a control register l1 (pacrl1) h'ffff838c h'ffff838d 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name D pa15md D pa15md * 2 D pa15md * 2 D pa15md * 2 initial value 0 0(1) * 1 0 0 0 0 0 0 r/w r r/w r r/w r r/w r r/w item 7 6 5 4 3 2 1 0 bit name D pa15md * 2 D pa15md * 2 pa9md1 pa9md0 pa8md1 pa8md0 initial value 0 0 0 0 0 0 0 0 r/w r r/w r r/w r/w r/w r/w r/w notes: 1. bit 14 is initialized to 1 in extended mode. 2. reserved bit on the sh7014. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 662 of 716 rej09b0398-0500 pfc bit name value description 0 general input/output (pa15) (single chip mode initial value) 14 pa15 mode (pa15md) 1 clock output (ck) (extended mode initial value) 0 general input/output (pa14) ( rd in on-chip rom invalid mode) (initial value) 12 pa14 mode (pa14md) 1 read output ( rd ) (pa14 in single chip mode) 0 general input/output (pa13) ( wrh in on-chip rom invalid mode) (initial value) 10 pa13 mode (pa13md) 1 most significant side write output ( wrh ) (pa13 in single chip mode) 0 general input/output (pa12) ( wrl in on-chip rom invalid mode) (initial value) 8 pa12 mode (pa12md) 1 least significant side write output ( wrl ) (pa12 in single chip mode) 0 general input/output (pa11) ( cs1 in on-chip rom invalid mode) (initial value) 6 pa11 mode (pa11md) 1 chip select output ( cs1 ) (pa11 in single chip mode) 0 general input/output (pa10) ( cs0 in on-chip rom invalid mode) (initial value) 4 pa10 mode (pa10md) 1 chip select output ( cs0 ) (pa10 in single chip mode) 0 general input/output (pa9) (initial value) 0 1 mtu timer clock input (tclkd) 0 interrupt request input ( irq3 ) 3, 2 pa9 mode 1, 0 (pa9md1 and pa9md0) 1 1 reserved 0 general input/output (pa8) (initial value) 0 1 mtu timer clock input (tclkc) 0 interrupt request input ( irq2 ) 1, 0 pa8 mode 1, 0 (pa8md1 and pa8md0) 1 1 reserved appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 663 of 716 rej09b0398-0500 pfc port a control register l2 (pacrl2) h'ffff838e h'ffff838f 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name pa7md1 pa7md0 pa6md1 pa6md0 pa5md1 pa5md0 D pa4md initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r r/w item 7 6 5 4 3 2 1 0 bit name D pa3md pa2md1 pa2md0 D pa1md D pa0md initial value 0 0 0 0 0 0 0 0 r/w r r/w r/w r/w r r/w r r/w bit name value description 0 general input/output (pa7) (initial value) 0 1 mtu timer clock input (tclkb) 0 chip select output ( cs3 ) (pa7 in single-chip mode) 15, 14 pa7 mode 1, 0 (pa7md1 and pa7md0) 1 1 reserved 0 general input/output (pa6) (initial value) 0 1 mtu timer clock input (tclka) 0 chip select output ( cs2 ) (pa6 in single-chip mode) 13, 12 pa6 mode 1, 0 (pa6md1 and pa6md0) 1 1 reserved 0 general input/output (pa5) (initial value) 0 1 serial clock input/output (sck1) 0 dma transfer request received input ( dreq1 ) (pa5 in single-chip mode) 11, 10 pa5 mode 1, 0 (pa5md1 and pa5md0) 1 1 interrupt request input ( irq1 ) 0 general input/output (pa4) (initial value) 8 pa4 mode (pa4md) 1 transmit data output (txd1) 0 general input/output (pa3) (initial value) 6 pa3 mode (pa3md) 1 receive data input (rxd1) 0 general input/output (pa2) (initial value) 0 1 serial clock input/output (sck0) 0 dma transfer request received input ( dreq0 ) (pa2 in single-chip mode) 5, 4 pa2 mode 1, 0 (pa2md1 and pa2md0) 1 1 interrupt request input ( irq0 ) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 664 of 716 rej09b0398-0500 pfc bit name value description 0 general input/output (pa1) (initial value) 2 pa1 mode (pa1md) 1 transmit data output (txd0) 0 general input/output (pa0) (initial value) 0 pa0 mode (pa0md) 1 receive data input (rxd0) port b i/o register (pbior) h'ffff8394 h'ffff8395 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name D D D D D D pb9ior pb8ior initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r/w r/w item 7 6 5 4 3 2 1 0 bit name pb7ior pb6ior pb5ior pb4ior pb3ior pb2ior pb1ior * pb0ior * initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w note: * reserved bit on the sh7014. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 665 of 716 rej09b0398-0500 pfc port b control register 1 (pbcr1) h'ffff8398 h'ffff8399 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r r item 7 6 5 4 3 2 1 0 bit name D D D D pb9md1 pb9md0 pb8md1 pb8md0 initial value 0 0 0 0 0 0 0 0 r/w r r r r r/w r/w r/w r/w bit name value description 0 general input/output (pb9) (initial value) 0 1 interrupt request input ( irq7 ) 0 address output (a21) (pb9 in single-chip mode) 3, 2 pb9 mode 1, 0 (pb9md1 and pb9md0) 1 1 reserved 0 general input/output (pb8) (initial value) 0 1 interrupt request input ( irq6 ) 0 address output (a20) (pb8 in single-chip mode) 1, 0 pb8 mode 1, 0 (pb8md1 and pb8md0) 1 1 wait state request input ( wait ) (pb8 in single-chip mode) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 666 of 716 rej09b0398-0500 pfc port b control register 2 (pbcr2) h'ffff839a h'ffff839b 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name pb7md1 pb7md0 pb6md1 pb6md0 pb5md1 pb5md0 pb4md1 pb4md0 initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name pb3md1 pb3md0 pb2md1 pb2md0 D pb1md * D pb0md * initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r r/w r r/w note: * reserved bit on the sh7014. bit name value description 0 general input/output (pb7) (initial value) 0 1 reserved 0 address output (a19) (pb7 in single-chip mode) 15, 14 pb7 mode 1, 0 (pb7md1 and pb7md0) 1 1 reserved 0 general input/output (pb6) (initial value) 0 1 reserved 0 address output (a18) (pb6 in single-chip mode) 13, 12 pb6 mode 1, 0 (pb6md1 and pb6md0) 1 1 reserved 0 general input/output (pb5) (initial value) 0 1 interrupt request input ( irq3 ) 0 reserved 11, 10 pb5 mode 1, 0 (pb5md1 and pb5md0) 1 1 read/write output (rdwr) 0 general input/output (pb4) (initial value) 0 1 interrupt request input ( irq2 ) 0 reserved 9, 8 pb4 mode 1, 0 (pb4md1 and pb4md0) 1 1 column address strobe ( cash ) (pb4 in single-chip mode) 0 general input/output (pb3) (initial value) 0 1 interrupt request input ( irq1 ) 0 reserved 7, 6 pb3 mode 1, 0 (pb3md1 and pb3md0) 1 1 column address strobe ( casl ) (pb3 in single-chip mode) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 667 of 716 rej09b0398-0500 pfc bit name value description 0 general input/output (pb2) (initial value) 0 1 interrupt request input ( irq0 ) 0 reserved 5, 4 pb2 mode 1, 0 (pb2md1 and pb2md0) 1 1 row address strobe ( ras ) (pb2 in single-chip mode) 0 general input/output (pb1) (a17 in on-chip rom invalid mode) (initial value) 2 pb1 mode (pb1md) 1 address output (a17) (pb1 in single chip mode) 0 general input/output (pb0) (a16 in on-chip rom invalid mode) (initial value) 0 pb0 mode (pb0md) 1 address output (a16) (pb0 in single chip mode) port c i/o register (pcior) (sh7016, sh7017) h'ffff8396 h'ffff8397 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name pc15ior pc14ior pc13ior pc12ior pc11ior pc10ior pc9ior pc8ior initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name pc7ior pc6ior pc5ior pc4ior pc3ior pc2ior pc1ior pc0ior initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 668 of 716 rej09b0398-0500 pfc port c control register (pccr) (sh7016, sh7017) h'ffff839c h'ffff839d 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name pc15md pc14md pc13md pc12md pc11md pc10md pc9md pc8md initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name pc7md pc6md pc5md pc4md pc3md pc2md pc1md pc0md initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name value description 0 general input/output (pc15) (a15 in on-chip rom invalid mode) (initial value) 15 pc15 mode (pc15md) 1 address output (a15) (pc15 in single chip mode) 0 general input/output (pc14) (a14 in on-chip rom invalid mode) (initial value) 14 pc14 mode (pc14md) 1 address output (a14) (pc14 in single chip mode) 0 general input/output (pc13) (a13 in on-chip rom invalid mode) (initial value) 13 pc13 mode (pc13md) 1 address output (a13) (pc13 in single chip mode) 0 general input/output (pc12) (a12 in on-chip rom invalid mode) (initial value) 12 pc12 mode (pc12md) 1 address output (a12) (pc12 in single chip mode) 0 general input/output (pc11) (a11 in on-chip rom invalid mode) (initial value) 11 pc11 mode (pc11md) 1 address output (a11) (pc11 in single chip mode) 0 general input/output (pc10) a10 in on-chip rom invalid mode) (initial value) 10 pc10 mode (pc10md) 1 address output (a10) (pc10 in single chip mode) 0 general input/output (pc9) (a9 in on-chip rom invalid mode) (initial value) 9 pc9 mode (pc9md) 1 address output (a9) (pc9 in single chip mode) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 669 of 716 rej09b0398-0500 pfc bit name value description 0 general input/output (pc8) a8 in on-chip rom invalid mode) (initial value) 8 pc8 mode (pc8md) 1 address output (a8) (pc8 in single chip mode) 0 general input/output (pc7) (a7 in on-chip rom invalid mode) (initial value) 7 pc7 mode (pc7md) 1 address output (a7) (pc7 in single chip mode) 0 general input/output (pc6) (a6 in on-chip rom invalid mode) (initial value) 6 pc6 mode (pc6md) 1 address output (a6) (pc6 in single chip mode) 0 general input/output (p5) (a5 in on-chip rom invalid mode) (initial value) 5 pc5 mode (pc5md) 1 address output (a5) (pc5 in single chip mode) 0 general input/output (pc4) (a4 in on-chip rom invalid mode) (initial value) 4 pc4 mode (pc4md) 1 address output (a4) (pc4 in single chip mode) 0 general input/output (pc3) (a3 in on-chip rom invalid mode) (initial value) 3 pc3 mode (pc3md) 1 address output (a3) (pc3 in single chip mode) 0 general input/output (pc2) (a2 in on-chip rom invalid mode) (initial value) 2 pc2 mode (pc2md) 1 address output (a2) (pc2 in single chip mode) 0 general input/output (pc1) (a1 in on-chip rom invalid mode) (initial value) 1 pc1 mode (pc1md) 1 address output (a1) (pc1 in single chip mode) 0 general input/output (pc0) (a0 in on-chip rom invalid mode) (initial value) 0 pc0 mode (pc0md) 1 address output (a0) (pc0 in single chip mode) port d i/o register l (pdiorl) (sh7016, sh7017) h'ffff83a6 h'ffff83a7 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name pd15ior pd14ior pd13ior pd12ior pd11ior pd10ior pd9ior pd8ior initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name pd7ior pd6ior pd5ior pd4ior pd3ior pd2ior pd1ior pd0ior initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 670 of 716 rej09b0398-0500 pfc port d control register l (pdcrl) (sh7016, sh7017) h'ffff83ac h'ffff83ad 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name pd15md pd14md pd13md pd12md pd11md pd10md pd9md pd8md initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name pd7md pd6md pd5md pd4md pd3md pd2md pd1md pd0md initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name value description 0 general input/output (pd15) (d15 in on-chip rom invalid mode) (initial value) 15 pd15 mode (pd15md) 1 data input/output (d15) (pd15 in single chip mode) 0 general input/output (pd14) (d14 in on-chip rom invalid mode) (initial value) 14 pd14 mode (pd14md) 1 data input/output (d14) (pd14 in single chip mode) 0 general input/output (pd13) (d13 in on-chip rom invalid mode) (initial value) 13 pd13 mode (pd13md) 1 data input/output (d13) (pd13 in single chip mode) 0 general input/output (pd12) (d12 in on-chip rom invalid mode) (initial value) 12 pd12 mode (pd12md) 1 data input/output (d12) (pd12 in single chip mode) 0 general input/output (pd11) (d11 in on-chip rom invalid mode) (initial value) 11 pd11 mode (pd11md) 1 data input/output (d11) (pd11 in single chip mode) 0 general input/output (pd10) (d10 in on-chip rom invalid mode) (initial value) 10 pd10 mode (pd10md) 1 data input/output (d10) (pd10 in single chip mode) 0 general input/output (pd9) (d9 in on-chip rom invalid mode) (initial value) 9 pd9 mode (pd9md) 1 data input/output (d9) (pd9 in single chip mode) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 671 of 716 rej09b0398-0500 pfc bit name value description 0 general input/output (pd8) (d8 in on-chip rom invalid mode) (initial value) 8 pd8 mode (pd8md) 1 data input/output (d8) (pd8 in single chip mode) 0 general input/output (pd7) (d7 in on-chip rom invalid mode) (initial value) 7 pd7 mode (pd7md) 1 data input/output (d7) (pd7 in single chip mode) 0 general input/output (pd6) (d6 in on-chip rom invalid mode) (initial value) 6 pd6 mode (pd6md) 1 data input/output (d6) (pd6 in single chip mode) 0 general input/output (pd5) (d5 in on-chip rom invalid mode) (initial value) 5 pd5 mode (pd5md) 1 data input/output (d5) (pd5 in single chip mode) 0 general input/output (pd4) (d4 in on-chip rom invalid mode) (initial value) 4 pd4 mode (pd4md) 1 data input/output (d4) (pd4 in single chip mode) 0 general input/output (pd3) (d3 in on-chip rom invalid mode) (initial value) 3 pd3 mode (pd3md) 1 data input/output (d3) (pd3 in single chip mode) 0 general input/output (pd2) (d2 in on-chip rom invalid mode) (initial value) 2 pd2 mode (pd2md) 1 data input/output (d2) (pd2 in single chip mode) 0 general input/output (pd1) (d1 in on-chip rom invalid mode) (initial value) 1 pd1 mode (pd1md) 1 data input/output (d1) (pd1 in single chip mode) 0 general input/output (pd0) (d0 in on-chip rom invalid mode) (initial value) 0 pd0 mode (pd0md) 1 data input/output (d0) (pd0 in single chip mode) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 672 of 716 rej09b0398-0500 pfc port e i/o register (peior) h'ffff83b4 h'ffff83b5 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name pe15ior pe14ior pe13ior pe12ior pe11ior pe10ior pe9ior pe8ior initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name pe7ior pe6ior pe5ior pe4ior pe3ior pe2ior pe1ior pe0ior initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w port e control register 1 (pecr1) h'ffff83b8 h'ffff83b9 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name pe15md1 pe15md0 pe14md1 pe14md0 D D D D initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r r r r item 7 6 5 4 3 2 1 0 bit name D D D D D D D D initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r r bit name value description 0 input/output (pe15) (initial value) 0 1 reserved 0 dma request received output (dack1) (pe15 in single-chip mode) 15, 14 pe15 mode 1, 0 (pe15md1 and pe15md0) 1 1 reserved 0 input/output (pe14) (initial value) 0 1 reserved 0 dma request received output (dack0) (pe14 in single-chip mode) 13, 12 pe14 mode 1, 0 (pe14md1 and pe14md0) 1 1 address hold output ( ah ) (pe14 in single-chip mode) appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 673 of 716 rej09b0398-0500 pfc port e control register 2 (pecr2) h'ffff83ba h'ffff83bb 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name D pe7md D pe6md D pe5md D pe4md initial value 0 0 0 0 0 0 0 0 r/w r r/w r r/w r r/w r r/w item 7 6 5 4 3 2 1 0 bit name pe3md1 pe3md0 pe2md1 pe2md0 pe1md1 pe1md0 pe0md1 pe0md0 initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name value description 0 general input/output (pe7) (initial value) 14 pe7 mode (pe7md) 1 mtu input capture input/output compare output (tioc2b) 0 general input/output (pe6) (initial value) 12 pe6 mode (pe6md) 1 mtu input capture input/output compare output (tioc2a) 0 general input/output (pe5) (initial value) 10 pe5 mode (pe5md) 1 mtu input capture input/output compare output (tioc1b) 0 general input/output (pe4) (initial value) 8 pe4 mode (pe4md) 1 mtu input capture input/output compare output (tioc1a) 0 general input/output (pe3) (initial value) 0 1 mtu input capture input/output compare output (tioc0d) 0 dreq1 request received output (drak1) (pe3 in single-chip mode) 7, 6 pe3 mode 1, 0 (pe3md1 and pe3md0) 1 1 reserved 0 general input/output (pe2) (initial value) 0 1 mtu input capture input/output compare output (tioc0c) 0 dreq1 request received input (pe2 in single-chip mode) 5, 4 pe2 mode 1, 0 (pe2md1 and pe2md0) 1 1 reserved appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 674 of 716 rej09b0398-0500 pfc bit name value description 0 general input/output (pe1) (initial value) 0 1 mtu input capture input/output compare output (tioc0b) 0 dreq0 request received output (drak0) (pe1 in single-chip mode) 3, 2 pe1 mode 1, 0 (pe1md1 and pe1md0) 1 1 reserved 0 general input/output (pe0) (initial value) 0 1 mtu input capture input/output compare output (tioc0a) 0 dreq0 request received output (drak0) (pe0 in single-chip mode) 1, 0 pe0 mode 1, 0 (pe0md1 and pe0md0) 1 1 reserved appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 675 of 716 rej09b0398-0500 i/o port a data register l (padrl) h'ffff8382 h'ffff8383 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name pa15dr pa14dr * pa13dr * pa12dr * pa11dr * pa10dr * pa9dr pa8dr initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name pa7dr pa6dr pa5dr pa4dr pa3dr pa2dr pa1dr pa0dr initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w note: * reserved bit on the sh7014. port b data register (pbdr) h'ffff8390 h'ffff8391 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name D D D D D D pb9dr pb8dr initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r/w r/w item 7 6 5 4 3 2 1 0 bit name pb7dr pb6dr pb5dr pb4dr pb3dr db2dr pb1dr * pb0dr * initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w note: * reserved bit on the sh7014. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 676 of 716 rej09b0398-0500 i/o port c data register (pcdr) (sh7016, sh7017) h'ffff8392 h'ffff8393 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name pc15dr pc14dr pc13dr pc12dr pc11dr pc10dr pc9dr pc8dr initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w port d data register l (pddrl) (sh7016, sh7017) h'ffff83a2 h'ffff83a3 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name pd15dr pd14dr pd13dr pd12dr pd11dr pd10dr pd9dr pd8dr initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w port e data register (pedr) h'ffff83b0 h'ffff83b1 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name pe15dr pe14dr pe13dr pe12dr pe11dr pe10dr pe9dr pe8dr initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w item 7 6 5 4 3 2 1 0 bit name pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 677 of 716 rej09b0398-0500 i/o port f data register (pfdr) h'ffff83b3 8 bit item 7 6 5 4 3 2 1 0 bit name pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr initial value * * * * * * * * r/w r r r r r r r r note: * initial values are dependent on the status of the pins at the time of the reads. appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 678 of 716 rej09b0398-0500 flash flash memory control regi ster 1 (flmcr1) h'ffff8580 8 bit item 7 6 5 4 3 2 1 0 bit name fwe swe esu psu ev pv e p initial value 1/0 0 0 0 0 0 0 0 r/w r r/w r/w r/w r/w r/w r/w r/w bit name value description 0 when a low level is input to the fwp pin (hardware-protected state) 7 flash write enable bit (fwe) 1 when a high level is input to the fwp pin 0 writes disabled (initial value) 6 software write enable bit (swe) 1 writes enabled setting condition: when fwe = 1 0 erase setup cleared (initial value) 5 erase setup bit (esu) 1 erase setup setting condition: when fwe = 1 and swe = 1 0 program setup cleared (initial value) 4 program setup bit (psu) 1 program setup setting condition: when fwe = 1 and swe = 1 0 erase-verify mode cleared (initial value) 3 erase-verify (ev) 1 transition to erase-verify mode 0 program-verify mode cleared (initial value) 2 program-verify (pv) 1 transition to program-verify mode setting condition: when fwe = 1 and swe = 1 0 erase mode cleared (initial value) 1 erase (e) 1 transition to erase mode setting condition: when fwe = 1, swe = 1, and esu = 1 0 program mode cleared (initial value) 0 program (p) 1 transition to program mode setting condition: when fwe = 1, swe = 1, and psu = 1 appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 679 of 716 rej09b0398-0500 flash flash memory control regi ster 2 (flmcr2) h'ffff8581 8 bit item 7 6 5 4 3 2 1 0 bit name fler ? ? ? ? ? ? ? initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r r bit name value description 0 flash memory is operating normally. flash memory program/erase protection (error protection) is disabled. clearing condition: power-on reset (initial value) 7 flash memory error (fler) 1 an error has occurred during flash memory programming/erasing. flash memory program/erase protection (error protection) is enabled. setting condition: see section 18.8.3, error protection. erase block register 1 (ebr1) h'ffff8582 8 bit item 7 6 5 4 3 2 1 0 bit name eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 initial value 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name value description 0 corresponding block is erase-protected (initial value) 7 to 0 eb7 to eb0 1 corresponding block is not erase-protected appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 680 of 716 rej09b0398-0500 flash ram emulation register (ramer) h'ffff8628 8/16/32 bit item 15 14 13 12 11 10 9 8 bit name ? ? ? ? ? ? ? ? initial value 0 0 0 0 0 0 0 0 r/w r r r r r r r r item 7 6 5 4 3 2 1 0 bit name ? ? ? ? ? rams ram1 ram0 initial value 0 0 0 0 0 0 0 0 r/w r r r r r r/w r/w r/w bit name value description 0 emulation not selected program/erase-protection of all flash memory blocks is disabled (initial value) 2 ram select (rams) 1 emulation selected program/erase-protection of all flash memory blocks is enabled bit2 rams bit1 ram1 bit0 ram0 address block name 0 * * h'fff800 to h'fffbff ram area 1 kb 1 0 0 h'01f000 to h'01f3ff eb4 (1 kb) 1 0 1 h'01f400 to h'01f7ff eb5 (1 kb) 1 1 0 h'01f800 to h'01fbff eb6 (1 kb) 1 1 1 h'01fc00 to h'01ffff eb7 (1 kb) legend: *: don't care appendix a on-chip supporting module registers rev.5.00 sep. 27, 2007 page 681 of 716 rej09b0398-0500 power-down state standby control register (sbycr) h'ffff8614 8/16/32 bit item 7 6 5 4 3 2 1 0 bit name sby hiz D D D D D D initial value 0 0 0 1 1 1 1 1 r/w r/w r/w r r r r r r bit name value description 0 executing sleep instruction puts the lsi into sleep mode (initial value) 7 standby (sby) 1 executing sleep instruction puts the lsi into standby mode 0 holds pin status while in standby mode (initial value) 6 port high impedance (hiz) 1 keeps pin at high impedance while in standby mode appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 682 of 716 rej09b0398-0500 appendix b i/o port block diagrams pa r internal data bus res pfc standby paw pandr q r c d q panmd q panior sbycr rxdm q hiz sci pan/rxdm notes: le g end: par: paw: res: port a read si g nal port a write si g nal reset si g nal n = 0, 3 m = 0, 1 figure b.1 pan/rxm block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 683 of 716 rej09b0398-0500 pa r internal data bus res sckmout pfc standby paw pa n d r q c d sbycr intc irqm dmac dreqm sci sckmin q panmd0 q panior q hiz q panmd1 pan/sckm/ dreqm / irqm notes: le g end: pa r : paw : res: port a read si g nal port a write si g nal reset si g nal n = 2, 5 m = 0, 1 figure b.2 pan/sckm/ dreqm / irqm block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 684 of 716 rej09b0398-0500 pa r internal data bus res pfc cs2 , cs3 standby paw pandr q c d q panmd0 q panmd1 q panior q hiz tclka, tclkb sbycr mtu r pa6/tclka/ cs2 , pa7/tclkb/ cs3 note: legend: par: paw: res: port a read signal port a write signal reset signal n = 6, 7 figure b.3 pa6/tclka/ cs2 , pa7/tclkb/ cs3 (sh7014, mask) block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 685 of 716 rej09b0398-0500 q pa7md0 q pa7md1 par res paw c d q pa7dr pfc sbycr we q hiz mtu tclkb cs3 q pa7ior pa7/tclkb/ cs3 on-chip flash memory programmer mode internal data bus standby legend: pa r : paw : res: port a read signal port a write signal reset signal figure b.4 pa7/tclkb/ cs3 block diagram (f-ztat version) appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 686 of 716 rej09b0398-0500 pa r internal data bus res pfc standby paw pa n d r q c d tclkc, tlckd sbycr mtu irq2 , irq3 intc r q panmd0 q panmd1 q panior q hiz pa8/tclkc/ irq2 , pa9/tclkd/ irq3 note: legend: pa r : paw : res: port a read signal port a write signal reset signal n = 8, 9 figure b.5 pan/tclkm/ irqx block diagram (sh7014, mask) appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 687 of 716 rej09b0398-0500 q panmd0 q panmd1 par res paw c d q pandr pfc sbycr oe , ce q hiz mtu tclkc,d intc irq2 , irq3 q panior pa8/tclkc/ irq2 pa9/tclkd/ irq3 on-chip flash memory programmer mode internal data bus standby note: legend: par: paw: res: port a read signal port a write signal reset signal n = 8, 9 figure b.6 pan/tclkm/ irqx block diagram (f-ztat version) appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 688 of 716 rej09b0398-0500 pa r internal data bus res txdm pfc standby paw q panmd q panior q hiz sbycr pandr q c d r pan/txdm notes: legend: par: paw: res: port a read signal port a write signal reset signal n = 1, 4 m = 0, 1 figure b.7 pan/txdm block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 689 of 716 rej09b0398-0500 pa r internal data bus res ck sin g le-chip mode * mcu mode 2 mcu mode 1 mcu mode 0 pfc standby paw sbycr pa15dr q c d r pa15/ck q pa15ior q pa15md q hiz note: le g end: par: paw: res: port a read si g nal port a write si g nal reset si g nal * sh7016, sh7017 only figure b.8 pa15/ck block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 690 of 716 rej09b0398-0500 pa r internal data bus res cs0 , cs1 , wrl , wrh , rd sin g le-chip mode mcu mode 0 mcu mode 1 mcu mode 2 pfc sbycr standby bus ri g ht release paw pandr q c d r q panmd q panior q hiz pan/xxx note: le g end: par: paw: res: port a read si g nal port a write si g nal reset si g nal n = 10 to 14 figure b.9 pan/xxx block diagram (sh7016, sh7017) appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 691 of 716 rej09b0398-0500 pbr pro g rammer mode internal data bus res sin g le-chip mode mcu mode 0 mcu mode 1 mcu mode 2 a16 pfc sbycr standby bus ri g ht release pbw pb0dr q c d r on-chip flash memory * a16 pb0/a16 q pb0mdo q pb0ior q hiz note: le g end: pbr: pbw: res: port b read si g nal port b write si g nal reset si g nal * f-ztat version only figure b.10 pb0/a16 block diagram (sh7016, sh7017) appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 692 of 716 rej09b0398-0500 pbr internal data bus res single-chip mode mcu mode 0 mcu mode 1 mcu mode 2 a17 pfc sbycr standby pbw pb1dr q c d r pb1/a17 q pb1md q pb1ior q hiz legend: pbr: pbw: res: port b read signal port b write signal reset signal figure b.11 pb1/a17 block diagram (sh7016, sh7017) appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 693 of 716 rej09b0398-0500 q pbnmd0 q pbnmd1 q pbnior pbr res pbw c d q c r pbndr pfc sbycr q hiz pbn/am am standby internal data bus notes: le g end: pbr: pbw: res: port b read si g nal port b write si g nal reset si g nal n = 6, 7 m = 18, 19 figure b.12 pbn/am block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 694 of 716 rej09b0398-0500 q pbnmd0 q pbnmd1 q pbnior pbr res pbw c d q c pbndr pfc sbycr q hiz pbn/ irqm / casx casl , cash intc irqm internal data bus standby notes: le g end: pbr: pbw: res: port b read si g nal port b write si g nal reset si g nal n = 3, 4 m = 1, 2 figure b.13 pbn/ irq m/ casx block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 695 of 716 rej09b0398-0500 q pb8md0 q pb8md1 q pb8ior pbr res pbw c d q c pb8dr pfc sbycr q hiz a20 bsc wait intc irq6 pb8/ irq6 /a20/ wait internal data bus standby legend: pbr: pbw: res: port b read signal port b write signal reset signal figure b.14 pb8/ irq6 /a20/ wait block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 696 of 716 rej09b0398-0500 q pb9md0 q pb9md1 q pb9ior pbr res pbw c d q c pb9dr pfc sbycr q hiz a21 intc irq7 pb9/ irq7 /a21 internal data bus standby legend: pbr: pbw: res: port b read signal port b write signal reset signal figure b.15 pb9/ irq7 /a21 block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 697 of 716 rej09b0398-0500 pbn/ irqm /xxxx q pbnmd0 q pbnmd1 q pbnior pbr res pbw c d q pbndr ras ,rdwr q hiz pfc sbycr intc irqm internal data bus standby notes: le g end: pbr: pbw: res: port b read si g nal port b write si g nal reset si g nal n = 2, 5 m = 0, 3 figure b.16 pbn/ irqm /xxxx block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 698 of 716 rej09b0398-0500 pcr pro g rammer mode internal data bus res sin g le-chip mode mcu mode 0 mcu mode 1 mcu mode 2 an pfc sbycr standby pcw pcndr q c d r on-chip flash memory * an q pcnmd q pcnior q hiz pcn/an notes: le g end: pcr: pcw: res: port c read si g nal port c write si g nal reset si g nal n = 0 to 15 * f-ztat version only figure b.17 pcn/an block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 699 of 716 rej09b0398-0500 pdr pro g rammer mode internal data bus res sin g le-chip mode mcu mode 0 mcu mode 1 mcu mode 2 dn dout pfc sbycr din standby sleep pdw pdndr q c d r on-chip flash memory * dn q pdnmd0 q pdnior q hiz pdn/dn notes: le g end: pdr: pdw: res: dout: din: port d read si g nal port d write si g nal reset si g nal data bus output timin g si g nal data bus input timin g si g nal n = 0 to 15 * f-ztat version only figure b.18 pdn/dn block diagram (sh7016, sh7017) appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 700 of 716 rej09b0398-0500 per res pew c d q pendr pen q hiz q penior pfc sbycr internal data bus standby note: legend: per: pew: res: port e read signal port e write signal reset signal n = 8 to 13 figure b.19 pen block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 701 of 716 rej09b0398-0500 per res pew c d q pe14dr pe14/dack0/ ah q pe14md0 q hiz q pe14md1 q pe14ior pfc sbycr drak0 ah internal data bus standby le g end: per: pew: res: port e read si g nal port e write si g nal reset si g nal figure b.20 pe14/dack0/ ah block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 702 of 716 rej09b0398-0500 per res pew c d q pe15dr pe15/dack1 q pe15md0 q hiz q pe15md1 q pe15ior pfc sbycr drak1 internal data bus standby le g end: per: pew: res: port e read si g nal port e write si g nal reset si g nal figure b.21 pe15/dack1 block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 703 of 716 rej09b0398-0500 standby pen/tiocxx pew res qd c pendr per pfc sbycr q hiz q penmd q penior internal data bus mtu tioc1a, tioc1b, tioc2a, tioc2b tioc1a, tioc1b, tioc2a, tioc2b note: le g end: per: pew: res: port e read si g nal port e write si g nal reset si g nal n = 4 to 7 figure b.22 pen/tiocxx block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 704 of 716 rej09b0398-0500 standby pen/tiocxx/drakm pew res qd c pendr per pfc sbycr q hiz q penmd0 q penmd1 q penior internal data bus mtu tioc0b tioc0d tioc0b tioc0d drakm notes: le g end: per: pew: res: port e read si g nal port e write si g nal reset si g nal n = 1, 3 m = 0, 1 figure b.23 pen/tiocxx/drakm block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 705 of 716 rej09b0398-0500 standby pen/tiocxx/ dreqm pew res qd c pendr per pfc sbycr q hiz q penmd0 q penmd1 q penior dma dreqm internal data bus mtu tioc0a tioc0c tioc0a tioc0c notes: le g end: per: pew: res: port e read si g nal port e write si g nal reset si g nal n = 0, 2 m = 0, 1 figure b.24 pen/tiocxx/ dreqm block diagram appendix b i/o port block diagrams rev.5.00 sep. 27, 2007 page 706 of 716 rej09b0398-0500 internal data bus standby sbycr q hiz ad ann pfr pfn/ann note: legend: pfr: port f read signal n = 0 to 7 figure b.25 pfn/ann block diagram appendix c pin states rev.5.00 sep. 27, 2007 page 707 of 716 rej09b0398-0500 appendix c pin states c.1 pin states table c.1 pin states in reset, and power-down modes pin modes pin function reset power-down class pin name power-on standby sleep clock ck o h * 1 o system control res i i i wdtovf o o o interrupt nmi i i i irq0 to irq3 , irq6 , irq7 z z i address bus a0 to a21 o z o data bus d0 to d15 z z i/o bus control wait z z i rdwr, ras z o h cash , casl z o h rd h z h cs0 , cs1 h z h cs2 , cs3 z z h wrh , wrl h z h ah z z l dmac dack0, dack1 z o * 1 o drak0, drak1 z o * 1 o dreq0 , dreq1 z z i mtu tioc0a to tioc0d, tioc1a, tioc1b, tioc2a, tioc2b z k * 1 i/o tclka to tclkd z z i sci sck0, sck1 z z i/o txd0, txd1 z o * 1 o rxd0, rxd1 z z i a/d converter an0 to an7 z z i appendix c pin states rev.5.00 sep. 27, 2007 page 708 of 716 rej09b0398-0500 pin modes pin function reset power-down class pin name power-on standby sleep i/o port pa0 to pa9, pa15 z k * 1 k pb0 to pb9 pc0 to pc15 pd0 to pd15 pe0 to pe15 * 2 pf0 to pf7 z z i legend: i: input o: output h: high-level output l: low-level output z: high impedance k: input pin with high impedance, output pin mode maintained. notes: 1. if the standby control register port high-impedence bits are set to 1, output pins become high impedence. 2. when an emulator is used, pe9 and pe11 to pe15 become high-impedance in standby mode. appendix c pin states rev.5.00 sep. 27, 2007 page 709 of 716 rej09b0398-0500 c.2 pin states of bus related signals table c.2 pin settings for on-chip peripheral modules on-chip peripheral module 16-bit space pin name on-chip rom (sh7016/17 only) on-chip ram 8-bit space upper byte lower byte word/ longword cs0 to cs3 h h h h h h ras * 1 h h h h h h cash * 2 h h h h h h casl * 2 h h h h h h rdwr h h h h h h ah l l l l l l rd r h h h h h h w ? h h h h h wrh r h h h h h h w ? h h h h h wrl r h h h h h h w ? h h h h h a21 to a0 address address a ddress address a ddress address d15 to d8 hi-z hi-z hi-z hi-z hi-z hi-z d7 to d0 hi-z hi-z hi-z hi-z hi-z hi-z legend: r: read w: write notes: 1. l asserted in ras down state or refresh state. 2. l asserted in refresh state. appendix c pin states rev.5.00 sep. 27, 2007 page 710 of 716 rej09b0398-0500 table c.3 pin settings fo r normal external space normal external space 16-bit space pin name 8-bit space upper word lower word word/longword cs0 to cs2 valid valid valid valid cs3 h h h h ras * 1 h h h h cash * 2 h h h h casl * 2 h h h h rdwr h h h h ah l l l l rd r l l l l w h h h h wrh r h h h h w h l h l wrl r h h h h w l h l l a21 to a0 address a ddress address address d15 to d8 hi-z data hi-z data d7 to d0 data hi-z data data legend: r: read w: write valid: chip select signal corresponding with accessed area is low; chip select signal in other cases is high. notes: 1. l asserted in ras down state or refresh state. 2. l asserted in refresh state. appendix c pin states rev.5.00 sep. 27, 2007 page 711 of 716 rej09b0398-0500 table c.4 pin settings for multiplex i/o space multiplex i/o space 16-bit space pin name 8-bit space upper by te lower byte word/longword cs0 to cs2 h h h h cs3 l l l l ras * 1 h h h h cash * 2 h h h h casl * 2 h h h h rdwr h h h h ah valid valid valid valid rd r l l l l w h h h h wrh r h h h h w h l h l wrl r h h h h w l h l l a21 to a0 address a ddress address address d15 to d8 hi-z address/da ta address address/data d7 to d0 address/data addres s address/data address/data legend: r: read w: write valid: high output in accordance with ah timing notes: 1. l asserted in ras down mode or refresh mode. 2. l asserted in refresh mode. appendix c pin states rev.5.00 sep. 27, 2007 page 712 of 716 rej09b0398-0500 table c.5 pin settings for dram space dram space 16-bit space pin name 8-bit space upper word lower word word/longword cs0 to cs3 h h h h ras * 1 valid valid valid valid cash * 2 h valid h valid casl * 2 valid h valid valid rdwr r h h h h w l l l l ah l l l l rd r l l l l w h h h h wrh r h h h h w h l h l wrl r h h h h w l h l l a21 to a0 address a ddress address address d15 to d8 hi-z data hi-z data d7 to d0 data hi-z data data legend: r: read w: write valid: asserted (low) at a timing determined by the dram access strobe waveform notes: 1. l asserted in ras down mode or refresh mode. 2. l asserted in refresh mode. appendix d notes when converting the f-ztat application software to the mask-rom versions rev.5.00 sep. 27, 2007 page 713 of 716 rej09b0398-0500 appendix d notes when converting the f-ztat application software to the mask-rom versions please note the following when converting the f-ztat application software to the mask-rom versions. the values read from the internal registers fo r the flash rom of the mask-rom version and f- ztat version differ as follows. status register bit f-ztat version mask-rom version flmcr1 fwe 0: application software running 1: programming 0: is not read out 1: application software running note: this difference applies to all the f-ztat versions and all the mask-rom versions that have different rom size. appendix e product code lineup rev.5.00 sep. 27, 2007 page 714 of 716 rej09b0398-0500 appendix e product code lineup table e.1 sh7014, sh7016, and sh7017 product code lineup product type product code mark code package (package code) sh7014 hd6417014f28 hd6417014f28 112-pin qfp (fp-112) hd6417014rf28 hd6417014rf28 112-pin qfp (fp-112) sh7016 mask rom version hd6437016f28 hd6437016( *** )f28 112-pin qfp (fp-112) sh7017 f-ztat version hd64f7017f28 hd64f7017 112-pin qfp (fp-112) note: ( *** ) is the rom code. appendix f package dimensions rev.5.00 sep. 27, 2007 page 715 of 716 rej09b0398-0500 appendix f package dimensions package dimensions of the sh7014, sh7016, sh7017 (fp-112) are shown in figure f.1. note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. 1.23 1.23 0.10 0.13 0.65 8 ? 0 ? 23.5 23.2 22.9 3.05 0.12 0.17 0.22 0.24 0.32 0.40 0.00 0.30 0.15 0.10 0.25 l 1 z e z d y x c b 1 b p a h d a 2 e d a a c 1 e e l h e 20 1.6 22.9 23.2 23.5 2.70 20 reference symbol dimension in millimeters min nom max 0.5 0.8 1.1 * 1 * 2 * 3 p e d e d 56 57 84 85 29 28 1 112 f ym x z z b h e h d 2 1 1 detail f c l a a a l terminal cross section p 1 1 b c b c p-qfp112-20x20-0.65 2.4g mass[typ.] fp-112/fp-112v prqp0112ja-a renesas code jeita package code previous code figure f.1 package dimensions (fp-112) appendix f package dimensions rev.5.00 sep. 27, 2007 page 716 of 716 rej09b0398-0500 renesas 32-bit risc microcomputer hardware manual sh7014, sh7016, sh7017f-ztat tm publication date: 1st edition, september 1997 rev.5.00, september 27, 2007 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2007. renesas technology corp., all rights reserved. printed in japan. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.0 2-6-2, ote-machi, chiyoda-ku, tokyo, 100-0004, japan sh7014, sh7016, sh7017f-ztat tm hardware manual |
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